(12) United States Patent
`Shimoda
`
`USOO6809706B2
`(10) Patent No.:
`US 6,809,706 B2
`(45) Date of Patent:
`Oct. 26, 2004
`
`(54) DRIVE CIRCUIT FOR DISPLAY DEVICE
`
`(75) Inventor: Masamichi Shimoda, Tokyo (JP)
`
`(73) Assignee: NEC Corporation, Tokyo (JP)
`
`- - -
`c:
`(*) Notice:
`
`-
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 264 days.
`
`(21) Appl. No.: 10/211,534
`(22) Filed:
`Aug. 5, 2002
`(65)
`Prior Publication Data
`US 2003/0030603 A1 Feb. 13, 2003
`Foreign Application Priority Data
`(30)
`Aug. 9, 2001
`(JP) ....................................... 2001-2421.03
`(51) Int. Cl. ............................ G09G 3/10; G09G 3/30;
`G09G 3/36
`(52) U.S. Cl. ............................. 345/55; 345/78; 345/82;
`345/92; 34.5/98; 34.5/100; 315/169.1; 315/169.3
`(58) Field of Search ........................... 345/74.1, 76, 78,
`345/82, 89, 92, 98, 100, 204, 214, 211;
`315/169.1, 169.3, 302
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4/1991 Hanson et al. ............. 345/74.1
`5,008,657 A
`5,266.936 A 11/1993 Saitoh ......................... 345/98
`5,721,563 A
`2/1998 Memida ...................... 345/98
`5,847,515 A * 12/1998 Lee et al. ................ 315/169.1
`6,204,610 B1 * 3/2001 Komiya ................... 315/169.3
`
`8/2001 Cok et al. ................ 315/169.1
`6,278.242 B1
`7/2002 Tanaka ....................... 34.5/211
`6,426,670 B1
`6,433,488 B1 * 8/2002 Bu ................
`... 315/169.3
`6,480,178 B1
`11/2002 Itakura et al. ................ 345/89
`6,525,709 B1 * 2/2003 O'Callaghan - - - - - - - - - - - - - - - - 345/98
`6,528,951 B2 * 3/2003 Yamazaki et al. ....... 315/169.3
`6,590,570 B1 * 7/2003 Maki .......................... 34.5/100
`2002/0030647 A1
`3/2002 Hacket al. ................... 345/82
`* cited by examiner
`Primary Examiner Bipin Shallwala
`ASSistant Examiner David L Lewis
`(74) Attorney, Agent, or Firm McGinn & Gibb, PLLC
`(57)
`ABSTRACT
`A drive circuit drives a display device including a plurality
`of pixels arranged as a matrix. Luminous elements are
`provided for the individual pixels. In this circuit, the lumi
`nous element and a drive transistor for driving the luminous
`element in each of the pixels are Serially connected between
`a first power Supply and a Second power Supply. A first
`Switching transistor Supplies the gate of the drive transistor
`with a control signal for controlling the drive transistor. A
`differential amplifier compares a Voltage at a connection
`point between the luminous element and the drive transistor,
`and a control Voltage which is input in the differential
`amplifier So as to control the luminance of the pixel, thereby
`generating a control Signal. The control Signal is Supplied to
`the gate of the drive transistor via the first Switching tran
`Sistor. A hold capacitor holds a Voltage between the gate and
`the Source of the drive transistor. Thus, the drive circuit does
`not present a luminance unevenness, enables a high grada
`tion display, prevents a decrease of the yield and the aperture
`ratio, and decreases the price and the power consumption.
`12 Claims, 9 Drawing Sheets
`
`
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 001
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 1 of 9
`
`US 6,809,706 B2
`
`F. G. 1 (PRIOR ART )
`
`
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 002
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 2 of 9
`
`US 6,809,706 B2
`
`F G. 2 (PRIOR ART )
`
`1 O2
`
`VDD
`
`C1 O1
`
`T-1 O1
`
`Tr103
`
`C1 O2
`
`Tr-1 O2
`di
`NJ-CURRENT
`PATH
`DURING
`PERIOD (2)
`
`d
`
`Tr-1 O4
`
`1 OO
`
`1 O1
`
`1 O3
`1 O4
`
`104 CONTROL
`-
`LINE
`1 02 DATA LINE - —: VDD
`- - - - Vodata
`
`PERIOD (1)
`
`(2)
`
`(3)
`
`(4)
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 003
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 3 of 9
`
`US 6,809,706 B2
`
`F. G. 4
`
`1 4 SCAN SIGNAL
`
`11 DAC OUTPUT -
`
`1 VOLTAGE OF - - - - - - - - %r
`EL ELEMENT
`
`
`
`SIGNAL FOR
`GATE OF Tr 2
`
`N
`
`- - - Vodata
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 004
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 4 of 9
`
`US 6,809,706 B2
`
`F. G. 6
`
`3.
`o
`
`data
`
`
`
`3.
`
`| data
`
`Vg (V)
`
`V2 V1 V3
`
`F G. 7
`
`Vf (V)
`
`V data
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 005
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 5 of 9
`
`US 6,809,706 B2
`
`F. G. 8
`
`-------------------------------------------------
`
`w
`
`w
`
`SHIFT REGISTER
`
`DATA REGISTER
`
`- 30
`
`LATCH CIRCUIT
`
`23
`
`6bit II . . . I-31
`Gbit II ... I - 32
`11 - . . .
`.
`
`D/A CONVERTER
`
`DIFFERENTIAL AMPLIFER
`
`13-...:
`
`VOD
`
`:-...-12
`
`14
`
`26
`
`PXEL ARRAY
`(m X in MATRIX)
`
`-
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 006
`
`

`

`US. Patent
`
`Oct. 26, 2004
`
`Sheet6 0f9
`
`US 6,809,706 B2
`
`423:;50m.G_n_
`
`UIH#5:5; .x00401NamKimom
`
`
`
`.mmkflomm
`
`.FDQFDO
`
`ljllnlllinllluk'
`53:093Ii53:0Iotjmm
`
`
`
`
`
`|_||||l_li205,z<omE
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 007
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 007
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 7 of 9
`
`US 6,809,706 B2
`
`F G 1 OA
`
`
`
`F G 1 OB
`
`FIG 1 OC
`
`F G 1 OD
`
`CONTROL SIGNAL 1
`
`CONTROL SIGNAL 2
`
`+ - AVf
`v
`
`Vodata-AV
`
`11
`
`Vodata + -
`
`Vodata
`
`12
`
`13
`
`AV Vodata-AV
`
`PERIOD
`(1)
`
`PERIOD
`(2)
`
`DAC OUTPUT 11 H
`SCANNING SIGNAL 14
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 008
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 8 of 9
`
`US 6,809,706 B2
`
`F G 11
`
`
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 009
`
`

`

`U.S. Patent
`
`Oct. 26, 2004
`
`Sheet 9 of 9
`
`US 6,809,706 B2
`
`F G. 12A
`
`-25
`
`VDO
`
`F G, 12B
`
`
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 010
`
`

`

`1
`DRIVE CIRCUIT FOR DISPLAY DEVICE
`
`US 6,809,706 B2
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a drive circuit for a
`luminous element in a display device, and Specifically
`relates to a drive circuit for a display device appropriate for
`driving a current-controlled luminous element Such as
`organic and inorganic EL (Electro Luminescence) elements
`and an LED (Light Emission Diode) whose luminance is
`controlled by a current flowing through it.
`2. Description of the Related Art
`A display device where Scan lines and Signal lines form a
`matrix, and luminous elements Such as organic and inor
`ganic EL elements and LEDs are provided individual inter
`Sections of the Scan lines and the Signal lines to display a
`character as a dot matrix is widely used for a television Set,
`a portable terminal, and an advertising board. Especially,
`Since the elements constituting the pixels are luminous
`elements, this type of display devices do not require a back
`light for illumination while a liquid crystal display device
`requires it, have characteristics Such as a wide view angle,
`and thus are attracting attention. Especially, an active drive
`display device, which includes Switching elements inte
`grated into the individual pixels on the matrix, and holds an
`image represented by the pixels for a certain period, has
`characteristics Such as higher luminance, higher resolution,
`and lower power consumption compared with a passive
`drive display device which includes only luminous
`elements, and thus is especially attracting attention recently.
`For this type of display device, conventionally a drive
`circuit shown in FIG. 1 has been used generally. In this
`conventional drive circuit, a Scan line 201 turns on a
`Switching transistor Tr201, a voltage on the data line 202 is
`written to a hold capacitor C202, and then the drive tran
`Sistor Tr202 is turned on. A current corresponding to con
`ductivity determined by the gate-Source Voltage of the drive
`transistor Tr202 flows through an EL element 200. Namely,
`the Voltage of the data line 202 conducts analog control of
`gradation display. However, Since the channel in a polysili
`con thin film transistor used for the active drive display
`device is polycrystal Silicon, variation of the characteristics
`is remarkably large compared with Single crystal Silicon.
`Thus, when the same gate Voltage is written, the current
`varies depending on the pixels due to the variation of the
`characteristics of the drive transistor Tr202, a luminance
`becomes uneven, and consequently high gradation display
`becomes difficult. To overcome this defect, a drive circuit
`which is not affected by variation in a threshold voltage is
`disclosed on pages 438 to 441 by Sarnoff Corp. in "SID 99
`DIGEST" in 1998 published by Society for Information
`Display.
`The following will describe the operation thereof while
`referring to FIG. 2 and FIG. 3.
`All of thin film transistors (Tr101 to Tr104) are consti
`tuted by P-channel transistors. In a period (1), all of the
`transistors Tr101 to Tr104 are turned on, and a current flows
`through an EL element 100. In a period (2), the transistor
`Tr104 turns off, a current flows on a path indicated by an
`arrow until the gate-Source Voltage Vgs of the transistor
`Tr102 reaches a threshold voltage Vth, and the transistor
`Tr102 turns off when Vgs=Vth. In a period (3), the transistor
`Tr103 turns off, and the voltage on a data line 102 changes
`VDD to Vdata. Then, the voltage generated between the
`both ends of the capacitor C102, namely the gate-Source
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`2
`voltage Vgs of the transistor Tr102, becomes -VDD+Vth
`C101 (VDD-Vdata)/(C101+C102). In a period (4), when
`the transistor Tr104 turns on, current I flowing through the
`EL element 100 is (Wu Cox/2-L)-((-C102. VDD
`C101 Vdata)/(C101+C102)) if the transistor Tr102 is used
`in the Saturation region. Since this expression does not
`include the threshold voltage Vith, even if there is a variation
`in Vith, the current is not affected. Here, “L” and “W'
`respectively indicate channel length and channel width of
`the transistor Tr102, “u' is mobility, and “Cox' is gate
`dielectric film capacitance.
`However, in this drive circuit, as the equation for calcu
`lating the current I described above clearly shows, though
`the variation of the threshold of the transistor can be
`compensated, the mobility of the transistor cannot be com
`pensated. Thus, when there is a variation in the mobility, the
`luminance of the individual pixels fluctuates, and uneven
`neSS in the luminance occurs. Also, Since this drive circuit
`requires two controlliens in addition to the four transistors,
`the two capacitors, the Scan line, and the data line, a pixel
`circuit becomes complicated, and the following two prob
`lems also occur.
`The first problem is that probability of defects in produc
`tion increases due to the complicated pixel circuit, and thus
`the yield decreases.
`The Second problem is that it is necessary to increase the
`current to provide intended luminance due to decrease of
`aperture ratio, and thus the power consumption increases.
`SUMMARY OF THE INVENTION
`An object of the present invention is to provide a drive
`circuit for a display device which does not present a lumi
`nance unevenneSS even when there is a variation in charac
`teristics of a transistor, and to provide a drive circuit for a
`display device enabling a high gradation display.
`In addition, another object of the present invention is to
`provide a drive circuit for a display device which prevents
`decrease in the yield and the aperture ratio, and decreases the
`price and the power consumption by Simplifying the con
`Stitution of a pixel circuit.
`A drive circuit for a display device according to the
`present invention is a drive circuit for use in a display device
`with a plurality of pixels arranged as a matrix and luminous
`elements being provided for the individual pixels. The drive
`circuit comprises:
`drive transistors provided for the individual luminous
`elements and driving Said luminous elements, Said
`luminous element and Said drive transistor in each of
`the pixels being Serially provided between a first power
`Supply and a Second power Supply;
`a first Switching transistor provided in each of the pixels
`for Supplying a gate of Said drive transistor with a
`control Signal for controlling Said drive transistor, and
`a differential amplifier for comparing a Voltage of a
`connection point between said luminous element and
`Said drive transistor in each of Said pixels, and a control
`Voltage input in Said differential amplifier and indicat
`ing luminance of the pixel, and, thereby generating Said
`control Signal, wherein
`Said control Signal is Supplied for the gate of Said drive
`transistor through Said first Switching transistor.
`In this drive circuit for a display device, as another aspect
`of the present invention, a Second Switching transistor may
`Supplies Said differential amplifier with Said Voltage of Said
`connection point between Said luminous element and Said
`drive transistor in each of Said pixels.
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 011
`
`

`

`US 6,809,706 B2
`
`3
`Also, both of Said first Switching transistor and Said
`Second Switching transistor may be controlled by the same
`Second control Signal.
`Said drive circuit for driving a display device may com
`prise a hold capacitor holding a Voltage between the gate and
`the Source of Said drive transistor.
`AS another aspect of the present invention, a circuit for
`canceling an input offset may be provided for the differential
`amplifier.
`AS another aspect of the present invention, the differential
`amplifier may be formed on the same Substrate as the pixel.
`In addition to these constitutions, it is possible to further
`constitute Such that the control Voltage which is Supplied for
`the display device, and indicates the luminance of the pixel
`is applied to the inverted input terminal (-) of the differential
`amplifier, and Simultaneously, the Voltage between the lumi
`nous element and the drive transistor is applied to the
`non-inverted input terminal (+) of the differential amplifier.
`Since the present invention is constituted as described
`above, the first and the Second Switching transistors are
`turned on while a pixel is Selected, and thus a feedback loop
`is formed by the differential amplifier. As a result, the gate
`of the drive transistor is driven such that the voltage of the
`image Signal indicating the luminance information of the
`pixel and the Voltage impressed on the luminous element are
`the same. Thus, even when there is a variation in the
`characteristics of the drive transistors, a variation does not
`present in the currents flowing through the luminous
`elements, and the uniformity of the display increases con
`Sequently.
`
`15
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`drawings. FIG. 4 to FIG. 11 are circuit diagrams showing
`drive circuits for a display device according to a first
`embodiment. The present invention relates to a drive circuit
`for a display device where a plurality of pixels are arranged
`as a matrix, and luminous elements are provided for the
`individual pixels. A luminous element 1 and a drive tran
`sistor Tr2 driving the luminous element 1 are serially
`provided between a first power supply VDD and a second
`power Supply GND. A first Switching transistor Tr1 Supplies
`the gate of the drive transistor Tr2 with a control signal 13
`for controlling the drive transistor Tr2. A differential ampli
`fier 2 compares a Voltage 12 at a connection point Jbetween
`the luminous element 1 and the drive transistor Tr2 with a
`control voltage 11 which is provided for the display device
`and indicates the luminance of the pixel, and then the
`differential amplifier 2 generates the control signal 13. The
`control Signal 13 is Supplied for the gate of the drive
`transistor Tr2 through the first Switching transistor Tr1.
`A hold capacitor C1 holds a Voltage between the gate and
`the source of the drive transistor Tr2. The first Switching
`transistor Tr1 and a Second Switching transistor Tr3 are
`N-channel thin film transistors. The drive transistor Tr2 is a
`P-channel thin film transistor. As for the differential ampli
`fier 2, a DAC output 11 indicating light emission informa
`tion for the EL element 1 (a control voltage which is
`indicating luminance of a pixel, and is Supplied for the
`display device) is Supplied for an inverted input terminal (-),
`a feedback signal 12 indicating a voltage impressed on the
`EL element 1 (the Voltage of the connection point between
`the luminous element and the drive transistor) is Supplied for
`a non-inverted input terminal (+), and an output signal 13,
`which is a product of a difference between the input signals
`and an internal gain of the differential amplifier 2, is
`provided. AS for the Switching transistor Tr1, one electrode
`(Such as the drain) thereof is connected with the output
`Signal 13, the other electrode (Such as the Source) thereof is
`connected with the gate of the drive transistor Tr2, and the
`gate is connected with a Scan Signal 14. When the Switching
`transistor Tr1 is turned on during a horizontal Scan period by
`the Scan Signal 14, the output Signal 13 is Supplied for the
`gate of the drive transistor Tr2. As for the drive transistor
`Tr2, the gate thereof is connected with the source of the
`Switching transistor Tr1, the Source thereof is connected
`with the positive power supply VDD, and the drain is
`connected with the anode of the EL element 1 So as to Supply
`the EL element 1 with a current. The hold capacitor C1 for
`holding the Voltage for one frame period is connected
`between the gate and the source of the drive transistor Tr2.
`AS for the Second Switching transistor Tr3, one electrode
`(such as the drain) thereof is connected with the anode of the
`EL element 1, the other electrode (Such as the Source)
`thereof is connected with the non-inverted input terminal (+)
`of the differential amplifier 2, and the gate is connected with
`the scan signal 14. When the Switching transistor Tr3 is
`turned on during the horizontal Scan period by the Scan
`signal 14, the Switching transistor Tr3 Supplies the differ
`ential amplifier 2 with the Voltage impressed on the EL
`element 1 as the feedback signal 12. The cathode of the EL
`element 1 is connected with the negative electrode of the
`power Supply.
`The following will specifically describe the first embodi
`ment of the present invention.
`First, a constitution of an EL display device 20 including
`the drive circuit of the present invention is described with
`reference to FIG. 8.
`FIG. 8 shows an example of the display device which
`includes pixels arranged as (m) lines by (n) columns, and
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a circuit diagram showing a constitution of a
`conventional drive circuit;
`FIG. 2 is a circuit diagram showing a constitution of a
`conventional drive circuit having a threshold compensation
`feature;
`FIG. 3 is a drawing showing signal waveforms in FIG. 2;
`FIG. 4 is a circuit diagram showing a constitution of a first
`embodiment of a drive circuit of the present invention;
`FIG. 5 is a drawing showing signal waveforms of the
`drive circuit of the present invention;
`FIG. 6 is a drawing showing a gate Voltage/drain current
`characteristic of a drive transistor Tr2;
`FIG. 7 is a drawing showing a Voltage/current character
`istic of an EL element;
`FIG. 8 is a block diagram showing a constitution of an EL
`display device;
`50
`FIG. 9 is a drawing showing signal waveforms in the EL
`display device;
`FIGS. 10A to 10D are drawings showing a differential
`amplifier with an offset-cancel circuit, FIG. 10A is a circuit
`diagram showing the constitution, FIG. 10B and FIG. 10C
`are drawings showing equivalent circuits in individual
`operation modes, FIG. 10D is a drawing showing Signal
`waveforms,
`FIG. 11 is a circuit diagram showing another constitution
`of the first embodiment; and
`FIGS. 12A and 12B are circuit diagrams showing consti
`tutions of a Second embodiment of the present invention.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`Preferred embodiments of the present invention will be
`described in detail with reference to the accompanying
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`55
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`60
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`65
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`LG Display Co., Ltd.
`Exhibit 1015
`Page 012
`
`

`

`US 6,809,706 B2
`
`1O
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`exhibits 64 gradations and 260 thousand colors. The EL
`display device 20 is constituted by a shift register 21, a data
`register 22, a latch circuit 23, a D/A converter 24, a
`differential amplifier 25, and a vertical scan circuit (not
`shown). Circuits for the individual blocks are formed on the
`Same glass Substrate.
`Based on a Start Signal ST and a clock Signal CLK, the
`shift register 21 Supplies the data register 22 with input
`Signals 30 indicating timing for capturing image data Signals
`(D0 to D5). Based on the input signals 30, the data register
`22 captures the continuously Supplied image data Signals
`(D0 to D5) corresponding to one data line, and provides the
`latch circuit 23 with the data. The latch circuit 23 latches
`databased on a latch Signal LE when data corresponding to
`(n) columns are ready in the data register 22, and provides
`the D/A converter 24 with the data. The D/A converter 24
`conducts digital/analog conversion So as to Supply the
`differential amplifier 2 with analog signals (the DAC outputs
`11). In the present embodiment, a D/A converter is provided
`for the individual data line in the D/A converter 24. Namely,
`the DAC output 11 exists for the every data line, and the
`number of the data lines is (n). The differential amplifier 25
`also has differential amplifiers 2 for the individual data lines.
`The differential amplifier 2 receives the DAC output 11, and
`the feedback signal 12 Supplied from a pixel array 26, and
`Supplies the output signal 13.
`The following will describe the operation of the present
`invention.
`First, the operation of the EL display 20 including the
`drive circuit of the present invention will be described based
`on signal waveforms in FIG. 9.
`First, when a start pulse ST rises, the shift register 21
`sequentially supplies the shift clocks 30 (SR1, SR2, ... SRn)
`in one horizontal period in Synchronization with the refer
`ence clock CLK. The data register 22 starts Sampling the
`digital image data (D0 to D5) on the rise of the shift clock
`30, and captures the data on the fall of the shift clock 30. The
`digital image data (D0 to D5) for the data line for the first
`column is captured based on the SR1 Signal, then the digital
`image data (D0 to D5) for the data line for the second
`column is captured based on the SR2 signal, and digital
`image data (D0 to D5) for the data line for the last nth
`column is captured based on the SRn signal. When the
`capturing the digital image data for the nth column is
`finished, the digital image data for the entire data lines are
`captured by the latch circuit 23 on the fall of the latch signal
`LE, and thus the latch output 32 changes. The D/A converter
`24 individually Supplies analog signal (DAC output 11)
`represented by the digital image data of six bits for the
`respective column. The drawing shows a waveform of the
`DAC output 11 for a certain data line. The output changes
`Stepwise as the latch output 32 changes.
`The following will describe the operation of the pixel for
`which the DAC output 11 is supplied with reference to FIG.
`4 and FIG. 5.
`When the scan signal 14 rises, the Switching transistor Tr1
`turns on, and thus the output signal 13 of the differential
`amplifier 2 is supplied for the gate of the drive transistor Tr2.
`Simultaneously, the Switching transistor Tr3 turns on, and
`thus the Voltage impressed on the EL element 1 is Supplied
`for the differential amplifier 2 as the feedback signal 12. As
`a result, a feedback loop along a path comprising the output
`Signal 13, the Switching transistor Tr1, the drive transistor
`Tr2, the EL element 1, the Switching transistor Tr3, and the
`feedback Signal 12 is formed. ASSuming that the Voltage
`supplied from the DAC output 11 is Vdata, since the voltage
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`of the EL element 1 is lower than Vdata when the scan starts,
`the output signal 13 changes toward the GND. As a result,
`the current supplied from the drive transistor Tr2 to the EL
`element 1 increases, and the Voltage of the EL element 1
`increases consequently. When the Voltage of the EL element
`1 increases, the output signal 13 changes toward the power
`supply VDD, the current supplied from the drive transistor
`Tr2 to the EL element 1 decreases, and consequently the
`Voltage of the EL element 1 decreases. Finally, when a Static
`State is reached, the Voltage of the EL element 1 converges
`to a voltage the same as that of the DAC output 11.
`The following will describe an operation when the char
`acteristics of the drive transistor Tr2 vary with reference to
`FIG. 6 and FIG. 7. FIG. 6 is a drawing showing Vg-Id
`characteristic of the drive transistor Tr2. A curve 5 shows
`characteristics intended during the design, and curves (2)
`and (3) show characteristics when the variation is assumed.
`The characteristics shown by the curve (2) have a higher
`threshold voltage Vt, and lower mobility than the charac
`teristics shown by the curve CD. To the contrary, the char
`acteristics shown by the curve (3) have a lower threshold
`Voltage Vt, and higher mobility than the characteristics
`shown by the curve CD. FIG. 7 is a drawing showing a
`current/voltage characteristic of the EL element 1.
`The voltage of the EL element 1 is the same as that of the
`DAC output 11, and its value is Vdata in the static state
`during the Scan period as described above. At this moment,
`a current Idata flows through the EL element 1 as FIG. 7
`shows. Also, at this moment, the gate Voltage is lower then
`the power supply voltage VDD by V1 as FIG. 6 shows. The
`following Section describes a case where the pixel includes
`the drive transistor Tr2 which has the characteristics indi
`cated by the curve (2). Since the feedback loop is formed,
`Similarly the Voltage of the EL element 1 is the same as that
`of the DAC output 11 in the static state. At this moment, the
`gate Voltage converges to a Voltage lower than the power
`supply voltage VDD by V2. When the pixel includes the
`drive transistor Tr2 whose characteristics is shown by the
`CWC (3), the gate Voltage converges to a Voltage lower then
`VDD by V3. Thus, even when the characteristics of the drive
`transistor Tr2 vary, the Voltage impressed on the gate
`changes according to the characteristics, and thus the current
`flowing through the EL element 1 is always Idata. Namely,
`the Voltage indicating the luminance (the DAC output 11) is
`precisely Supplied for the EL element without receiving the
`effect of the variation of the characteristics of the drive
`transistor Tr2.
`FIG. 10 is a circuit diagram showing an example where an
`offset-cancel circuit for the differential amplifier 2 is pro
`vided.
`When there is a difference in the characteristics of tran
`Sistors constituting the differential input in the differential
`amplifier 2, an offset Voltage is generated between the input
`Signals. If this Voltage varies among the differential ampli
`fiers 2 provided for the individual data lines, the variation
`causes an uneven display in the column direction. When a
`data driver including the differential amplifier 2 is consti
`tuted outside a display panel, it is possible to reduce the
`offset Voltage by using a transistor made of Single crystal
`silicon or the like. However, as described above, the poly
`Silicon thin film transistor presents a large variation in the
`characteristics. Thus, it is preferable to arrange the two
`transistors constituting the differential input on regions close
`to each other, thereby unifying their characteristics.
`However, even this method may not sufficiently unify their
`characteristics. If this is the case, it is effective to add a
`circuit for canceling the input offset Voltage.
`
`LG Display Co., Ltd.
`Exhibit 1015
`Page 013
`
`

`

`US 6,809,706 B2
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`FIG. 10A shows a constitution of the differential amplifier
`2 with the offset-cancel circuit.
`The offset-cancel circuit is constituted by Switching tran
`sistors Tr11, Tr12, and Tr13, and an offset compensation
`capacitor C11. In this circuit, all of the Switching transistors
`are N-channel thin film transistors. The following will
`describe the individual connections. As for the offset com
`pensation capacitor C11, one end thereof is connected with
`the DAC output 11, and the other end thereof is connected
`with the inverted input terminal (-) of the differential
`amplifier 2. One electrode (such as the drain) of the Switch
`ing transistor Tr11 is connected with the DAC output 11, the
`other electrode (Such as the Source) is connected with the
`non-inverted input terminal (+), and the gate thereof is
`connected with a control line 1. AS for the Switching
`transistor Tr12, one electrode (Such as the drain) thereof is
`connected with the output signal 13, the other electrode
`(Such as the Source) thereof is connected with the inverted
`input terminal (-), and the gate thereof is connected with the
`control line 1. As for the Switching transistor Tr13, one
`electrode (Such as the drain) thereof is connected with the
`feedback signal 12, the other electrode (such as Source)
`thereof is connected with the non-inverted input terminal
`(+), and the gate thereof is connected with a control line 2.
`The following section describes the operation while refer
`ring to FIGS. 10B to 10D. During a period CD in FIG. 10D,
`the control lines 1 and 2 turn on the Switching transistors
`Tr11 and Tr12, and turn off the Switching transistor Tr13.
`FIG. 10B shows an equivalent circuit during the period CD.
`When there is an offset voltage AV exists between the inputs
`of the differential amplifier 2, since a voltage follower is
`formed, the offset compensation capacitor C11 is charged to
`AV. Then, the Switching transistors Tr11 and Tr12 turn off,
`the Switching transistorTr13 turns on, and thus an equivalent
`circuit shown in FIG. 10C is realized in a period (2). The
`voltage at the inverted input terminal is (Vdata-AV) in the
`differential amplifier 2. The period (2) is the period for
`forming the feedback loop for the pixel circuit as described
`above, and thus the Voltage of the feedback Signal 12
`converges to the Voltage Vdata which is higher than the
`Voltage of the inverted input terminal by the offset Voltage
`of AV in the Static State. As a result, the input offset is
`canceled, and thus the Vdata is impressed on the EL element
`1. With this constitution, as shown in FIG. 10D, it is
`preferable to change the rise of the Scan Signal 14 to the Start
`of the period (2), thereby avoiding Scanning the pixel in the
`period (D.
`In the present embodiment, adding the circuit for cancel
`ing the input offset of the differential amplifier 2 provides the
`effect of preventing the variation of the luminance generated
`respectively on the data lines.
`FIG. 11 shows a case where P-channel MOS FETs are
`used for the transistors Tr1 and Tr3 in FIG. 4. In this case,
`a signal formed by inverting the polarity of the Scan Signal
`14 is supplied for the gate of the transistors Tr1 and Tr2.
`The following will describe a second embodiment of the
`present invention. FIG. 12A and FIG.12B respectively show
`drive circuits for a display device according to the Second
`embodiment of the present invention.
`While the drive transistor Tr2 is a P-channel MOSFET in
`the first embodiment, the drive transistor Tr2 is an N-channel
`MOSFET in FIGS. 12A and 12B. In this constitution, the
`feedback Signal 12 is Supplied for the inverted input terminal
`(-) of the differential amplifier 2 in FIG. 12A, and the
`feedback signal 12 is Supplied for the non-inverted input
`terminal (+) of the differential amplifier 2 in FIG. 12B.
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`In the embodiments of the present invention, although the
`D/A converter and the differential amplifier 2 are provided
`for the individual data lines, it is possible to arrange the
`plurality of data lines as a block, and thus to reduce the
`number of the D/A converters and the differential amplifiers
`2. When the block includes the two data lines, the number
`of the circuits is reduced to /2. When the block includes the
`four data lines, the number of the circuits is reduced to 4.
`In these cases, Switching means is provided between the
`differential amplifier 2 and the pixel array 26, a vertical Scan
`period is time-shared, and thus the data lines in the block are
`Sequentially Selected.
`AS described above, with the present invention, the
`Switching transistors Tr1 and Tr3 turn on, and thus the
`negative feedback loop is formed by the differential ampli
`fier 2 while a pixel is selected. Thus, the operation for
`equalizing the DAC output Signal 11 indicating the lumi
`nance information of the pixel and the Voltage impressed on
`the EL element 1 is conducte