SECOND EDITION
`
`I”; PRINCIPLES OF
`i; i CMOS VLSI DESIGN
`i A Sysimns Pe-I‘spect-ive
`
`
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`NEIL II. E. \VES'I‘L'
`KA ;\ I R AN [‘1 S H EACH-11A N
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`LG Display Co., Ltd.
`Exhibit 1012
`Page 001
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`LG Display Co., Ltd.
`Exhibit 1012
`Page 001
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`Pr‘ncrples ofCMOS VLSI Design by Neil
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`An introduction to VLSI Systems J C: ver 1V and an
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`to
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`Also fin
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`LG Display Co., Ltd.
`Exhibit 1012
`Page 002
`
`

`

`I
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`ADDISON-WESLEY PUBLISHING COMPANY
`
`Reading, Massachusetts • Menlo Park, California • New York
`
`Don Mills, Ontario • Wokingham, England • Amsterdam • Bonn
`
`
`Sydney • Singapore • Tokyo • Madrid , San Juan • Milan • Paris
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 003
`
`

`

`p. cm.
`Includes hihlinn,·�nh references and index.
`
`
`0-201 -53376�6
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`construction 2. Metal oxide <l!Arnll'.t,nrf,
`
`I.
`
`Kamran. . II. Title.
`1992
`621.3'95--dc20
`
`92-16564
`
`1
`
`1
`
`All rights reserved. No part of this publication may be reproduced, stored in a
`
`
`
`retrieval system, or transmitted, in any form or by any means, electronic, mechani­
`cal, photocopying, recording, or otherwise, without the prior written permission of
`the publisher. Printed in the United States of America.
`
`1 2 3 4 5 6 7 8 9 1 O·MA-96959493
`
`'''"''' ''''''''''''"'"''''""�"""""'""""""'h'"hll'II'•-------
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`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 004
`
`

`

`I
`
`To Avril, Melissa, Tammy and Nicky
`
`
`Kylie, Jason
`und Michelle,
`
`.i
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 005
`
`

`

`spent
`worked one year at the Micruelcctronics Center of North
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`duties at Duke and the of North Carolina.
`Wcstc
`B. Sc .. B.E..
`Ph.D. from
`South Australia.
`
`Karnrun
`
`Associate Professor in El!!ctricnl
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`
`
`Gallium Arsenide VLSI
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 006
`
`

`

`many
`were
`cuplurcd on u CMOS VLSI design system. Thus, where po.ssiblc. diagrnms
`
`
`were checked via simulation or m:t cnmpurison. The tendency has been tu
`
`
`include figures where po:.sible ("u picture i!> worth u thousand wordi;") lo
`
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`lrigger the reader's thinking.
`vii
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`LG Display Co., Ltd.
`Exhibit 1012
`Page 007
`
`

`

`-
`
`llurli11gro11, Mass.
`
`N.H.E.W.
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 008
`
`

`

`
`
`Edwards, Chris Terman, Jud Leonard,
`
`number of the circuit
`
`R11rli11gw11, Mu.u.
`
`N.H.E.W.
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 009
`
`

`

`•
`
`x
`
`PREFACE
`
`PRIMITIVES
`
`KEY TO SCHEMATICS USED IN THIS BOOK
`
`n-channel anhancemenl MOS lransislor
`
`p·ohannel enhl!ncemeffl MOS han""IDr
`
`n-dtannel depl&liM MOS lranlillor
`
`1(
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`1(
`•-l>t-4 Juncllon diode
`.. 1..J
`0\ npn llipclar translslOr
`.J~ pnp llipolar lransislor
`BUSSES
`~ bu9 ripper
`
`I resistor
`fa
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`lndu,:lor
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`VOO SLq>ly voltage
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`• \!'.,,: VSS supply voltage ·.· . .-{;,.l . . <
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`E bus Ion/join
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`•,t;;l: lrislalaparl
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`a bus wi<llh spscilies lho wi:llh of lllil bus arxl lhe bus riJlper or btls lor1</join specily
`·· 4; · · ·.· A.B.C.D
`whleh sublilllds ol lhe l!us are a"1ractecl Imm Hie tlUS
`FOO
`a oos can be named by conealelli!ling
`a tlUS lipper can ll•lract eani..1ary liel:ls per conneclio.n,
`..
`names or tield!l
`while e bus lfflll!Dln exllllCIS onG signal par oonneclion
`H""' lhe bus FOO.:l:O• ls made up al lhe sigmls
`~ w
`A.B,C and D wilh F00<3>=A elc .
`.JI: ; A lour bil bus Mlh A<O>wJ: A<ll >!>.Y M2>•• A<3•...,
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`INSff.?, \ti!~ A16bd~r;allod1NST(INST«t5:&>lwilh
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`REPLICATION
`ref)lication it indicaled by a small x and a number on a schem•iiii k:on
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`DEVICE/GA TE SIZES
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`· . ·- · 412
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`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 010
`
`

`

`1
`
`4
`
`5
`
`INTRODUCTION
`CMOS CIRCUITS
`I I
`I Book
`I MOS Transistors
`1.4 MOS Transistor Switches
`1.5 CMOS
`1.5.1 The Inverter
`1.5.2 Combinational
`1.5.3 The NANO Gate
`1.5.4 The NOR Gate
`1.5.5
`1.5.6
`1.5.7
`
`1.6.1 Bchaviorul Representation
`22
`1.6.2 Structural Representation
`24
`1.6.3 Physical Rcrircsentution
`28
`
`xi
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`LG Display Co., Ltd.
`Exhibit 1012
`Page 011
`
`

`

`-
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`CONTENTS
`
`An Examplt:
`1.7. l
`Specification
`1.7.2
`Behavioral Description
`Structural Sp!!cilication
`1.7.3
`1.7.4
`Physical Description
`1.7.5
`Summary
`CMOS Scorecard
`Summary
`References
`
`1.8
`1.9
`I. IO
`
`2
`
`l"
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`MOS TRANSISTOR THEORY
`Introduction
`2.1
`nMOS Enhoncemcnt Transistor
`2.1.1
`pMOS Enhancement Transistor
`2.1.2
`Threshold Voltage
`2.1.3
`2.1.3.1 Threshold Voltage Equations
`2.l.4 Body Effect
`MOS Device Design Equations
`Busic DC Equations
`2.2.1
`Second Order Effects
`2.2.2
`2.2.2.I Threshold Voltage-Body Effect
`2.2.2.2 Subthreshold Region
`2.2.2.3 Channel-length Modulation
`2.'.U.4 Mobility Variation
`2.2.2.5 Fowler-Nordheim Tunnding
`2.2.2.6 Drain Punchthrough
`2.2.2.7 Impact ionization-Hot Electrons
`2.2.3 MOS Models
`Small Signal AC Characteristics
`2.2.4
`The Compli:mcntary CMOS Inverter-DC Characteristics
`~ 1/P1, Ratio
`2.3.1
`2.3.2 Noise Margin
`The CMOS Inverter as an Amplifier
`2.3.3
`Static Loud MOS Inverters
`The Pscudo-nMOS Inverter
`2.4.1
`2.4.2 Unsaturated Loai.J lnvcner.,
`2.4.3
`Saturated Load Inverters
`The Ca!l.1:ooc Inverter
`2.4.4
`2.4.5 TIL Interface Inverter
`The Differential Inverter
`The Trnnsmission Gate
`The Tristate Inverter
`
`2.3
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`2,4
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`' -__ :,
`2.6
`2.7
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`30
`31
`31
`32
`35
`37
`38
`39
`39
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`41
`41
`43
`47
`47
`48
`51
`51
`51
`53
`54
`55
`55
`56
`57
`57
`57
`58
`59
`61
`68
`69
`71
`72
`73
`77
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`so
`80
`81
`86
`91
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`LG Display Co., Ltd.
`Exhibit 1012
`Page 012
`
`

`

`01'."viccs
`Diodes
`
`Transistors
`2Jl.2
`BiCMOS Inverters
`2.8.3
`Summ,iry
`Exercise~
`
`References
`
`Level J Moild
`
`2.9
`2JO
`2.
`12
`
`CMOS PROCESSING TECHNOLOGY
`
`and Diffusion
`
`Metal lntcn:onnccl
`
`J.1.2 Oxidation
`3 . .3
`The Silicon Gate Pmccss
`3 .. 4
`Basic CMOS
`A basic n,wdl CMOS Process
`3.2.
`3.2.2
`The
`Process
`3.2.3
`Twin-Tub Processes
`3.2.4
`Silicon On lnsulalor
`CMOS Process Enhancements
`3.3.1
`Interconnect
`I Metal lntcrconnccL
`3.3.
`3.3.1.2
`3.3.1.3 Loca[ lnlcn:onncct
`3 .. l2 Circuit Elements
`3.3.2.1 Rc!>istors
`3.3.2.2
`Allcrable ROM
`3.3.2.3
`3.3.2.4
`Transistor~
`3.3.2.5 Thin-film Transi.stor~
`3-DCMOS
`
`Scribe Linc
`
`CMOS n-wcll Rules
`
`3.4.:2
`JA.3
`3.4.4
`3.4.5
`SOI Rules
`3.4.6
`3.4.7 Dc~ign Rules-Summ.iry
`Lotchup
`
`3.2
`
`3 .. s
`
`CONTENTS
`
`91
`91
`93
`96
`98
`98
`99
`106
`
`109
`
`123
`12-4
`25
`30
`130
`30
`132
`133
`34
`I J.-l
`34
`136
`136
`139
`140
`141
`]42
`143
`14-1.
`150
`55
`55
`]56
`156
`156
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`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 013
`
`

`

`xiv
`
`CONTENTS
`
`3.5.
`3.5.2
`3.5.3
`
`of
`
`3.6
`
`3.7
`3.8
`3.9
`3.10
`
`mu! Dimension Chci.:ks
`3.6.2 Circuit Extrnction
`
`Exercises
`
`References
`
`CMOS
`
`Process Flow
`
`CIRCUIT CHARACTERIZATION
`AND PERFORMANCE ESTIMATION
`4.1
`I ntrnduction
`Resistance Estim:llion
`4.2
`Resistance of
`4.2.l
`4.2.2 Contact and Via Resistance
`
`4.3
`
`4,4
`4.5
`
`4.3.2
`4.::u
`4.3.4
`4.3.5
`
`4.3.6
`4.3.7
`4.3.8
`
`4.5.2
`4.5.3
`4.5.4
`
`Guide
`
`Characteristics
`Models
`Fall Time
`Rise Time
`
`Input Wuvcfurm Slopi:
`4.5.4.2
`Input Cupucilancc
`4.5.4,:, Switch-Lcvd RC Models
`
`156
`158
`160
`16
`62
`63
`164
`166
`67
`167
`68
`72
`
`115
`75
`76
`
`192
`198
`202
`204
`205
`207
`:ms
`208
`1 0
`2
`213
`214
`2 lfl
`216
`217
`218
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 014
`
`

`

`4.6
`
`,u
`
`,U!
`
`4.9
`4. 0
`
`4.1
`4. 2
`4.13
`
`4.14
`4.15
`4.16
`
`Inverters
`Ca~caded Pseudo nMOS lnverlcrs
`
`4.5.5
`CMOS ,Gate Transistor
`4.6.
`4.6.2
`4.6.3
`Power
`4.7.
`4.7.2
`4.7.3
`4.7.4
`4.7.5
`
`Power
`Conductors
`
`4.8.2
`
`Proccs~ Variation
`Corners
`-1.l0.4
`Issues
`4.10.5
`4.10.6 Power and Clod, Conductor
`4.10.7
`Yield
`
`of MOS Tran~islor Dimension~
`
`Exerci:.cs
`Rcf'crcnccs
`
`CMOS CIRCUIT AND LOGIC DESIGN
`5.
`ln1roduc1ion
`5.2
`CMOS
`5.2.
`5.2.2
`5.2.J
`5.2.4
`
`Gate
`Fan.in and Fan-out
`Typical CMOS NANO and NOR Delays
`Transistor Sizing
`Summary
`
`CONTENTS
`
`xv
`
`223
`225
`226
`226
`228
`229
`23
`23
`233
`235
`236
`237
`238
`239
`240
`240
`243
`243
`2.W
`245
`246
`247
`248
`248
`248
`250
`,. _:,
`250
`
`253
`255
`255
`256
`257
`
`261
`26
`262
`26-1
`267
`271
`272
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 015
`
`

`

`xvi
`
`CONTENTS
`
`:5.3
`
`Basic
`
`of
`
`Gates
`
`The Inverter
`NANO ,md NOR gates
`Gates
`CMOS S1andard Cell
`
`5.3.2
`5.3.3
`5.3.4
`5.3.5
`5.3.6
`5.3.7
`5.3.8
`5.3.9
`5.3.10
`CMOS
`5.4.
`5A.2
`5.4.3
`5.4.4
`5.4.5
`5.4.6
`5.4.7
`
`5.5.3
`
`5.5.5
`:5.5.6
`5.5.7
`5.5.8
`5.5.9
`5.5. 0
`5.5.
`5.5. 2
`5.5. 3
`5.5.14
`5.5. 5
`55.16
`1/0 Structures
`5.6 .. 1 o~wall Orgunizution
`5.6.2
`V00 :mu Vss Puds
`5.6.3 Output Pm.ls
`
`5.4
`
`5.5
`
`:5.6
`
`273
`278
`279
`283
`285
`286
`287
`290
`29
`294
`295
`295
`297
`298
`
`302
`304
`308
`3 0
`3
`3[4
`315
`3 7
`7
`3 !l
`322
`323
`325
`334
`337
`340
`344
`346
`350
`35
`352
`353
`355
`356
`357
`357
`360
`360
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 016
`
`

`

`CONTENTS
`
`5.6.4
`5.6.5
`5.6.6
`5.6.7
`
`Pad,
`Tristulc and Bidirectional Pad\
`Mi~ccllancou~ Pm.ls
`ECL ::md Low
`
`Pad!.
`
`5.1
`5.8
`5.9
`5 0
`
`Exercise'>
`Rcfcrcnci::s
`
`CMOS DESIGN METHODS
`lntmduction
`6.
`6.2
`
`Structured
`
`Gate
`
`Concum:nt
`Sca,of-Gatc and Gutc
`
`6.3
`
`6.2.2
`6.:U
`6.2.-1
`6.2.5
`6.2.6
`6.2.7
`CMOS
`6.3.
`6.3.2
`63J
`6.3.4
`
`6.3.6
`
`6.3.7
`6.3.8
`
`fr3J)J
`
`16
`3M
`365
`367
`368
`370
`
`381
`38
`382
`382
`383
`38-1
`387
`387
`389
`39
`w
`39
`39:!
`395
`400
`-100
`403
`406
`407
`-11 J
`414
`417
`4l7
`-117
`-118
`-120
`-42
`..i::n
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 017
`
`

`

`xviii
`
`CONTENTS
`
`6 5
`
`6J1
`
`<.U
`
`6J!
`
`Methods
`
`Placemenc
`
`6.4.4.2
`6.4.4.3 An Autommic Placement
`
`6.4.2
`6A.3
`6.4.4
`
`6.5.2
`6.5.3
`65.4
`6.5.5
`
`Verification Tools
`Simulation
`6.6.L Circuil-ic\cl Simulation
`6.6.l.2
`Simulalion
`6.6.].3
`6.6.1.4 Swiich-lcvd Simulalion
`6.6.1.5 Mixci.1-mode Simulator~
`6.6.1.6
`
`Verifier~
`
`6.6.2
`6.6.3
`6.6.4
`Extraction
`6.6.5
`6.6.6 Bm:k-Annotalion
`6.6.7
`Vcri licatio n
`Paucrn Generation
`6.6.8
`Economics
`
`Costs
`
`Schedule
`
`6.7.2
`6.7.3
`6.7.4
`6.7.5
`6.7.6
`Data Sheet~
`6Jt
`The
`6.8.2
`Pim.1u1
`6.8.J Description of Opcrution
`DC Spl!cilicution.~
`6.8...1-
`
`army
`
`424
`424
`425
`427
`43
`43
`43
`432
`434
`437
`437
`438
`438
`438
`439
`440
`44
`
`442
`4-B
`444
`444
`445
`445
`446
`447
`448
`448
`448
`448
`449
`450
`450
`
`452
`452
`453
`454
`454
`456
`456
`456
`457
`~57
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 018
`
`

`

`6.9
`6.10
`6.
`
`Exerci~cs
`References
`
`CMOS TESTING
`7.
`
`7.2
`
`Stuck-At Fm1hs
`7 .2.1.2 Short-Circuit and
`
`Automatic Test Pu11crn Generation
`Faul!
`
`7.2.2
`7.2.3
`7.2.4
`7.2.5
`7.2.6
`7.2.7
`7.2.8
`
`Scan-Based Test
`7 .3.3.
`Level Sensitive Sc;m
`7.3.3.
`Serial Scan
`7 .33.2 Partial Scriill Scan
`7.33.3 Parallel Scan
`Sdf-Tcst
`7.:.1.4.
`7.3.4.2
`7 .3.4.3
`
`I1cra1ivc
`
`(LSSD)
`
`and i3ILB0
`
`7 .-t2
`l\.tcmorics
`Random logi1.:
`7.4.3
`System,Lc~'cl Test Tcchni,1ucs
`7.5.1
`Boumlury Scan
`
`CONTENTS
`
`xix
`
`457
`458
`458
`458
`459
`
`465
`
`..J.66
`468
`456
`471
`472
`472
`473
`474
`475
`475
`476
`48
`482
`483
`484
`485
`485
`485
`489
`489
`490
`493
`493
`495
`495
`497
`498
`498
`498
`499
`.500
`5110
`500
`500
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 019
`
`

`

`xx
`
`CONTENTS
`
`lnlruduction
`7.5.
`7.5 .. 2 The Tes! Access Port
`7.5.1.3 The Test Architeccure
`7.5.1.4 The
`Controller
`
`7.6
`7.7
`7.8
`7.9
`
`E.xcrciscs
`References
`
`CMOS SUBSYSTEM DESIGN
`8.1
`!111rrn.lm:1io11
`8.2
`
`Addition.
`
`Addi1ion/Suhtrnction
`8.2.
`Adders
`8.2 .. 2 Bit-Parallel Adder
`8.2 .. 3 Bit Serial Adc.h:rs.
`:mcl
`8.2 . .4 Transmission-Gate Adder
`8.2. .5
`Adders
`8.2. .6
`Adder
`8.2 .. 7
`8.2 .. &
`8.2.l.9
`
`Zero/One DctccLors
`
`lU.2
`8.2.3
`8.2.4
`8.2.5
`
`8.2.6
`8.2.7
`
`8.3
`
`Shifters
`8.2.8
`Memory Elements
`8.3.1
`Read/Write Memory
`
`500
`501
`502
`502
`503
`504
`504
`506
`506
`50B
`508
`508
`
`513
`513
`5 3
`5 5
`5 5
`5 7
`
`520
`524
`526
`532
`532
`53--1
`536
`537
`537
`537
`539
`539
`539
`54
`542
`545
`s.n
`554
`557
`560
`563
`564
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 020
`
`

`

`CONTENTS
`
`xxi
`
`IU.2
`8.3.3
`Control
`8.4.1
`
`!1.4.2
`
`RAM
`8.3.1
`IU .. 2 Rcgisli:r Files
`8.3 . .3 rlFOs, LIFO~. SIPOs
`8.3 . .4 Serial-Access M,•mn,rv
`Read Only Memory
`Comenl·Addrcssablc Memory
`
`Finite-Stale Machines
`8.4.1.1 FSM Design Procedure
`Control Logic Implementation
`PLA Control
`8.4.2.
`8.4.2.2 ROM Conlrol
`8.4.2.3 Muhilcvcl Logic
`8.4.2.4 An Example or Control,
`Logic lmplcmcnlalion
`
`8.5
`8.6
`8,7
`
`Excrc:iscs-
`References
`
`9
`CMOS SVSTEIVI DESIGN EXAMPLES
`9.1
`Jntroduclion
`A Core RISC Microcontrollcr
`9.2
`lnslruction Set
`9.2.1
`9.2.1. l Address Archilecmre
`ALU Class Immuctions
`Control Transfer Instructions
`Archilt!'CIUrc
`Bypassing. Rt!'sult
`Pus:.-urounJ
`9.2.2.2 Cundilional
`9.'.L2 3 Subroutine Cull and Return
`9.l.2.4 1/0 Archil.:clurc
`9.:U Major Logic Blocks
`9.2.3.1 ALU_DP
`9;2.:t2 Register File
`9.2.3.3 PC Da1apath (PC_DPJ
`9.1.3.4 Jnslrm:tion Mcmury
`
`lJ.2.2
`
`or
`
`564
`580
`582
`583
`58.5
`589
`590
`591
`591
`595
`595
`602
`6(1.f
`
`604
`620
`621
`622
`
`625
`
`627
`627
`628
`629
`629
`63[
`633
`634
`
`637
`633
`639
`639
`6--tO
`MO
`651
`654
`656
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 021
`
`

`

`nH
`
`CONTENTS
`
`9.2.3.5
`9.2.3.6
`
`9.'.!.4
`
`functional Verification and
`9.2.5
`A TV Edm Cllnccllcr
`9.3.
`Ghost Cancellation
`9.3.2
`FIR and IIR filters
`9.3.3
`Architecture
`9.3.4
`Architcctun:
`9.3.4.
`Filter Considerations
`Overview
`9.3.4.2
`
`9.3.5
`
`9.3.5.4
`Power Distribution
`
`9.3.6
`9.3.7
`9.3.8
`9.3.9
`A 6,bit Flash AID
`Introduction
`Basic Architecture
`
`Exo:rdscs
`References
`
`INDEX
`
`9J
`
`9.-1
`
`9.5
`9.6
`9.7
`
`656
`658
`663
`666
`669
`672
`672
`674
`676
`677
`677
`678
`680
`680
`685
`685
`689
`689
`690
`692
`694
`69-l
`694
`695
`696
`696
`698
`698
`701
`701
`701
`702
`
`7U3
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 022
`
`

`

`r
`
`I
`
`r-
`
`MOS
`TRANSISTOR
`THEORY
`
`2.1
`
`Introduction
`
`In Chapter I the MOS transistor was introduced in terms or it!> operation a!,
`an ideal switch. In this chaplcr we will examine the characteristic!i of MOS
`transistors in more detail to lay the foundation for predicting the perfora
`mancc of the switches, which is less than ideal. Figure 2. I shows some of the
`symbols that are commonly used for MOS transistors. The symbols in Fig.
`2.1 (a) will be used where it is necessary only to indicate the switch logic
`required to build a function. If the substrate connection needs to be shown.
`the symbols in Fig. 2.l(b) will be used. Figure 2.l(c) shows an example of
`the many symbols that may be encountered in the literature.
`This chapter will concentrate on the static or DC operation of MOS tran.
`sistors. This is the first design goal that must be satisfied to cn,;ure that logic
`gates operate as logic gates. All circuits arc analog in nature and the digital
`abstraction only remains an abstraction a,; long all certain dc!,ign goals arc
`met. Design for Liming constraints ill covered in Chapter 4.
`An MOS transislor is termed a majority-carrier device, in"' hich the cur(cid:173)
`rent in a conducting channel bct\l.cen the source and the drain is modulated
`by a voltage applied to the gate. In an n-type MOS transistor (i.e .. nMOS).
`the majority characters arc electron!.. A positive voltage applied on the gute
`with respect to the substrate enhance,; the number of electrons in the channel
`
`~1-~~
`_)_ ~~ ~,
`
`I
`FIGURE 2.1 MOS transis-
`tor symbols
`
`41
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 023
`
`

`

`42
`
`CHAPTER 2 MOS TRANSISTOR THEORY
`
`(the region immediately under the gale) and hence increases the conductivity
`of the channel. For gate voltages les~ than a threshold value denoted by V1,
`the channel is cut off, thus causing a very low drain-to-source currenl. The
`operation of a p· lype transistor (i.e., pMOS) is analogous to the nMOS tran·
`sistor, with the exception that the majority carriers arc holes and the voltages
`arc negative with respect to the substrate.
`The first parameter of interest that characterizes the switching behavior
`of an MOS device is the threshold , 1oltagc, V1• This is defined as the voltage
`at which an MOS de,·icc begins to conduct ("turn on"). We can graph the rel·
`alive conduction against the difference in gate-to-source voltage in terms of
`the source-to-drain current Ui1) and the gate-to-source voltage (V8). These
`graphs for a fixed drain -source voltage, Vc1." arc shown in Fig. 2.2. It is pos(cid:173)
`sible to make n· device.~ that conduct when the gate vohagc is equal to the
`source ,oltage, while others require a positive difference between gate and
`source voltages to bring about conduction (negative for p-dcvices). Those
`devices that arc normally cut off (i.e., nonconducting) with zero gate bias
`(gate voltage- source voltage ) arc further classed as enhancement-mode
`devices, whereas those de vices that conduct with zero gate bias arc called
`depiction-mode devices. Then-channel transistors and p-channel transistors
`arc the duals of each other; that is, the voltage polarities required for correct
`operation arc the oppo~ite. The thre~hold vollages for n-channcl and
`p-channel devices arc denoted by Vw and V11'. respectively.
`
`n-channel enhancement
`
`n-channel depletion
`
`Drain 1 '
`
`Curren!
`(Ids)
`
`I I
`
`---<1,-o-. v,n ---(cid:173)
`
`GDi.-to•Source Voltage (Vgsl
`
`Gate-lo,Source Vollage Ngsl
`
`Gale·to•Source Voltage (V gs)
`
`Gale-lo·Souree Vollage (Vgsl
`
`I l Drain
`
`Currant
`(Ids)
`
`p channe enhancement
`
`0 +Vtp
`
`/ 1 Drain
`
`Curren!
`(ldsl
`
`p-channel deplelion
`
`FIGURE 2.2 Conduction
`characteristics for enhance·
`ment and depletion mode
`MOS transistors (assuming
`fixed Vds)
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 024
`
`

`

`In CMOS technologie~ both n-channet and p-channel transistors arc fab(cid:173)
`ricated on lhe same chip. Furthermore. most CMOS integrated circuils, at
`present, use transistors of the enhancement type.
`
`2.1.1 nMOS Enhancement Transistor
`The structure for an n•channel enhancement- type transistor, shown in Fig.
`2.3, consists of a moderately doped p~typc silicon substrate into which two
`heavily doped 11+ regions, the source and the drain, are diffused. Between
`the!.e two regions there is a narrow region of p•type substrate called the
`clumnel. which is covered by a thin insulating layer of silicon dioxide (Si02)
`called gate oxide. Over this oxide layer is a polycrystalline silicon (polysili(cid:173)
`con) electrode, referred to as the gate. Polycrystalline silicon is silicon that is
`not composed of a single crystal. Since the oxide layer is an insulator, the
`DC current from the gate to channel is essentially zero. Because of the inher(cid:173)
`ent symmetry of the structure, there is no phy!,ical distinction between the
`drain and source regions. Since Si02 has relatively low loss and high dielec(cid:173)
`tric strength, the application of high gate fields is feasible.
`In operation, a positive voltage is applied between the source and the
`drain (Vi1,). With zero gate bia,; (Vg.t = 0), no current flows from source to
`drain because they are effectively insulated from each other by the two
`reversed biased p11 junction\ shown in Fig. 2.3 (indicated by the diode sym(cid:173)
`bols). However, a voltage applied to the gate, which is positive with respect to
`the ~ource and the substrate, produces an electric field £ ncross the substrate,
`which attracts electrons toward the gate and repels holes. If the gate voltage is
`sufficiently large, the region under the gate changes from p-type to n-typc
`(due to accumulation of attracted electron!>) and provides a conduction path
`between the source and the drain. Under such a condition, the surface of the
`underlying p·type silicon is said 10 be i111w1ed. The term 11-clu11111e/ is applied
`to the structure. This concepl is further iJlu,;trated by Fig. 2.4(a), which shows
`the initial distribution of mobile positive holes in a p-type silicon substrate of
`an MOS structure for a voltage, Vg.l"' much les!, than a voltage, V,, which is
`
`_ G_a_ie_~ /gale oxide Drain
`
`i~ e__! •Vds
`
`r / channel
`holes ! ! E f eleclrons l~
`
`p- subslrale -. Subslrate
`
`(Usually V 55)
`
`l
`
`2.1
`
`INTRODUCTION
`
`43
`
`FIGURE 2.3 Physical struc(cid:173)
`ture of an nMOS transistor
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 025
`
`

`

`44
`
`CHAPTER 2 MOS TRANSISTOR THEORY
`
`ACCUMULATION
`
`•
`
`._ ___________ _
`T
`
`(a)
`
`DEPLETION
`
`-
`
`depletion region
`
`~
`
`I
`
`-
`
`INVERSION
`
`Inversion region (n-type)
`
`depletion region
`
`FIGURE 2.4 Accumulation,
`Depletion and Inversion
`modes in an MOS structure.
`
`the threshold voltage. Thb i,; termed the acrnm11/atio11 mode. As Vgs is raised
`above V1 in potential, the holes are repelled causing a depletion region under
`the gate. Now the structure is in the depletio11 mode (Fig. 2.4b). Raising v.~r
`further above V, re~ult\ in electrons being atlracted to the region of the sub(cid:173)
`strate under the gate. A conductive layer of electrons in the p substrate gives
`rise to the name i11w!r,fio11 mode (Fig. 2.4c).
`The difference between a p,r junction that exist, in a bipolar transistor or
`diode (or between the ~ource or drain und substrate) and the inversion layer
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 026
`
`

`

`2.1
`
`INTRODUCTION
`
`45
`
`• •
`
`substrate junction is that in the pn junction, the n-type conductivity is
`brought about by a metallurgical process; that b,, the electrons arc introduced
`into the semiconductor by the introduction of donor ions. In an inversion
`layer substrate junction, the n-type layer is induced by the electric field £
`applied to the gate. Thus, this junction, instead of being a metallurgical junc(cid:173)
`tion, is afield-i11d11ced junction.
`Electrically, an MOS device therefore acts as a voltage-controlled
`switch that conducts initially when the gate-to-source voltage, Vg,{' is equal
`to the threshold voltage, V1• When a voltage V,1j is applied between source
`and drain, with Vg.t = V,, the horizontal and vertical components of the elec(cid:173)
`trical field due to the source-drain voltage and gate-to-substrate voltage
`interact, causing conduction to occur along the channel. The horizontal com(cid:173)
`ponent of the electric field associated with the drain-to-source voltage (i.e.,
`Vds > 0) is responsible for sweeping the electrons in the channel from the
`source toward the drain. As the voltage from drain to source is increased, the
`resbtive drop along the channel begins to change the shape of the channel
`characteristic. This behavior is shown in Fig. 2.5. At the source end of the
`channel, the full gate voltage is effective in inverting the channel. However,
`at the drain end of the channel, only the difference between the gate and
`drain voltages is effective. When the effective gate voltage (V1.i - V1) is
`greater than the drain voltage, the channel becomes deeper as V~P is
`increased. Thb is termed the "linear," "resistive," "nonsaturated," or "unsat(cid:173)
`urated" region, where the channel current l,1s is a function of both gate and
`drain voltages. If V,15 > Vi:s - V,, then Vg,1 < V1 (Vg,f is the gate to drain volt(cid:173)
`the channel no longer reaches
`age), and the channel becomes pinched off-
`the drain. This is illustrated in Fig. 2.5(c). However, in this case, conduction
`is brought about by a drift mechanism of electrons under the influence of the
`positive drain voltage. As the electrons leave the channel, they are injected
`into the drain depiction region and arc subsequently accelerated toward the
`drain. The voltage across the pinched•off channel tends to remain fixed at
`(V85 - V,). This condition is the "saturated" state in which the channel cur(cid:173)
`rent is controlled by the gate voltage and is almost independent of the drain
`voltage. For fixed drain-to-source voltage and fixed gate voltage, the factors
`that influence the level o( drain current, 1.,,1, flowing between source and
`drain (for a given substrate resistivity) arc:
`
`• the distance between source and drain
`• the channel width
`• the threshold voltage V1
`• the thickness of the gate-insulating oxide layer
`• the dielectric constant of the gate insulator
`• the carrier (electron or hole) mobility,µ .
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 027
`
`

`

`46
`
`CHAPTER 2 MOS TRANSISTOR THEORY
`
`J (Nonsarurated Mode,
`
`(b)
`
`{_
`
`FIGURE 2.5 nMOS device
`behavior under the influence
`of different terminal voltages
`
`(C)
`
`(Saturated Mode)
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 028
`
`

`

`2.1
`
`INTRODUCTION
`
`47
`
`The normal conduc1ion charac1cris1ics of an MOS lransistor can be cat(cid:173)
`egorized as follows:
`
`• "Cul•off' region: where the current now is essentially zero (accumu(cid:173)
`lation region).
`• "Nonsaturated" region: weak inversion region where lhe drain current is
`dcpcndem on the gate and the dmin voltage ( with respect to the !>Ubstrate ).
`• "Saturated" region: channel is strongly inverted and the drain current
`flow is ideally independent of the drain,source voltage (slrong inver(cid:173)
`sion region).
`
`An abnormal conduction condition called avalanche breakdown or
`punch-through can occur if very high voltages arc applied to the drain.
`Under these circumslanccs. the gale has no control over the drain current.
`
`2.1.2 pMOS Enhancement Transistor
`So far, our discussions have been primarily dirccled toward nMOS; how(cid:173)
`ever. a reversal of n-type and p· lype regions yields a p-channel MOS 1ransis-
`1or. This is illustrated by Fig. 2.6. Applica1ion of a negative gate voltage
`(w.r.t. source) draws holes into the region below the gate, resulting in the
`channel changing from n-type to p-type. Thus. similar to nMOS, a conduc(cid:173)
`tion path is created between the source and the drain. In this instance. how(cid:173)
`ever, conduction results from the movement of holes (versus electrons) in
`the channel. A negathc drain voltage sweeps holes from the source through
`the channel to the drain.
`
`2.1.3 Threshold Voltage
`The threshold voltage. V1, for an MOS transistor can be defined as the volt(cid:173)
`age applied between the gate and the source of an MOS device below which
`the drain-to-source current l,15 effectively drop!> to zero. The word "cffcc-
`
`Drain
`
`Source
`
`Gale
`
`~·-~.[_J••••,--[=::~~-Vds
`h~os t t E l electrons r
`
`r l·
`
`n-subslrate
`
`I
`
`Subslrale
`(Usually V00 )
`
`FIGURE 2.6 Physical struc(cid:173)
`ture of a pMOS transistor
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 029
`
`

`

`48
`
`CHAPTER 2 MOS TRANSISTOR THEORY
`
`lively" is used because the drain current never really is zero but drops to a
`very small value that may be deemed insignificant for the current application
`(i.e., fast digital CMOS circuits). In general, the threshold voltage is a func·
`tion of a number of parameters including the following:
`
`• Gate conductor material.
`• Gate insulation material.
`• Gate insulator thickness-channel doping.
`• Impurities at the silicon-insulator interface.
`• Voltage between the !>ource and the substrate, V.rb·
`
`In addition, the absolute value of the threshold voltage decreases with an
`increase in temperature. This variation is approximately -4 mV/°C for high
`substrate doping levels, and - 2 mv,~c for low doping levels. 1
`
`2. 1.3. 1 Threshold Voltage Equations
`
`Threshold voltage, V1• may be expressed as
`
`V = V
`
`I
`
`+V
`/ · 11W$
`//,
`
`(2.1)
`
`where V,.,,,,,s is the ideal threshold voltage of an ideal MOS capacitor and Vfl,
`is what is termed the Hat-band voltage. V,,mos is the threshold where there is
`no work function difference between the gate and substrate materials.
`The MOS threshold voltage, V1•11111s, is calculated by considering the
`MOS capacitor structure that forms the gate of the MOS transistor (see for
`example 2 or3). The ideal threshold voltage may be expressed as
`
`V
`t - 11111s
`
`Qb
`= -,,1,. + -
`-'+'1, c
`
`11.r
`
`(2.2)
`
`kTJ (NA) C . h
`w ere '+'1, = q II N; • ox 1st e ox1 c capacitance
`.d
`.
`h
`
`,h
`
`and Qb = J 2e5;'JN,\2<P1, which is called the bulk charge term.
`
`The symbol $1, is the bulk potential. a term that accounts for the doping of the
`substrate. It represents the difference between the Fermi energy level of the
`doped semiconductor and the Fermi energy level of the intrinsic semiconduc(cid:173)
`tor. The intrinsic level is midway between the valence-band edge and the
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 030
`
`

`

`2.1
`
`INTRODUCTION
`
`49
`
`conduction-band edge of the semiconductor. In a p-type semiconductor the
`Fermi level is closer to the valence band, while in an n~typc semiconductor it
`is closer to the conduction band. N,1 is the density of carriers in the doped
`semiconductor substrate, and N; is the carrier concentration in intrinsic
`(undoped) silicon. N, is equal to 1.45 x IO II} cm-3 at 300°K. The lowercase k is
`Boltzmann ·s constant ( 1.380 x 10-23 J/°K). Tis the temperature (°K) and q is
`the electronic charge ( l.602 x 10-19 Coulomb). The expression kT/q equals
`.02586 Volts at 300t>K. The term Esr is the permittivity of silicon ( 1.06 x I 0- 12
`Farads/cm). The term Cox is the gate-oxide capacitance, which is inversely
`proponional to the gate•oxide thickness (t,JX). The threshold voltage, V1•11ws• is
`positive for n-transistors and negative for p-transistors.
`The flatband voltage, V fl, • is given by
`
`(2.3)
`
`The term V fl, is the flat-band voltage. The term Qfc represents the fixed
`charge due to surface states that arise due to imperfections in the silicon(cid:173)
`oxide interface and doping. The term cj>1115 is the work function difference
`between the gate material and the silicon substrate (4>8,11"' - <l>s;), which may
`be calculated for an 11+ gate over a p substrate (the normal way for an n tran·
`sistor) as follows: 4
`
`(2.4a)
`
`where
`
`)5
`.,
`Eg = is the band gap energy of silicon ( 1.16 - .704 x rn-3 T +~ 108
`
`and Tis the temperature (°K). For an 11+ poly gate on an a-substrate (a nor(cid:173)
`mal p-transistor)
`
`Eg
`16
`q>1115 = - ( 2 - 4>11) -"-0.2V (N,1 = lx lO
`
`- 3
`)
`cm
`
`(2.4b)
`
`From these equations it may be seen that for a given gate and !.ubstrate mate(cid:173)
`rial the threshold voltage may be varied by changing the doping concentra(cid:173)
`tion of the substrate (N,1), the oxide capacitance (C0_t). or the surface state
`charge (Q1J. In addition. the temperature variation mentioned above may be
`seen.
`It is often neces!.ary to adjust the native (original) threshold voltage of
`an MOS device. Two common techniques used for the adjuo;tment of the
`threshold voltage entail varying the doping concentration at the silicon-
`
`
`
`
`LG Display Co., Ltd.
`Exhibit 1012
`Page 031
`
`

`

`50
`
`CHAPTER 2 MOS TRANSISTOR THEORY
`
`insulator interface through ion implantation (i.e .. affecting Qfi) or using dif·
`ferent insulating material for the gate (i.e .. affecting C,,x). The former
`approach introduces a small doped region at the oxide/substrate interface
`that adjusts the flat-band voltage by varying the Qft. term in Eq. (2.3). In the
`latter approach for instance, a layer of silicon nitride (Si 3N4 ) (relati