Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`INTEL CORPORATION
`Petitioner
`
`v.
`
`PACT XPP SCHWEIZ AG
`Patent Owner
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,928,763
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`I.
`II. MANDATORY NOTICES ............................................................................. 2
`A.
`37 C.F.R. § 42.8(b)(1): Real Party-in-Interest ...................................... 2
`B.
`37 C.F.R. § 42.8(b)(2): Related Matters ............................................... 2
`C.
`37 C.F.R. § 42.8(b)(3): Counsel Information........................................ 2
`D.
`37 C.F.R. § 42.8(b)(4): Service Information ......................................... 3
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.103 ....................................... 3
`III.
`IV. CERTIFICATION OF GROUNDS FOR STANDING .................................. 3
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 3
`A.
`37 C.F.R. § 42.104(b)(1): Claims for Which IPR Is Requested ........... 3
`B.
`37 C.F.R. § 42.104(b)(2): Grounds for Challenge ................................ 3
`C.
`37 C.F.R. § 42.104(b)(3): Claim Construction ..................................... 6
`D.
`37 C.F.R. § 42.104(b)(4): How the Claims Are Unpatentable ............. 6
`E.
`37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge .................. 6
`VI. BACKGROUND OF SEMICONDUCTOR MANUFACTURING ............... 6
`A.
`Processors ............................................................................................. 7
`B.
`Interconnects for Multiprocessor Systems ............................................ 7
`VII. OVERVIEW OF THE ’763 PATENT ............................................................ 8
`A.
`The Alleged Problem in the Art ............................................................ 8
`B.
`Prosecution History ............................................................................. 10
`VIII. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 10
`IX. OVERVIEW OF THE PRIMARY PRIOR ART .......................................... 10
`A.
`Balmer ................................................................................................. 10
`B. Wilkinson ............................................................................................ 12
`C. Miyamori ............................................................................................. 13
`D. Nicol .................................................................................................... 15
`E.
`Hennessy ............................................................................................. 16
`SPECIFIC GROUNDS FOR PETITION ...................................................... 17
`
`X.
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`i
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`A. Ground I: Claims 1-3, 9-14, 16-20, 22, 24, 26, 30, 31-33, 39-
`44, 46-50, 52, 54, 56, and 60 of the ’763 patent Are Obvious In
`View Of Balmer .................................................................................. 17
`Independent Claims 1, 31 ......................................................... 17
`
`Dependent Claims 2, 32 ............................................................ 32
`
`Dependent Claims 3, 33 ............................................................ 33
`
`Dependent Claims 9, 39 ............................................................ 35
`
`Dependent Claims 10, 40 .......................................................... 36
`
`Dependent Claims 11, 41 .......................................................... 37
`
`Dependent Claims 12, 42 .......................................................... 37
`
`Dependent Claims 13, 43 .......................................................... 38
`
`Dependent Claims 14, 44 .......................................................... 38
`
` Dependent Claims 16, 46 .......................................................... 41
` Dependent Claims 17, 47 .......................................................... 43
` Dependent Claims 18, 48 .......................................................... 44
` Dependent Claims 19, 49 .......................................................... 44
` Dependent Claims 20, 50 .......................................................... 45
` Dependent Claims 22, 52 .......................................................... 47
` Dependent Claims 24, 54 .......................................................... 47
` Dependent Claims 26, 56 .......................................................... 49
` Dependent Claims 30, 60 .......................................................... 50
`Ground II: Claims 21 and 51 of the ’763 patent Are Obvious In
`View Of Balmer and Nicol .................................................................. 51
`Dependent Claims 21, 51 .......................................................... 51
`
`C. Ground III: Claims 1-3, 9-14, 16-20, 22, 24, 26, 30, 31-33, 39-
`44, 46-50, 52, 54, 56, and 60 of the ’763 patent are Obvious in
`View of Wilkinson in Combination with Hennessy ........................... 55
`Independent Claims 1, 31 ......................................................... 55
`
`Dependent Claims 2, 32 ............................................................ 71
`
`Dependent Claims 3, 33 ............................................................ 72
`
`Dependent Claims 9, 39 ............................................................ 73
`
`Dependent Claims 10, 40 .......................................................... 74
`
`
`B.
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`Dependent Claims 11, 41 .......................................................... 74
`Dependent Claims 12, 42 .......................................................... 75
`Dependent Claims 13, 43 .......................................................... 75
`Dependent Claims 14, 44 .......................................................... 76
` Dependent Claims 16, 46 .......................................................... 76
` Dependent Claims 17, 47 .......................................................... 77
` Dependent Claims 18, 48 .......................................................... 78
` Dependent Claims 19, 49 .......................................................... 78
` Dependent Claims 20, 50 .......................................................... 79
` Dependent Claims 22, 52 .......................................................... 79
` Dependent Claims 24, 54 .......................................................... 80
` Dependent Claims 26, 56 .......................................................... 81
` Dependent Claims 30, 60 .......................................................... 82
`D. Ground IV: Claims 1-3, 9-14, 16-20, 22, 24, 26, 30, 31-33, 39-
`44, 46-50, 52, 54, 56, and 60 of the ’763 patent are Obvious in
`View of Wilkinson in Combination with Hennessy and
`Miyamori ............................................................................................. 83
`Independent Claims 1, 31 ......................................................... 83
`
`Dependent Claims 10-14, 40-44 ............................................... 91
`
`Dependent Claims 2-3, 9, 16-20, 22, 24, 26, 30, 32-33,
`
`39, 46-50, 52, 54, 56, 60 ........................................................... 91
` Motivation to Combine Wilkinson and Hennessy with
`Miyamori ................................................................................... 91
`Ground V: Claims 21 and 51 of the ’763 patent are Obvious in
`View of Wilkinson in Combination with Hennessy, Miyamori,
`and Nicol ............................................................................................. 92
`Dependent Claims 21, 51 .......................................................... 92
`
`XI. CONCLUSION .............................................................................................. 96
`CERTIFICATE OF COMPLIANCE ....................................................................... 97
`
`
`
`E.
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`In re Dance,
`160 F.3d at 1343 ................................................................................................. 91
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ............................................................................ 6
`Statutes
`35 U.S.C. § 102 ...................................................................................................... 3, 4
`35 U.S.C. § 103 ...................................................................................................... 4, 5
`Rules
`37 C.F.R. § 1.68 ......................................................................................................... 6
`37 C.F.R. § 42.8(b) ................................................................................................ 2, 3
`37 C.F.R. § 42.10(b) .................................................................................................. 3
`37 C.F.R. § 42.15(a)(1) .............................................................................................. 3
`37 C.F.R. § 42.103 ..................................................................................................... 3
`37 C.F.R. § 42.104 ................................................................................................. 3, 6
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`PETITIONER’S EXHIBIT LIST1
`
`Exhibit
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`Description
`Declaration of Dr. Pinaki Mazumder (“Ex. 1001”)
`Curriculum Vitae of Dr. Pinaki Mazumder
`U.S. Patent No. 7,928,763 (the “’763 patent”)
`File History of U.S. Patent No. 7,928,763 (the “’763 File History”)
`United States Patent No. 5,197,140 (“Balmer”)
`Reserved
`U.S. Patent No. 5,761,523 (“Wilkinson”)
`United States Patent No. 6,141,762 (“Nicol”)
`Miyamori, Takashi and Olukotum, Kunle., A Quantitative Analysis
`of Reconfigurable Coprocessors for Multimedia Applications,
`IEEE Symposium on FPGAs for Custom Computing Machines
`(Pub. April 17, 1998) ("Miyamori") (Ex. 1009)
`Declaration of Gerard P. Grenier in Support of Public Availability
`of A Quantitative Analysis of Reconfigurable Coprocessors for
`Multimedia Application (Miyamori)
`Joint Claim Construction Chart filed by the parties January 31,
`2020
`John L. Hennessy & David A. Patterson, Computer Organization
`and Design: The Hardware/Software Interface (2d. ed. 1998)
`Declaration of Rachel J. Watters in Support of Public Availability
`of Computer Organization and Design: the Hardware/Software
`Interface (2d ed. 1998)
`
`
`
`
`
`
`
`1 Unless otherwise specified, citations are to the original page, column, and line
`
`numbers in exhibits. Brackets ([]) are used to refer to the sequential page numbers
`
`added to exhibits pursuant to 37 C.F.R. § 42.63(d)(2)(i).
`
`v
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`Intel Corporation (“Intel” or “Petitioner”) requests inter partes review (“IPR”)
`
`of claims 1-3, 9-14, 16-22, 24, 26, 30, 31-33, 39-44, 46-52, 54, 56, 60 (“the
`
`Challenged Claims”) of U.S. Patent No. 7,928,763 (the “’763 patent”) (Ex. 1003).
`
`I.
`
`INTRODUCTION
`The ’763 patent is directed to “reconfigurable data processing architectures”
`
`for “cell element field[s].” Ex. 1003, 1:23-25. According to the patent,
`
`reconfigurable architectures have “considerable advantages in comparison with
`
`traditional processor architectures” because the former can better-process “a large
`
`proportion of parallel and/or vectorial data processing steps.” Id. at 1:61-64. But
`
`reconfigurable processors are “not as great when . . . data processing steps that are
`
`traditionally best capable on sequencer structures are to be executed.” Id. at 1:64-
`
`2:9. The claimed invention of the ’763 patent purportedly seeks to resolve these
`
`issues by importing well-known concepts from CPUs into reconfigurable
`
`processors. Id. at 3:24-26; 10:63-65. Specifically, the ’763 patent uses “[f]unction
`
`cell-memory cell combinations” to execute “sequential program parts.” Id. at
`
`Abstract, 3:52-67. But as will be explained herein, the use of function cell-memory
`
`cell combinations was well-known in the prior art, including in the context of
`
`reconfigurable architectures. This Petition thus demonstrates that IPR should be
`
`instituted, and the challenged claims are unpatentable.
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`1
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`II. MANDATORY NOTICES
`37 C.F.R. § 42.8(b)(1): Real Party-in-Interest
`A.
`Intel is the real party-in-interest for Petitioner.
`
`37 C.F.R. § 42.8(b)(2): Related Matters
`B.
`PACT XPP Schweiz AG (“PACT”) has asserted the ’763 patent in PACT XPP
`
`Schweiz AG v. Intel Corp., Case No. 1:19-cv-1006-UNA (D. Del.). This case may
`
`affect, or be affected by, decisions in these proceedings.
`
`C.
`
`37 C.F.R. § 42.8(b)(3): Counsel Information
`Lead Counsel
`Backup Counsel
`Kevin Bendix
`Robert A. Appleby, P.C.
`Reg. No. 67,164
`Reg. No. 40,897
`kevin.bendix@kirkland.com
`robert.appleby@kirkland.com
`Postal and Hand-Delivery Address:
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`KIRKLAND & ELLIS LLP
`333 South Hope Street
`601 Lexington Avenue
`Los Angeles, CA 90071
`New York, New York 10022
`Telephone: (213) 680-8400
`Telephone: (212) 446-4800
`Facsimile: (213) 680-8500
`Facsimile: (212) 446-4900
`
`Gregory S. Arovas, P.C.
`Reg. No. 38,818
`greg.arovas@kirkland.com
`Postal and Hand-Delivery Address:
`KIRKLAND & ELLIS LLP
`601 Lexington Avenue
`New York, New York 10022
`Telephone: (212) 446-4800
`Facsimile: (212) 446-4900
`
`
`
`2
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`37 C.F.R. § 42.8(b)(4): Service Information
`D.
`Intel concurrently submits a Power of Attorney, 37 C.F.R. § 42.10(b), and
`
`consents to electronic service directed to Intel_PACT_IPR@kirkland.com.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.103
`
`The undersigned authorizes the Office to charge fees set forth in 37 C.F.R. §
`
`42.15(a)(1) for this Petition to Deposit Account No. 506092. The undersigned
`
`further authorizes payment for any additional fees that may be due in connection
`
`with this Petition to be charged to this deposit account.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`Intel certifies pursuant to 37 C.F.R. § 42.104(a) that the ’763 patent is
`
`available for IPR and that Intel is not barred or estopped from requesting IPR
`
`challenging the claims on grounds identified herein.
`
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`37 C.F.R. § 42.104(b)(1): Claims for Which IPR Is Requested
`A.
`Intel challenges claims 1-3, 9-14, 16-22, 24, 26, 30, 31-33, 39-44, 46-52, 54,
`
`56, and 60 of the ’763 patent.
`
`37 C.F.R. § 42.104(b)(2): Grounds for Challenge
`B.
`The claims are challenged based on the following references:
`
`1. United States Patent No. 5,197,140 (“Balmer”) (Ex. 1005); filed November
`
`17, 1989; issued March 23, 1993, prior art under §§ 102(a), (b), and (e).
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`2. U.S. Patent No. 5,761,523 (“Wilkinson”) (Ex. 1007); filed June 7, 1995;
`
`issued June 2, 1998, prior art under §§ 102(a), (b), (e).
`
`3. U.S. Patent No. 6,141,762 (“Nicol”) (Ex. 1008); filed August 3, 1998; issued
`
`October 31, 2000. Nicol is prior art under 35 U.S.C. §§ 102(a), (b), and (e).
`
`4. T. Miyamori, A Quantitative Analysis of Reconfigurable Coprocessors for
`
`Multimedia Applications (“Miyamori”) (Ex. 1009); published in Proceedings,
`
`IEEE Symposium on FPGAs for Custom Computing Machines, date of
`
`conference April 17, 1998. Miyamori is prior art under §§ 102(a) and (b).
`
`5.
`
`John L. Hennessy & David A. Patterson, Computer Organization and Design:
`
`The Hardware/Software Interface (2d. ed. 1998) (“Hennessy”) (Ex. 1012);
`
`published in 1998, prior art under §§ 102(a), (b).
`
`None of these references were before the Patent Office during prosecution of
`
`the ’763 patent.
`
`Petitioner requests IPR on the following grounds:
`
`Ground
`
`Claims
`
`Proposed Statutory Rejection
`
`1
`
`2
`
`Obviousness under § 103 in view of Balmer
`
`1-3, 9-14,
`16-20, 22,
`24, 26, 30-
`33, 39-44,
`46-50, 52,
`54, 56, and
`60
`21 and 51 Obviousness under § 103 in view of Balmer in
`combination with Nicol
`
`4
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`Obvious under § 103 in view of Wilkinson in
`combination with Hennessy
`
`1-3, 9-14,
`16-20, 22,
`24, 26, 30-
`33, 39-44,
`46-50, 52,
`54, 56, and
`60
`1-3, 9-14,
`16-20, 22,
`24, 26, 30-
`33, 39-44,
`46-50, 52,
`54, 56, and
`60
`21 and 51 Obvious under § 103 in view of Wilkinson in
`combination with Hennessy, Miyamori, and Nicol
`
`Obvious under § 103 in view of Wilkinson in
`combination with Hennessy and Miyamori
`
`3
`
`4
`
`5
`
` G
`
` rounds 1-5 are not redundant. Grounds 1-5 present substantially different
`
`discussions on how the Challenged Claims are unpatentable. For instance, while all
`
`disclose invalidating function cell-memory cells pairs, each provides for a
`
`substantially different overall processor architecture. Ground 1 relies on Balmer as
`
`the primary reference for interconnecting multiple processors and memory utilizing
`
`crossbar technology for the programmable interconnect, including dedicated paths
`
`for certain memories and a transfer processor to communicate with external memory.
`
`Ground 3 relies on Wilkinson as the primary reference for interconnecting multiple
`
`processor-memory elements in a parallel processor array with a ring interconnect.
`
`Ground 4 combines the processor-memory element arrays of Wilkinson with the
`
`reconfigurable architecture bus interconnect logic of Miyamori. Grounds 2 and 5
`
`add to Grounds 1, 3 and 4 the concept of frequency control as disclosed in Nicol.
`
`5
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
`
`37 C.F.R. § 42.104(b)(3): Claim Construction
`C.
`Terms in an IPR should be construed in accordance with the principles set
`
`forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). 37 C.F.R.
`
`§ 42.104(b)(3). The parties dispute a number of claim terms in the co-pending
`
`district court case, as set forth in Ex. 1011.
`
`The Board does not need to resolve these issues, though, because as explained
`
`in Section XI, the Challenged Claims are obvious based on Grounds 1-5 regardless
`
`of which construction the Board adopts.
`
`37 C.F.R. § 42.104(b)(4): How the Claims Are Unpatentable
`D.
`A detailed explanation of how the Challenged Claims are unpatentable is
`
`provided in Section XI.
`
`37 C.F.R. § 42.104(b)(5): Evidence Supporting Challenge
`E.
`A list of exhibits is provided at the end of this Petition. The relevance of this
`
`evidence and the specific portions supporting the challenge are provided in Section
`
`IX. Intel submits a declaration of Dr. Pinaki Mazumder (“Mazumder Decl.”) (Ex.
`
`1001) and a copy of Dr. Mazumder’s Curriculum Vitae (Ex. 1002) in support of this
`
`Petition under 37 C.F.R. § 1.68.
`
`VI. BACKGROUND OF SEMICONDUCTOR MANUFACTURING
`The ’763 patent broadly relates to reconfigurable data processing architectures
`
`for data processing “cell element fields.” Reconfigurable processing cell
`
`architectures can be configured and optimized to execute particular instructions
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`repeatedly, but they are often less capable than traditional processors because they
`
`cannot handle as a broad set of instructions. A brief overview of such reconfigurable
`
`multiprocessor systems follows.
`
`Processors
`A.
`A general-purpose processor retrieves an instruction stored in a memory and
`
`decodes the instruction to perform logical and arithmetic operations on data, also
`
`fetched from the memory. Ex. 1001 ¶46-48. This is generally accomplished by an
`
`arithmetic logic unit (“ALU”). Ex. 1001 ¶46. As an example, a “32-bit architecture”
`
`will receive a sequence of 32-bit instructions, and an instruction set architecture
`
`could require that the first 8 bits define an instruction, and the remaining bits
`
`correspond to data to be manipulated, an address where data can be stored, or other
`
`information. Ex. 1001 ¶46-48. Processors use a significant number of caches,
`
`registers, and other memory components to temporarily store data that is being
`
`processed. Ex. 1001 ¶46-48.
`
`Interconnects for Multiprocessor Systems
`B.
`Early multiprocessor systems could use a number of different architectures as
`
`identified, in part, by their interconnect configurations. Engineers have long-since
`
`used reconfigurable architectures that enable a multiprocessor system to change the
`
`general interconnect structure among the various components. Ex. 1001 ¶49-67.
`
`Whereas non-reconfigurable bus systems are generally static and route data along
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`the
`
`interconnection network until
`
`it arrives at
`
`the specified destination,
`
`reconfigurable systems—including the crossbar interconnect—will instead create a
`
`physical path between a source and destination using switches. Ex. 1001 ¶49-67.
`
`Engineers have developed reconfigurable interconnect buses that are “dynamically”
`
`reconfigurable at runtime, which means the system can reconfigure portions or the
`
`entirety of the interconnect structure while the device is still in operation.
`
`VII. OVERVIEW OF THE ’763 PATENT
`The ’763 patent issued from U.S. App. No. 12/836,364 (the “’364
`
`application”), filed July 14, 2010, claiming priority to a foreign application filed on
`
`September 6, 2002. Ex. 1003, Cover. For purposes of this Petition only, Petitioner
`
`does not contest that the ’763 patent is entitled to the September 6, 2002 priority
`
`date.
`
`A. The Alleged Problem in the Art
`The ’763 patent states that the “present invention” relates to “reconfigurable
`
`data processing architectures” for “cell element field[s].” Ex. 1003, 1:23-25.
`
`According to the patent, reconfigurable architectures have “considerable advantages
`
`in comparison with traditional processor architectures” because the former can
`
`better-process “a large proportion of parallel . . . data processing steps.” Id. at 1:61-
`
`64. But reconfigurable processors “are not as great” at executing “sequential
`
`program parts” that are more similar to those found in a traditional processor. Id. at
`
`8
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`1:64-2:9, 3:52-67. The ’763 patent explains that these program parts (e.g.,
`
`Huffmann coding within MPEG4 coding) are difficult to parallelize, and require
`
`sequential execution. Id. at 3:58-67.
`
`The claimed invention of the ’763 patent purportedly seeks to resolve this
`
`issue by using “[f]unction cell-memory cell combinations” to execute “sequential
`
`program parts.” Id. at Abstract, 3:52-67. This arrangement allows memory to
`
`function as a cache and the function cell to load “commands that are to be executed
`
`by the ALU.” Id. at 11:1-2, 2:31-36. The processing units within the processor can
`
`then be adapted to perform sequential (red) along with parallel (green) data
`
`processing as shown in the ’763 patent Figure 6(a).
`
`Id. at Fig. 6(a).
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`Prosecution History
`B.
`The examiner issued a Notice of Allowance on November 12, 2010 without a
`
`substantive office action. Id. at 421-27. The ’763 patent issued on April 19, 2011.
`
`Ex. 1003, Cover.
`
`VIII. LEVEL OF ORDINARY SKILL IN THE ART
`A POSITA at the time of the alleged invention would have had at least a M.S.
`
`degree in electrical engineering or computer engineering (or equivalent experience),
`
`and at least three years of experience with processor design and memory
`
`architecture. Ex. 1001 ¶73-74.
`
`IX. OVERVIEW OF THE PRIMARY PRIOR ART
`The claimed multi-processor system―having data processing cells (each
`
`adopted for sequentially executing at least one of algebraic logic functions) and
`
`memory cells―was known in the art long before the priority date of the ’763 patent.
`
`Indeed, Balmer, Wilkinson, Nicol, and Miyamori disclose this cell-pair structure and
`
`similar bus interconnect structures, and thus these references render the Challenged
`
`Claims obvious.
`
`A. Balmer
`Balmer describes a multiprocessor system with parallel processors (PPs) all
`
`having communication links to several memories, which can be reconfigured, within
`
`a single chip. Ex. 1005, Abstract. As shown below, the system allows multiple
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`memories (purple) to be accessed concurrently by parallel processors (blue) using a
`
`crossbar switch (yellow). Id.
`
`
`
`Ex. 1005, Figure 4. 2
`
`Balmer teaches that its crossbar switch is “reconfigured to allow access” to
`
`the correct processors and/or memory. Ex. 1005, 6:25-28. “[T]he crossbar switch
`
`can serve to, on a cycle by cycle basis if necessary, interconnect various processors
`
`together to work from a single instruction for a period of time or to work
`
`independently[.]” Ex. 1005, 9:11-20. As Balmer explains, this ability to reconfigure
`
`its
`
`interconnects within a single cycle—i.e., dynamically/programmably
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`interconnecting at runtime—“allows for complete flexibility of processor and
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`memory operation as well as optimal use of data transfer resources.” Id. at 9:20-27.
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`B. Wilkinson
`Wilkinson discloses a configurable parallel array processor with “[e]ight
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`processors on a single chip [that each] have their own associated processing element,
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`significant memory, and I/O[.]” Ex. 1007, Abstract. Wilkinson uses “processor
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`memory elements” or “PMEs” that have the “capability of fetching and executing
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`stored instructions from their own main store in MIMD operation or to fetch and
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`execute commands via the [an] interface in SIMD mode.” Id. Figure 13 shows the
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`logical arrangement of a cluster of PMEs, replicated below:
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`Ex. 1007, Figure 13 (processors in blue, bus interconnect in yellow, and memories
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`in purple). Each PME includes “four programmable bi-directional I/O ports” such
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`that “programmable routing on the chip generally causes links to be established
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`between the PMEs[.]” Id. at 14:23-33, 23:40-56. “[S]ystem paths are
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`programmatically configurable, allowing high bandwidth links on a target network,
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`and allowing dynamic partition of off chip like PME-to-PME links to provide more
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`bandwidth on specific paths as meets the needs of a particular application.” Id. at
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`39:18-34. Thus, “the system can have a diversity of interconnection topologies, with
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`routing performed dynamically and programmatically.” Id. at 46:52-63.
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`C. Miyamori
`Miyamori describes the use of reconfigurable coprocessors in multimedia
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`applications, including a reconfigurable multimedia array coprocessor (REMARC).
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`Ex. 1009, 1. Miyamori teaches that the REMARC system “achieves speedups of a
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`factor of 7.3 for DES encryption and 2.3 for MPEG-2 decoding.” Id. The
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`REMARC coprocessor bus provides for data transmission on horizontal (Figure 3,
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`yellow) and vertical busses and additionally data flow between adjacent processors
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`(Figure 4, yellow). Id.
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`Id. at Fig. 3.
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`Id. at Fig. 4.
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`D. Nicol
`Nicol discloses a multiprocessor system that dynamically controls the supply
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`voltage and clock frequency of each of the processors to minimize overall power
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`consumption. Ex. 1009, Abstract.
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`Figure 4
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`Each processing element (“PE”) has an individual supply voltage (orange), allowing
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`the clock frequency of each PE to be dynamically adjusted. Ex. 1009, 5:66–6:3;
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`Figure 4. Nicol explains that this allows PEs with higher loads to have higher clock
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`frequencies and corresponding supply voltages than PEs with lower processing
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`loads. Id., 5:60–63.
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`E. Hennessy
`Hennessy is a textbook titled Computer Organization and Design, published
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`in 1998. Among the many topics that it covers are processor architecture and bus
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`systems that interconnect processors with other processors, memory, and I/O. The
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`contents of Hennessy reflect the knowledge that a POSITA would have had before
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`the priority date of the ’763 patent.
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`Petition for Inter Partes Review of U.S. Patent No. 7,928,763
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`X.
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`SPECIFIC GROUNDS FOR PETITION
`The sections below demonstrate in detail how the prior art renders obvious
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`the Challenged Claims. Secondary considerations do not support a finding of
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`nonobviousness. Ex. 1001 at ¶226. Should PACT submit alleged evidence relating
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`to secondary considerations, Intel respectfully requests the right to respond.
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`In view of the substantial overlap in claims, often including verbatim the same
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`limitations, Petitioner addresses analogous claims together in each of the grounds
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`below.
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`A. Ground I: Claims 1-3, 9-14, 16-20, 22, 24, 26, 30, 31-33, 39-44, 46-
`50, 52, 54, 56, and 60 of the ’763 patent Are Obvious In View Of
`Balmer
`Independent Claims 1, 31
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` A multi-processor chip, comprising:
`Petitioner does not believe that this preamble is limiting, but to the extent
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`Patent Owner argues otherwise, Balmer discloses “[a] multiprocessor system”
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`whereby “[t]he processor is structured with several individual processors all having
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`communication links to several memories.” Ex. 1005, Abstract. Balmer’s invention
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`is “contained on a single silicon chip.” Id. Balmer thus discloses the claimed
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`“multi-processor chip.” Ex. 1001 ¶89.
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` a plurality of data processing cells, each adapted for
`sequentially executing at least one of algebraic and
`logic functions and having:
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`Balmer discloses “[a] multiprocessor system” whereby “[t]he processor is
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`structured with several individual processors all having communication links to
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`several memories.” Ex. 1005, Abstract. The individual processors correspond to
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`the claimed “plurality of data processing cells.” Ex. 1001 ¶90. This arrangement
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`can be seen in Balmer’s Figure 1, where each of the individual parallel processors—
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`labeled “PP”—is highlighted blue:
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`Ex. 1005, Fig. 1. Each parallel processor executes algebraic and logic functions.
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`Ex. 1005, 8:34-36 (“[I]mplementation of algorithms with the same data flow
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`although using unique arithmetic or logical functions.”).
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`Balmer’s Parallel Processors are though “reconfigurable SIMD/MIMD”
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`processors. Ex. 1005, 8:49. When operating in MIMD mode, the PPs sequentially
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`execute algebraic and logic functions. Ex. 1005, 8:34-36 (“MIMD would include
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`the implementation of algorithms with the same data flow although using unique
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`arithmetic or logical functions.”), 35:56-60 (“[T]he PPs can be configured to execute
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`from…independent instruction streams (Multiple Instruction Multiple Data (MIMD)
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`mode); Ex. 1001 ¶91. Specifically, Balmer’s processors in MIMD mode
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`sequentially “execut[e] their own instruction streams” on data. Ex. 1005, 26:11-41,
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`see Section IX.A.
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`at least one arithmetic logic unit;
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`Each of Balmer’s parallel processors includes at least an arithmetic logic unit
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`(ALU) within its “data unit,” as illustrated in Figure 33 below.
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`More specifically, each parallel processor includes “three main units”: “the program
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`flow control unit 3002, the address unit 3001 and the data unit 3000.” Ex. 1005,
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`37