United States Patent c19J
`Balmer
`
`I IIIII IIIIIIII Ill lllll lllll lllll lllll lllll lllll lllll lllll 111111111111111111
`US005197140A
`5,197,140
`[11] Patent Number:
`[45] Date of Patent: Mar. 23, 1993
`
`[54] SLICED ADDRESSING MULTI-PROCESSOR
`AND METHOD OF OPERATION
`Inventor: Keith Balmer, Bedford, England
`[75]
`[73] Assignee: Texas Instruments Incorporated,
`Dallas, Tex.
`[21] Appl. No.: 437,946
`Nov. 17, 1989
`[22] Filed:
`[51] Int. Cl.5 ...................... G06F 12/00; G06F 15/00;
`G06F 7 /33; G06F 7 /50
`[52] U.S. Cl . .................................... 395/400; 395/300;
`364/749; 364/786; 364/787
`[58] Field of Search ............... 395/400, 800, 163, 166;
`364/749, 786, 787
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,260,840 7/1966 King .................................... 364/787
`3,683,163 8/1972 Hanslip ............................... 364/749
`3,728,532 4/1973 Pryor .................................. 364/787
`4,562,535 12/1985 Vincent et al ...................... 395/325
`4,644,496 2/1987 Andrews ............................. 395/800
`4,747,043 5/1988 Rodman .............................. 395/425
`4,860,248 8/1989 Lumelsky ............................ 395/163
`4,888,679 12/1989 Fossum et al ................... : ... 395/800
`4,953,101 8/1980 Kelleher et al. .................... 395/166
`5,101,338 3/1992 Fujiwara et al .................... 395/400
`OTHER PUBLICATIONS
`"The Connection Machine", W. D. Hillis, published in
`The MIT Press (1985).
`"Handling Real Time Images Comes Naturally to Sys(cid:173)
`tolic Array Chip", by Hannaway, Shea, Bishop in Elec(cid:173)
`tronic Design, pp. 289-300, Nov. 1984.
`"Systolic Array Chip Recognizes Visual Patterns
`Quicker Than a Wink", by W.W. Smith, P. Sullivan, in
`Electronic Design, pp. 257-266, No. 29, 1984.
`"Real Time 3D Object Tracking in a Rapid Prototyping
`Environment", Robert J. Gove, Electronic Imaging
`'88, Oct. 4, 1989, pp. 54-59.
`"Integration of Symbolic and Multiple Digital Signal
`Processors with the Explorer/Odyssey for Image Pro(cid:173)
`cessing and Understanding-Applications", Robert J.
`Gove, Proceedings to the IEEE International Sympo(cid:173)
`sium of Circuits and Systems, pp. 968-971 (May, 1987).
`"The Use of Parallel-Processing Computers in Digital
`
`Image Processing", Lew Brown, Electronic Imaging
`'87, International Electronic Imaging Exposition and
`Conference, Nov. 2, 1987, pp. 1057-1060.
`"VITec Parallel C Compiler", by Butler, Electronic
`Imaging '89, International Electronic Imaging Exposi(cid:173)
`tion and Conference, Nov. 1989, pp. 741-747.
`"A Single Board Image Computer with 64 Parallel
`Processors" by Stephen Wilson, Electronic Imaging
`'87, International Electronic Imaging Exposition &
`Conference, Nov. 2, 1987, pp. 470-475.
`"The Androx Parallel Image Array Processor", Wayne
`Threatt, Electronic Imaging '87, International Elec(cid:173)
`tronic Imaging Exposition & Conference, Nov. 2, 1987,
`pp. 1061-1064.
`"Design of a Massively Parallel Processor", Kenneth
`Batcher, IEEE Transactions on Computers, v. C-29,
`No. 9, Sep. 1980, pp. 836-840.
`"High Resolution Frame Grabbing and Processing
`Through Parallel Architecture", Daniel Crevier, Elec(cid:173)
`tronic Imaging '87, International Electronic Imaging
`Exposition & Conference, Nov. 2, 1987, pp. 681-682.
`(List continued on next page.)
`
`Primary Examiner-Joseph L. Dixon
`Assistant Examiner-Michael A. Whitfield
`Attorney, Agent, or Firm-Robert D. Marshall, Jr.;
`James C. Kesterson; Richard L. Donaldson
`[57]
`ABSTRACT
`A multi-processor system arranged, in one embodiment,
`as an image and graphics processor. The processor is
`structured with several individual processors all having
`communication links to several memories. An address(cid:173)
`ing scheme, called sliced addressing, is used to spread
`contiguous related data over several memories so that
`the data can be concurrently accessed by several pro(cid:173)
`cessors. A crossbar switch serves to establish the pro(cid:173)
`cessor memory links. The entire image processor, in(cid:173)
`cluding the individual processors, the crossbar switch
`and the memories, is contained on a single silicon chip.
`
`13 Claims, 35 Drawing Sheets
`
`ORIGINAL
`ADDRESS
`
`A
`
`2505
`2507
`
`2504
`
`LOGIC'>.L
`---i--i----- ZERO
`
`A
`
`B
`
`2506
`2508
`
`ADDER WITH 2509
`SLICE
`C'>PABIUlY
`
`A
`
`B
`
`FA
`CoADD Ci
`
`SLICE MASK BUS FROM PROCESSOR REGISTER
`
`INTEL - 1005
`
`

`

`5,197,140
`Page 2
`
`OTHER PUBLICATIONS
`"Multiple Digital Signal Processor Environment for
`Intelligent Signal Processors by Gass et al.", Proceed(cid:173)
`ings of the IEEE, v. 75, No. 9 (Sep. 1987) pp.
`1246-1259.
`"Architecture and Design of the Mars Hardware Ac(cid:173)
`celerator", AGRA Wall, in 24th ACM/IEEE Design
`.
`Automation Conference (1987), pp. 101-107.
`. "A 200 MIPS Single-Chip IKFFY Processor", by O'-.
`1 Brien, Mather & Holland, IEEE International Solid-S(cid:173)
`; tate Circuits Conference, Feb. 16, 1989, pp. 166-167.
`
`"An Architectural Study, Design and Implementation
`of Digital Image Acquisition Processing and Display
`Systems with Micro-Processor-Based Personal Com(cid:173)
`puters and Charge-Coupled Device Imaging Technol(cid:173)
`ogy", a Dissertation by Robert J. Gove, SMU, May 17,
`1986.
`
`"A Medium Grained Parallel Computer for Image Pro(cid:173)
`I cessing" by R. S. Cok, published by Digital Technology
`Center, Eastman Kodak Co., Rochester, N.Y., pp.
`927-936.
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 1 of 35
`
`5,197,140
`
`100
`CYCLE-RATE LOCAL CONNECTION NETWORK (CROSSBARS)
`
`r--------------------------,
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`171 172
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 2 of 35
`
`5,197,140
`
`BUS
`
`34
`35
`
`FIG. 3
`
`8
`
`FIG. 6
`(PRIOR ART)
`
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`
`INTEL - 1005
`
`

`

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`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 4 of 35
`
`5,197,140
`
`FIG. 11
`
`1114
`GEOMETRIC MODEL
`
`2D
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`QUERY
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`CYCLE
`P-i
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 5 of 35
`
`5,197,140
`
`FIG. 13
`MEMORY
`(REGION 1)
`(REGION 3)
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`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 6 of 35
`
`5,197,140
`
`FIG. 16
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`

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`I
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`I
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`I
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`
`PP2
`MAIN
`BUS
`
`PP2's GRANT-
`
`PP2's GRANTED-
`
`PP2's CONNECT
`
`PP3's 5 MS ADDR
`PP3's 11 LS AOOR
`PPJ
`: : AND CTRL SIGNALS
`{
`PP3's 32 DATA
`
`PP3's GRANT-
`
`PP3's GRANTED-
`
`PP3's CONNECT
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 10 of 35
`
`5,197,140
`
`2103
`
`103 2102
`
`>0000 >0800 >1000 >1800 >2000 >2800 >3000
`
`>3800
`
`64
`64
`>1900 >2100
`64
`64
`64
`PIXELS PIXELS PIXELS >193F >213F PIXELS PIXELS
`
`64
`PIXELS
`
`>1940
`
`>07FF
`
`>OFFF >17FF
`
`>1FFF >27FF
`
`0
`
`2
`
`3
`
`4
`
`>2FFF >37FF
`6
`
`5
`
`>3FFF
`7
`
`NORMAL ARITHMETIC
`
`{
`
`>193F
`>~1
`>1940
`
`-
`-
`-
`
`0 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1
`0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
`0 0 0 1 100 1010000 0 0
`
`I
`
`\
`
`SLICED ARITHMETIC
`
`SLICE NUMBER
`...
`0 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1
`-
`> 193F
`(SLICE MASK) 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0
`I
`I
`4
`CARRY
`0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
`0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
`FIG. 27
`
`+
`>0001
`-
`>2100
`
`-
`-
`
`INTEL - 1005
`
`

`

`)90 I
`101
`103
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`
`102
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`
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`EXECUTE
`LCK _. SETS 'S'
`A
`B
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`
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`B
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`A
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`
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`
`LCK
`A
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`
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`- - - - - - - SYNCHRONIZED------
`
`FIG. 22
`
`•
`
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`
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`0
`
`INTEL - 1005
`
`

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`m
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`0
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`1
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`CACHE-MISS
`
`FIG. 23
`
`m - MASTER CLOCK
`s - SLAVE CLOCK
`
`s: m s: m
`LD-E2
`ST-E1
`tu
`A2
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`4
`3
`
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`tr> = ~
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`~ w
`
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`A1
`F2
`2
`
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`E
`A
`LCK-FO
`0
`
`(3210)
`SYNC BITS = 0110
`IN BOTH PP2 AND PP1
`
`:m
`
`PP2's PIPELINE
`INSTR f FETCH_.
`PP2's SYNC LINE
`s-..
`
`PP1's PIPELINE
`INSTR f FETCH_,.
`PP1's SYNC LINE
`s-.
`
`INSTRUCTION # _,.
`AND OF SYNCS
`
`EO
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`
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`
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`0
`
`INTEL - 1005
`
`

`

`FIG. 24
`
`127
`0
`a l™ENf PIXELS! <;
`b ~-------------1
`C L __________ _J
`
`15
`EXTERNAL -
`• tMAGE MEMORY'
`BUFFER
`
`SLICED
`
`AD~RESSING >a
`2401
`
`I
`b
`C
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`F
`
`-1
`
`1Q
`A ·suer
`
`o I 1 I 2 I J I 4 I 5 I 6 I 7
`
`RAMS ADDRESSABLE BY CROSSBAR
`
`FIG. 25
`(PRIOR ART)
`
`NORMAL
`ADDER
`
`A
`
`Co
`
`B .1-J2503
`
`FA I
`
`Ci1------1Co
`
`I FA
`
`2501
`
`·I
`LOGICAL
`c,._ _ _ ZERO
`
`A
`
`8 J.-,2502
`
`I FA I
`
`Ci1--------1Co
`
`ADDER WITH 2509
`SLICE
`r.APABIUlY
`FIG. 26
`
`ADDRESS TO MEMORY
`
`ORIGINAL
`ADDRESS
`
`2506
`2508
`
`A B
`FA
`Co ADD Ci
`
`A B
`FA
`Co ADI) Ci
`
`2505
`25.07
`
`A
`
`8
`
`FA
`Co ADD Ci
`
`2504
`
`SLICE MASK BUS FROM PROCESSOR REGISTER
`
`T~MR~~r
`
`LOGICAL
`- - - - - - - - ZERO
`
`~ •
`00
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`
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`
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`
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`w
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`
`(II
`
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`.....:a
`
`0
`
`INTEL - 1005
`
`

`

`PP3
`
`.1QJ
`
`PC
`
`2812
`
`2802
`
`2813
`
`2803
`
`PP2
`
`102
`
`PC
`
`2811
`
`2801
`
`PP1
`
`101
`
`PC
`
`PP0
`
`100
`
`PC
`
`2810
`
`2800
`
`4-6
`
`X 9 I SIMD
`
`MIMD
`
`MIMD
`
`9-6
`
`X 9 I SIMD
`
`9-1
`
`I FIG. 28
`
`MIMD
`
`ADDRESS TO
`INSTRUCTION RAM
`
`401
`
`MIMD
`
`MIMD
`
`402
`
`MIMD
`
`403
`MIMD SIMD
`
`TP
`ONTROL
`
`INSTRUCTIONS/
`DATA
`
`INSTRUCTIONS/
`DATA
`
`INSTRUCTIONS/ I I REGISTER I I INSTRUCTION
`104
`2820
`
`DATA
`
`I
`
`10-13
`
`10-9
`
`10-5
`
`10-1
`
`0 •
`r.11
`•
`
`'"'C a t'I) = """"
`
`a:
`~
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`
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`~
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`
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`tn
`
`UI
`
`.....:a
`
`... ... \0
`... ... ~
`
`0
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 15 of 35
`
`5,197,140
`
`32 BIT INSTRUCTIONS
`
`FIG. 29
`
`172
`
`EQCMP .2fil.2
`PC .29.QJ------
`
`CONTROL
`
`12
`
`SHIFT(cid:173)
`NORM
`
`2910
`
`-----MULTIPLIER
`2905
`
`NORMAUZ
`ml§
`
`REGISTER FILE
`.299.1 1 - - - - - - - -+ - - - - -1
`
`2907
`
`L -- ----------------------~
`
`171
`32 BIT
`ADDRESS
`
`DATA
`
`IN/OUT
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 16 of 35
`
`5,197,140
`
`PARALLEL
`PROCESSOR r--------------------, 3100
`V
`.
`I
`.--------1...
`3000
`
`DATA UNIT
`{FIG. 33)
`
`301
`
`3015
`
`3017
`
`ADDRESS UNIT
`(FIG. 32)
`
`•
`
`IMMEDIATE I
`
`40
`
`3020-.+---+--+---+-+---"3--.2i..;..1-+---
`I .... ---,------.---i--...-
`1
`L-
`3019
`
`3011
`
`3012 3013
`
`...... ....,.......,....,...,........,,1
`----- 3003
`3oos-'1 3oos-'1
`LOCAL
`GLOBAL
`M>DR/DATA ADDR/DATA
`
`PACKET
`REQUEST
`RUPTS
`
`R KET
`ACKNOWLEDGEMENT
`
`INSTRUCTION
`PORT
`3004
`
`FIG. 30
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 17 of 35
`
`5,197,140
`
`PROGRAM FLOW CONTROL UNIT
`r-----------------------------------------,
`~[1
`Ji!
`i
`
`f
`'
`'
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`.JJM
`
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`
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`,, r-{---,----{---,----{---;-7
`~----1 L£3-
`I
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`3118
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`LE2 _
`...__....;;;;;;;;;;;;;;;..al
`I
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`LR2 3123 1
`1
`I .__.. _ _,. .__.. __ _,. 1--__._..._.,
`3117
`3102
`'i L£1 3116
`LR13122 :
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`______ u
`3130 . -
`GRANTED
`.
`:::- -
`CONTENTION
`LSA
`i - - - -..... 3-1-11.... ~ ~ SYNC SIGNAL ~o, ..
`~ ~ _ ~11.m 9pu.1r-u r30081
`RET
`1------3-1-03~ 8 tx ,~ SIMD PAUSE r3001i
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`:
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`SIGNALS
`I N
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`: .__..-+-------11 I
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`
`........ LS7
`2
`
`I',.
`
`..
`.., 32
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 18 of 35
`
`5,197,140
`
`3001
`T
`r-------------------------------------------,
`
`ADDRESS UNIT
`
`MUX
`
`5
`
`PRE/POST
`
`LATCH
`
`MUX
`
`5
`
`PRE/POST
`
`LATCH
`
`.J2QQ
`MUX
`GLOBAL
`11
`- - - - - - -~~-:!J~~L
`
`MUX
`
`MUX
`
`5
`
`11
`
`~
`LOCAL
`- ~~-J!!_IT...J
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`- - - - - - - -1
`I
`I
`I
`
`L - - - - - - - - - - - - ----------- -- ------ ______ J
`
`ADDRESS
`(CONTENTION)
`3210 5 MSB
`
`11 LSB
`
`GLOBAL BUS
`3005
`
`ADDRESS
`(CONTENTION)
`3211
`5 MSB
`LOCAL BUS
`3006
`
`FIG. 32
`
`11 LSB
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 19 of 35
`
`5,197,140
`
`FIG. 33
`~-----------------------------------~
`
`DATA UNIT
`
`I
`I
`I
`I
`I
`I
`
`I
`
`IMMEDIATE
`REGISTER SRC 1
`! .
`I
`GLOBAL STORE 1
`I
`I
`I
`I
`GLOBAL LOAD I
`I
`I
`I
`LOCAL STORE I
`
`DATA
`REGISTER----------.
`FILE
`
`0
`
`PRE
`
`00-D7
`
`0
`
`MUXMQ.§
`
`MUX~ MUX~
`
`LOCAL LOAD
`
`REGISTER DST
`
`ALU
`OPTIONS
`w:M~FLA~G~S~~---~ 1 's LOGIC
`
`3304
`
`1 MUX .._...,._ ____________ __.
`: ~
`~-----------------------------------~
`
`FIG. 34
`
`0
`STATUS REGISTER (SR)
`31
`INlcjvjzlilslMLDjcLDjololRlulolPlololololoJojojojolololololololol
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 20 of 35
`
`5,197,140
`
`I
`SIMD PAUSE
`
`I
`SYNC SIGNAL
`
`F
`
`A
`F
`
`Exb
`Anm
`Fem
`
`. . . . . . . .. . ..
`Etl
`Enm
`. . . ... A
`. . . . . . . . .
`. . . F
`. . . Fpc
`Fwp
`Fwa
`
`I
`
`FIG. 35
`
`E
`A
`F
`pc +1
`
`E
`A
`
`pc
`
`pc
`
`pc
`
`p C
`
`pc
`
`+1
`pc
`
`p ct1
`+1
`pc
`pc
`Fem - CACHE-MISS
`Anm - NO MASTER PHASE OF THE ADDRESS UNIT, THUS NO REGISTER MODIFY.
`LOADS
`Exb - CROSSBAR ACCESS(ES) OCCUR. STORES COMPLETE TO MEMORY.
`COMPLETE INTO TEMPORARY LATCHES, MASTER PHASE OF DATA UNIT
`OPERATIONS KILLED.
`Enm - NO MASTER PHASE OF DATA UNIT.
`Fwa - WAIT FOR CACHE-MISS ACKNOWLEDGE FROM TP.
`Fpc - TRANSFER PC AND SEGMENT NUMBER TO TP
`Fwp - WAIT FOR SUBSEGMENT PRESENT FLAG TO BECOME SET.
`EtL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESIGNATION REGISTER(S). .
`DATA UNIT PERFORMS ITS ALU/MPY OPERATIONS.
`
`FIG 36
`.
`
`\
`
`I
`
`I
`
`1P
`
`AUSE
`
`SIMD
`
`SYNC SIGNAL
`
`F
`
`A
`F
`
`E
`A
`F
`
`EgL
`Anm
`Fnm
`
`Eg
`Anm
`Fnm
`
`Etl
`A
`F
`
`E
`A
`
`E
`A
`F
`pc +1
`+1
`+1
`+1
`pc
`pc
`+1
`pc
`pc
`pc
`pc
`EgL - CONTENTION DETECTED ON BOTH GLOBAL AND LOCAL BUSES. NO MASTER
`PHA.5E IN DATA UNIT.
`Fnm - NO MASTER PHASE ON FETCH. PIPE NOT LOADEO.
`LOCAL BUS TRANSFER OCCURS.
`Eg - CONTENTION DETECTED ON GLOBAL BUS.
`STORE TO MEMORY, OR LOAD TO TEMP REGISTER. NO MASTER PHA.5E IN
`DATA UNIT.
`EtL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESTINATION REGISTER(S).
`DATA UNIT PERFORMS ITS M..U/MPY OPERATIONS.
`Anm - NO MASTER PHASE IN ADDRESS UNIT. ADDRESS REGISTER NOT MODIFIED.
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 21 of 35
`
`5,197,140
`
`F
`
`A
`F
`
`E
`A
`Fsa
`
`E
`A
`Fer
`
`E
`A
`Fsa
`
`E
`A
`Fen
`
`pc+1
`
`lc=2
`pc+1
`cld=1
`mld=1
`
`pc+1
`
`pc=eo
`lc<>1
`pc:=sa
`lc:=lc-1
`cld:=mld
`
`pc+1
`
`pc=eo
`lc=1
`pc+1
`lc:=lr
`cld:=cld-1
`
`E
`A
`
`E
`
`E
`A
`F
`
`pc+1
`
`Fsa - START ADDRESS OF LOOP. PC INCREMENTS NORMALLY.
`Fer - END ADDRESS, REPEAT LOOP.
`LOOP COUNTER NOT ONE. LOAD PC
`WllH START ADD.
`Fen - END ADDRESS, NO-REPETITION.
`INCREMENTS NORMAl.1 Y.
`
`LOOP COUNTER IS ONE. PC
`FIG. 37
`
`FIG. 38
`I
`SIMD BRANCH-TAKEN
`
`SYNC SIGNAL
`
`F
`
`A
`•Fd1
`
`\
`
`Epr
`A
`F
`
`I
`
`Epc
`A
`•Fd2
`
`Epr
`A
`Fba
`
`pc+1
`
`pc+1
`
`pc:=ba
`ret:= c+1
`p
`
`pc+1
`
`pc+1
`
`E
`A
`F
`pc+1
`
`LOAD PC WllH BRANCH ADDRESS.
`Epc - COPY PC+ 1 INTO RET.
`(EITHER Epr CAN PUSH THE RETURN ADDRESS).
`Epr - PUSH RET IF A CALL
`Fd1 - DELAY SLOT 1 INSTRUCTION FETCH.
`Fd2 - DELAY SLOT 2 INSTRUCTION FETCH.
`Fba - FETCH INSTRUCTION FROM BRANCH ADDRESS.
`INTERRUPTS LOCKED our.
`•
`-
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 22 of 35
`
`5,197,140
`
`I
`I
`I
`I
`I
`I
`SIMD •MASTER" PP TO •sLAVE" PP INTERRUPT SIGNAL
`
`SIMD • sLAvr pp TO • MASTER" pp INTERRUPT SIGNAL
`
`SIMD PAUSE (INACTIVE)
`I
`SYNC SIGNAL
`
`E
`A
`F
`Int
`
`F
`
`A
`F
`
`Int
`IN
`SLAVE
`pp
`
`\
`
`E
`A
`Fpv
`
`E
`Apv
`Fpr
`
`Epv
`Apr
`Fps
`
`Epr
`~s
`$Fin
`
`Eps
`A
`SF
`
`E
`A
`
`E
`
`pc+1
`
`pc+1
`
`pc+1
`
`pc
`
`pc
`
`pc:=vec
`ret:= c p
`
`pc+1
`
`pc+1
`
`INTERRUPT OCCURS.
`Int -
`{PC TO RET. VECTOR FETCH INTO PC).
`Fpv - PSEUDO INSTRUCTION.
`Apv - CALCULATE INTERRUPT VECTOR ADDRESS.
`Epv - COPY PC TO RET.
`FETCH INTERRUPT VECTOR INTO PC.
`Fpr - PSEUDO INSTRUCTION.
`{PUSH RET).
`Apr - C'>.l.CULATE STACK PUSH ADDRESS.
`Epr - PUSH RET ONTO STACK.
`(PUSH SR).
`Fps - PSEUDO INSTRUCTION.
`Aps - C'>.l.CULATE STACK PUSH ADDRESS.
`Eps - PUSH SR ONTO STACK. Cl.EAR S, I ~D CLD BITS IN SR.
`Fin - ARST INSTRUCTION OF INTERRUPT ROUTINE.
`S - SYNC, INTERRUPTS ~D LOOPING DISABLED UNTIL AFTER SR HAS BEEN PUSHED.
`NEITHER OF ARST TWO INSTRUCTIONS OF INTERRUPT ROUTINE MAY BE A LCK.
`FIG. 39
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 23 of 35
`
`5,197,140
`
`L
`I
`I
`I
`I
`I
`I
`I
`SIMD MASTER" PP TO • SLAVE" PP's INTERRUPT SIGNAL
`I
`PP TO • MASTER" PP INTERRUPT SIGNAL
`I
`\
`
`SIMD •s~
`
`\
`
`SIMD PAUSE
`
`SYNC SIG~
`
`I
`
`F
`
`E
`A
`
`p
`C
`
`pc
`
`p
`C
`
`p
`C
`
`p c+1
`
`A E
`Enm ... Etl
`F A
`Exb
`. . . ... A
`E
`Fid Anm
`Fnm ... . .. Fpv ~v Epv
`Fpr ~r Epr
`Int
`Eps
`Fps ~s
`Int
`$Fin A
`IN
`SF
`Slave
`pp
`+1
`c+1
`+1
`p
`p
`pc
`p
`pc
`C
`C
`IDLE INSTRUCTION FETCHED.
`Fid -
`INSTRUCTION FETCH. PIPELINE NOT LOADED.
`Fnm - NO MASTER PHASE ON
`Anm - NO MASTER PHASE ON INSTRUCTION FETCH. ADDRESS REGISTERS NOT MODIFIED.
`LOADS
`Exb - CROSSBAR ACCESS(ES) OCCUR. STORES COMPLETE TO MEMORY.
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT OPERATIONS
`KILLED.
`Enm - NO MASTER PHASE IN DATA UNIT.
`INTERRUPT OCCURS.
`Int -
`EtL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESTINATION REGISTER(S).
`DATA UNIT PERFORMS ITS ALU/MPY OPERATIONS.
`{PC TO REf. VECTOR FETCH INTO PC).
`Fpv - PSEUDO INSTRUCTION.
`~v - CALCULATE INTERRUPT VECTOR ADDRESS.
`Epv - COPY PC TO REf. FETCH INTERRUPT VECTOR INTO PC.
`{PUSH RET).
`fpr - PSEUDO INSTRUCTION.
`~r - CALCULATE STACK PUSH ADDRESS.
`Epr - PUSH RET ONTO STACK.
`{PUSH SR).
`fps - PSEUDO INSTRUCTION.
`~s - CALCULATE STACK PUSH ADDRESS.
`Eps - PUSH SR ONTO STACK. CLEAR S, I ~D CLO BITS IN SR.
`Fin - FIRST INSTRUCTION OF INTERRUPT ROUTINE.
`$ - SYNC, INTERRUPTS ~D LOOPING DISABLED UNTIL AFTER SR HAS BEEN PUSHED.
`NEITHER OF FIRST lWO INSTRUCTIONS OF INTERRUPT ROUTINE MAY BE A LCK.
`FIG. 40
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 24 of 35
`
`5,197,140
`
`FIG. 41
`I
`I
`INCOMING SYNC SIGNAL
`\
`
`OUTGOING SYNC SIGNAL (ACTIVE)
`
`I
`
`f
`
`A
`f
`
`Exb
`Anm
`Fns
`
`Enm
`. . .
`fns
`
`. . .
`Etl
`... A
`...
`f
`
`A
`F
`
`E
`A
`
`E
`
`pc +1
`p c+1
`pc +1
`pc +1
`pc
`pc
`p C
`fns - NO SYNC CONDmON. PIPE NOT LOADED. PC UNALTERED.
`Anm - NO MASTER PHASE IN ADDRESS UNIT. ADDRESS REGISTERS NOT MODIFIED.
`LOADS
`Exb - CROSSBAR ACCESS(ES) OCCUR. STORES COMPLETE TO MEMORY.
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT
`OPERATIONS KILLED.
`Enm - NO MASTER PHASE IN DATA UNIT.
`EtL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESIGNATION REGISTER(S).
`DATA UNIT PERFORMS ITS ALU/MPY OPERATIONS.
`
`LOADS: (ASSUMING NO SIGN-EXTENSION)
`
`FIG. 42
`
`(MEMORY)
`
`(REGISTER)
`
`32-BIT
`LOADS •..
`
`REG VALUE
`
`BYTE NO.
`3 2 1 0
`SOURCE DATA:
`- - - -
`0000h = D C B A
`0004h = H G f E
`= ? ? ? ?
`DESTINATION
`-
`0000h DCB A DCB A
`0004h - - - -
`DCB A
`? D C B
`0001h
`- DCB
`0005h E---
`E D C B
`? ? D C
`0002h
`- DC
`-
`F E D C
`0006h FE -
`-
`? ? ? D
`0003h ---0
`G f ED
`0007h G f E -
`
`16-BIT
`LOADS ...
`
`M>D.
`
`REG VALUE
`
`OP.
`
`ADD.
`
`0000h 0 0 B A OOBA
`0002h - - - -
`0 0 BA
`? ? ? B
`0001h ---8
`0 0 C B
`0003h 0 0 C -
`0 0 D C
`0002h 0 0 D C
`0004h - - - -
`0 0 DC
`? ? ? D
`0003h ---0
`0 0 E D
`0005h 0 0 E -
`
`LO
`LOU
`LO
`LOU
`LO
`LOU
`LO
`LOU
`
`OP.
`
`-
`
`LO
`LOU
`LO
`LOU
`LO
`LOU
`LO
`LOU
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 25 of 35
`
`5,197,140
`
`SOURCE DATA: = DCB A
`BYTE NO.
`DESTINATION DATA: = 3 2 1 0
`- - - -
`0000h = ? ? ? ?
`0004h = ? ? ? ?
`0000h
`0004h
`? ? B A
`? ? ? ?
`? ? B A
`? ? ? ?
`? ? A ?
`? ? ? ?
`? B A ?
`? ? ? ?
`? A ? ?
`? ? ? ?
`B A ? ?
`? ? ? ?
`0003h A--- A ? ? ?
`? ? ? ?
`0005h ---8 A ? ? ?
`? ? ? B
`
`STORES:
`
`ADD.
`
`16-BIT
`STORES ...
`0000h 0 0 B A
`0002h - - - -
`
`0001h --A-
`0003h -8--
`
`0002h -A--
`0004h 8---
`
`OP.
`
`ST
`
`STU
`
`ST
`
`STU
`
`ST
`
`STU
`
`ST
`
`STU
`
`OP.
`
`ST
`
`STU
`
`ST
`
`STU
`
`ST
`
`STU
`
`ST
`
`STU
`
`FIG. 43
`
`ADD.
`
`(REGISTER)
`
`(MEMORY)
`
`REG VALUE
`
`32-BIT
`STORES ...
`0000h DCB A D C B A
`? ? ? ?
`0004h - - - -
`DCB A
`? ? ? ?
`CB A?
`0001h CBA-
`? ? ? ?
`0005h ---D CB A?
`? ? ? D
`BA??
`0002h BA--
`? ? ? ?
`--DC BA??
`0006h
`? ? DC
`0003h A--- A ? ? ?
`? ? ? ?
`-DCB A???
`0007h
`? D C B
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 26 of 35
`
`5,197,140
`
`ADD WITH SATURATE
`DO, D1, D2
`02, 03, 02
`
`ADDM
`MRGM
`
`· MAXIMUM
`DO, D1, 02
`DO, D1, D2
`
`SUBM
`MRGM
`
`TRANSPARENCY
`DO, D1
`DO, D2, D3
`
`CMPM
`MRGM
`
`DO = 89 23 CD 67
`+D1 = 01 AB 45 EF
`02: = 8A CE 12 56
`MFLAGS: = ?? ?? ?? ?3
`
`DO = 89 23 CD 67
`-01 = 01 AB 45 EF
`D2: = 88 67 88 67
`MFlAGS: = ?? ?? ?? ?5
`
`DO= 89 23 CD 67
`(-)D1 = 23 23 23 23
`(= 66 00 8A 44)
`MFlAGS: = ?? ?? ?? ?4
`
`D2 = 8A CE 12 56
`D3 = FF FF FF FF
`02: = 8A CE FF FF
`
`COLOUR EXPANSION
`
`LO
`MRGM
`
`•NJ, MFlAGS
`DO, 01, 02
`
`MFLAGS = XX XX XX X6
`
`D0=11111111
`D 1 = 88 88 88 88
`D2: = 11 88 88 11
`
`DO = 89 23 CD 67
`01 = 01 AB 45 EF
`D2: = 89 AB CD EF
`
`DO = 89 23 CD 67
`D2 = 87 65 43 21
`03: = 89 65 CD 67
`
`COLOUR COMPRESSION
`
`GUIDED COPY
`
`CMPM
`
`DO, D1 , D2
`
`DO= 89 23 CD 67
`{-)D1 = 89 89 89 89
`(= 00 89 44 CD)
`MFLAGS = ?? ?? ?? ?8
`
`FIG. 44
`
`LO
`MRGM
`
`tNJ, MFLAGS
`DO, 01, D1
`
`MFlAGS = XX XX XX XC
`
`DO= 89 23 CD 67
`D1 = 87 65 43 21
`D1: = 87 65 CD 67
`
`cJ..,........up-1
`
`i
`A 17
`8.f._t--:8--------------tc e6roc:
`- · -----------1 j
`li--0
`-l----UNE OF 512 PIXEI..S------j
`
`GROUPS
`
`FIG. 45
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 27 of 35
`
`5,197,140
`
`. FIG. 46
`
`4600
`
`IMAGE
`PROCESSOR
`
`OUTPUT
`BUS
`
`4603
`
`FIG. 4 7
`
`CONTROL
`CODE
`....
`I _o __ o __ o ....,I _1 __ 0____.I
`
`4600
`
`REMOTE
`
`4800
`
`4603
`
`TRANSMISSION
`SENDER
`
`LOCAL
`
`TRANSMISSION
`RECEIVER
`
`IMAGE
`PROCESSOR
`
`4801
`
`4802
`
`FIG. 48
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 28 of 35
`
`5,197,140
`
`TELEPHONE
`LINE
`
`4902
`
`4904
`
`~!
`
`ACQUISmON
`UNIT
`
`FIG. 49
`
`4908
`4906 LIGHT 4907
`OBJECT OR
`OPTICS a.----1 DOCUMENT
`CCD's
`FOR COPYING
`
`4900
`
`ISP &
`MEMORY
`
`4903
`
`IMAGE INFORMATION
`
`5001
`
`5002
`HARD
`DRIVE
`
`5007
`STATISTICAL
`ACCUMULATED
`ECORDKEEPI
`
`ISP
`5000
`
`VIDEO
`CNTRL
`
`5003
`
`VRAM
`
`CCD's
`
`5004
`
`5008
`
`LATCH
`
`FIG. 50
`
`CONTROLLED
`MECHANISM
`
`5009
`
`DISPLAY
`
`5010
`
`HOST PRINTER
`PORT
`
`CAMERA
`
`ISP
`
`FIG. 51
`r------------ ---,
`I
`5105 1 C
`I C
`I D
`fil.Q1
`I
`5102 .------ I
`I
`MEMORY
`1 .filQ.§
`L----------------J
`
`CCD
`FLAT
`PANEL
`DISPLAY
`
`5104
`
`I
`
`1
`
`I
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 29 of 35
`
`5,197,140
`
`HOST
`
`5205
`
`BUFFER
`
`5202
`re=-=--=-.-----~.---~~~M~ORY
`
`5207
`
`SCANNER
`
`5206
`FRONT END
`PROCESSOR
`
`FIG. 52
`
`5203
`
`5204
`
`5312
`
`IMAGING
`DEVICE
`
`5318
`
`ADDRESS
`GENERATOR
`
`IMAGE
`DATA
`MEMORY
`
`IMAGE
`PROCESSOR
`
`5320
`
`5310
`~
`
`5314
`
`FIG. 53
`
`5322
`
`OUTPUT
`DEVICE
`
`5316
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 30 of 35
`
`5,197,140
`
`5424
`~
`
`z
`
`Zo
`z1
`0
`0
`---r,---- ----,
`I 5426d
`I
`428:
`5428:
`I
`I
`5430
`I
`I 0
`I
`I
`
`1 1
`
`r-----
`1 5426a
`I 5436a
`: 5434a
`:s430a
`
`,,....,___, ___ ....-<
`
`y20
`
`I
`
`,,______, 0
`I
`15438
`I
`---l5426h-
`54281
`I
`15430
`,,____, o'
`I
`I
`I
`I
`O
`1
`I
`I
`---~----- ___ L ___ _
`I 54261
`I 5426k
`54281
`5428:
`I
`I
`ls430
`:s430
`---.11
`11
`I
`I
`I
`I
`I
`I
`- - -~ - - - - - ___ i ___ _
`1
`1
`X2
`X3
`
`I
`o
`---7
`4281
`I
`I
`I
`I 0
`I
`I
`0
`I
`___ j
`I
`428:
`I
`I
`I
`I 0
`I
`I
`I
`
`,---.J
`Xo
`
`--1
`
`I
`I
`----L-----
`0
`x,
`
`X
`FIG. 54
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 31 of 35
`
`5,197,140
`
`Y2_0 __ ---.
`
`y
`
`1
`
`I
`I
`I
`
`FIG. 55
`___ 1 ____ _ --,
`55481
`I
`I
`I
`I
`I
`
`554sl5546e
`I
`I
`15550
`11--f-......._ 0 I
`I
`I
`5554 I
`___ .l_ ___ _
`1
`X2
`
`X
`
`5558:
`_5556J
`0
`X1
`
`5666
`
`r
`
`ROW
`COUNTS
`
`~5668
`0 1 2 3 4
`
`FIG. 56
`
`1 00000000
`2 00000000
`300111100
`4 00100000
`500111000
`6 00100000
`7 00100000
`8 00000000
`9 00000000
`1 2 3 4 5 6 7 8
`
`5670
`,--,
`
`COLUMN
`COUNTS
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`Mar. 23, 1993
`
`Sheet 32 of 35
`
`5,197,140
`
`5700
`
`5702
`
`8 x 64 BIT FIFO
`
`SOURCE
`ADDRESS
`GENERATOR
`
`DESTINATION
`ADDRESS
`GENERATOR
`
`EXPAND/ALIGN LOGIC
`
`I
`18
`I
`18
`
`en
`~
`~
`704 ~
`I=
`CD
`I
`N
`pr)
`
`5705
`
`5706
`
`5707
`
`5703
`
`5701
`
`...J
`0
`
`~
`
`0