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`U.S. DEPARTMENT OF COWERCE
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`PATENT AND TRADEMARK OFFICE
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`ATTORNEY DOCKET NO.:
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`CONTINUATION PATENT APPLICATION
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`2885/1 39
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`TRANSMITTAL LETTER
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`UNDER 37 CPR. 153(1))
`Address to:
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`Commissioner for Patents
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`PO. Box 1450
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`Alexandria, VA 223 13~1450
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`Transmitted herewith for filing is a patent application.
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`Inventor(s):
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`Martin VORBACH —- Berliner Strasse 50, 67360 Lingenfeld, Federal Republic of Germany
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`For: RECONFIGURABLE SEQUENCER STRUCTURE
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`Enclosed are:
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`A.
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`-25— pages of specification, 4— pages of claims, and —I— page of abstract;
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`B.
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`~6- sheet(s) of drawing(s);
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`Preliminary Amendment; and
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`D. Declaration and Appointment of Power of Attorney (copies from prior application
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`(37 ‘CFR 1.63(d) and 3.7303) Statement) (See paragaph 5 below);
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`Incorporation by Reference. The entire disclosure of the prior application, from
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`which a copy of the oath or declaration is supplied under paragraph 1(D) above is
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`considered as being part of the disclosure of the accompanying application and is
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`hereby incorporated by reference therein.
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`Related Applications:
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`This application is a continuation of and claims priority to U.S. Patent Application No.
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`12/541,299, filed August 14, 2009, which is a continuation of and claims priority to U.S.
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`Patent Application Serial No. 12/082,073, filed on April 7, 2008, which is a continuation of
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`and claims priority to U.S. Patent Application Serial No. 10/526,595, filed on January 9,
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`2006, which was the National Stage of International Application Serial No. PCT/EPOS/ 38599,
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`filed on September 8, 2003, which claims benefit of and priority to German Patent
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`Application Serial No. DE 102 41 8128, filed on September 6, 2002, the entire contents of
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`each of which are expressly incorporated in the accompanying application by reference
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`Page 1
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`INTEL - 1004
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`INTEL - 1004
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`The filing fee has been calculated as shown below:
`FILING FEES
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`4.
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`EXAMINATION FEE
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`TOTAL CLAIMS
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`MULTIPLE DEPENDENT CLAIM PRESENT
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`La
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`TOTAL CLAIMS FEES
`520.00
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`k-;"':l3id{liticrlal fee for specification and drawings filed in paper over 100 sheets (excluding sequence listing or
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`computer program listing filed in an electronic medium). The fee is $250 for each additional 50 sheets ofpaper
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`or fraction thereof.
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`Tom sheetsm'
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`’50: — x 5250-00
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`TOTAL FEES =
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`TOTAL BASIC, EXAM AND SEARCH FEES
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`NUMBER
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` Ifthe applicant is a small entity under 37 C.F.R. §§ 1.9 SMALL ENTITY 805.00 (722.00
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`and 1.27, then divide total fee by 2, and enter amount here.
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`if e—filing)
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`5.
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`The required application filing fee and claim fees of $805.00 ($722.00 for e-filing) is
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`being paid by credit card.
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`Dated: July 14, 2010
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`Customer No.: 26646
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`Resp ectfully submitted,
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`By:
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`/Aaron Grunberger/
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`Aaron Grunberger
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`Reg. No. 59,210
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`KENYON & KENYON
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`One Broadway
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`New York, New York 10004
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`(212) 425—7200 (telephone)
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`(212) 425-52 88 (facsimile)
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`Page 2
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`INTEL - 1004
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`Page 2 of 539
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`INTEL - 1004
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`directly or by one or more bus systems. PAEs are arranged in
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`any configuration, mixture and hierarchy,
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`known as a PAE array or, for short, a PA. A configuring unit
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`the system being
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`RECONFIGURABLE SEQUENCER STRUCTURE
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`[2885/139]
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`Description
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`The present invention relates to a cell element field and a
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`method for operating same. The present invention thus relates
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`in particular to reconfigurable data processing architectures.
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`The term reconfigurable architecture is understood to refer to
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`units (VPUs) having a plurality of elements whose function
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`and/or interconnection is variable during run time. These
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`elements may include arithmetic logic units, FPGA areas,
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`input/output cells, memory cells, analog modules, etc. Units
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`of this type are known by the term VPU, for example. These
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`typically include arithmetic and/or logic and/or analog and/or
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`memory and/or interconnecting modules and/or communicative
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`typically referred to as PAEs, which
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`peripheral modules
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`(108),
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`are arranged in one or more dimensions and are linked together
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`may be assigned to the PAE.
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`principle systolic arrays, neural networks, multiprocessor
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`systems, processors having multiple arithmetic units and/or
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`In addition to VPU units,
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`in
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`logic cells,
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`interconnection and network modules such as
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`crossbar circuits, etc., as well as FPGAs, DPGAs,
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`transputers,
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`etc., are also known
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`It should be pointed out that essential aspects of VPU
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`technology are described in the following protective rights of
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`the same applicant as well as in the particular follow—up
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`applications to the protective rights listed here:
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`P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2,
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`DE 196 54 846.2v53, DE 196 54 593.5-53, DE 197 O4 O44.6~53,
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`NY01 1974077 V1
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`INTEL - 1004
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`Page 3 of 539
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`INTEL - 1004
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`DE 198 80 129.7, DE 198 61 088.2—53, DE 199 80 312.9,
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`PCT/DE 00/01869, DE 100 36 627.9—33, DE 100 28 397.7,
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`DE 101 10 530.4, DE 101 11 014.6, PCT/EP 00/10516,
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`EP 01 102 674.7, DE 102 06 856.9, 60/317,876, DE 102 02 044.2,
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`DE 101 29 237.6953, DE 101 39 170.6.
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`It should be pointed out that the documents listed above are
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`incorporated in particular with regard to particulars and
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`details of the interconnection, configuration, embodiment of
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`architecture elements,
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`trigger methods, etc., for disclosure
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`purposes.
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`The architecture has considerable advantages in comparison
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`with traditional processor architectures inasmuch as data
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`processing is performed in a manner having a large proportion
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`of parallel and/or vectorial data processing steps. However,
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`the advantages of this architecture in comparison with other
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`processor units, coprocessor units or data processing units in
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`general are not as great when the advantages of
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`interconnection and of the given processor architectonic
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`particulars are no longer achievable to the full extent.
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`This is the case in particular when data processing steps that
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`are traditionally best mappable on sequencer structures are to
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`be executed. It is desirable to design and use the
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`reconfigurable architecture in such a way that even those data
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`processing steps which are typically particularly suitable for
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`being executed using sequencers are executable particularly
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`rapidly and efficiently.
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`The object of the present invention is to provide a novel
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`device and a novel method for commercial application-
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`The method of achieving this object is claimed independently.
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`Preferred embodiments are characterized in the subclaims.
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`INTEL - 1004
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`INTEL - 1004
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`According to a first essential aspect of the present
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`in the case of a cell element field whose function
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`and/or interconnection is reconfigurable in particular during
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`invention,
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`run time without interfering with unreconfigured elements for
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`data processing with coarsely granular function cell elements
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`in particular for execution of algebraic and/or logic
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`functions and memory cell means for receiving, storing and/or
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`outputting information, it is proposed that function cell—
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`memory cell combinations be formed in which a control
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`connection to the memory means is managed by the function cell
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`means. This control connection is for making the address
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`and/or data input/output from the memory controllable through
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`the particular function cell,
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`typically an ALU—PAE. It is thus
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`possible to indicate, for example, whether the next
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`information transmitted is to be handled as an address or as
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`data and whether read and/or write access is necessary. This
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`transfer of data from the memory cell, i.e., the memory cell
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`item of
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`means, which may be a RAM—PAE, for example,
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`cell means, which may be an ALU—PAE, for example,
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`it possible for new commands that are to be executed by the
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`to the function
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`then makes
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`by integration into a structural unit.
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`ALU to be loadable into the latter. It should be pointed out
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`that function cell means and memory cell means may be combined
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`In such a case it is
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`possible to use a single bus connection to input data into the
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`memory cell means and/or the ALU. Suitable input registers
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`and/or output registers may then be provided and, if desired,
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`additional data registers and/or configuration registers
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`different from the former may also be provided as memory cell
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`It should also be pointed out that it is possible to construct
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`a cell element field containing a plurality of different cells
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`and/or cell groups, strips or similar regular patterns being
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`preferably provided with the different cells because these
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`NYOl 1974077 v1
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`3
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`INTEL - 1004
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`INTEL - 1004
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`permit a very regular arrangement while facilitating the
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`design equally in terms of hardware design and operation. With
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`such a strip—like arrangement or other regular layout of a
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`small plurality of different cell elements, for example,
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`elements having integrated function cell means—memory cell
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`means combinations, i.e., cells in which function cell means
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`recognized,
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`and memory cell means are integrated according to the present
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`invention, are provided centrally in the field, where
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`typically only a few different program steps are to be
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`executed within a sequencer structure because, as has been
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`this provides very good results for traditional
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`data stream applications, while more complex sequencer
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`structures may be constructed at the edges of the field where,
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`for example, an ALU—PAE which represents a separate unit
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`possibly may be provided in addition to a separate RAM—FAB and
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`optionally a number of I/O-PAEs using, i.e., arranging
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`appropriate control lines or connections thereof because
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`frequently more memory is needed there, e.g.,
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`to temporarily
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`store results generated in the field central area of the cell
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`element field and/or for datastreaming,
`to pre—enter and/or
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`process data needed thereby.
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`When cells that integrate memory cell means and function cell
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`in the center of the field, a small
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`means are provided, e.g.,
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`memory may then be provided there for different commands to be
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`executed by the function cell means such as the ALU. It is
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`possible here in particular to separate the command memory
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`and/or the configuration memory from a data memory, and it is
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`possible to design the function memory to be so large that
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`alternatively, one of several, e.g.,
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`two different sequences
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`may be executed. The particular sequence to be executed may
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`occur in response to results generated in the cell and/or
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`control signals such as carry signals, overflow signals,
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`and/or trigger signals arriving from the outside.
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`In this way,
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`NYOl 1974077 v1
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`4
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`INTEL - 1004
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`Page 6 of 539
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`INTEL - 1004
`Page 6 of 539
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`this arrangement may also be used for wave reconfiguration
`methods.
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`In this way it is possible to construct a sequencer structure
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`in a cell element field by providing a dedicated control
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`connection controlled by function cells in a dedicated manner
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`between function cell and function cell means and memory cell
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`and/or memory cell means with only two elements connected by
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`suitable buses without requiring additional measures and/or.
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`design changes otherwise. Data, addresses, program steps,
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`etc., may be stored in the memory cell in a manner known per
`se from traditional processors. Since both elements, if
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`properly configured, may also be used in another way,
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`this
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`yields a particularly efficient design which is particularly
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`adaptable to sequencer structures as well as vectorial and/or
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`parallelizable structures. Parallelization may thus be
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`supported merely via suitable PAE configurations, i.e., by
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`providing PAEs that operate in two different spatial
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`directions and/or via cell units equipped with data throughput
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`registers.
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`It is clear here that a plurality of sequencer type structures
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`may be constructed in the reconfigurable cell element field by
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`using only two cells in a cell element field, namely the
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`function cell and the information processing cell. This is
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`advantageous inasmuch as a number of different tasks that are
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`different from one another per se must often be executed in
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`in a multitasking—capable operating
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`system. A plurality of such tasks must then be executed
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`effectively and simultaneously in a single cell element field.
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`data processing, e.g.,
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`The advantages of real time applications are obvious.
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`Furthermore it is also possible to operate the individual
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`sequencer structures that are constructed in a cell element
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`field, providing the control connection according to the
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`present invention, at different clock rates, e.g.,
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`to lower
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`NYOl 1974077 v1
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`5
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`INTEL - 1004
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`Page 7 of 539
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`INTEL - 1004
`Page 7 of 539
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`power consumption by executing lower priority tasks at a
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`slower rate. It is also possible to execute sequencer type
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`program parts in the field in parallel or vectorially in
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`execution of algorithms that are largely parallel per se and
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`vice versa.
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`Typically, however, it is preferable for sequencer—type
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`structures to be clocked at a higher rate in the cell element
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`field, whether they are sequencer~type structures having an
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`area connected to neighboring cells or buses or whether they
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`are combinations of spatially differentiable separate and
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`separately useable function cell elements such as ALU—PAEs and
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`memory cell elements such as RAM—PAEs. This has the advantage
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`that sequential program parts, which are very difficult to
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`parallelize in any case, may be used in a general data flow
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`processing without any negative effect on the overall data
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`processing. Examples of this include, e.g., a HUFFMANN coding
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`which is executable much better sequentially than in parallel
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`and which also plays an important role for applications such
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`in this case the essential other parts of
`as MPEG4 coding, but
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`the MPEG4 coding are also easily parallelizable. Parallel data
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`processing is then used for most parts of an algorithm and a
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`sequential processing block is provided therein. An increase
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`in the clock frequency in the sequencer range by a factor of 2
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`to 4 is typically sufficient.
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`It should be pointed out that instead of a strip arrangement
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`of different cell elements, another grouping,
`in particular a
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`multidimensional grouping, may also be selected.
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`The cell element field having the cells whose function and/or
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`interconnection is configurable may obviously form a
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`30
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`processor, a coprocessor and/or a microcontroller and/or a
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`parallel plurality of combinations thereof.
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`NYOl 1974077 v1
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`6
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`INTEL - 1004
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`Page 8 of 539
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`INTEL - 1004
`Page 8 of 539
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`The function cells are typically formed as arithmetic logic
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`units, which may be in particular coarsely granular elements
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`but may also be provided with a fine granular state machine,
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`for example.
`In a particularly preferred exemplary embodiment,
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`the ALUs are extended ALUs
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`patent applications of the present applicant. An extension may
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`(EALUs) as described in previous
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`include in particular the control line check, command decoder
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`unit, etc., if necessary.
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`The memory cells may store data and/or information in a
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`volatile and/or nonvolatile form. When information stored in
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`the memory cells, whether program steps, addresses for access
`to data or data stored in a register~type form, i.e., a heap
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`is stored as volatile data, a complete reconfiguration may
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`take place during run time. Alternatively it is possible to
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`provide nonvolatile memory cells. The nonvolatile memory cells
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`may be provided as an EEPROM area and the like, where a
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`rudimentary BIOS program that is to be executed on boot—up of
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`the system is stored. This permits booting up a data
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`processing system without additional components. A nonvolatile
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`data memory may also be provided if it is decided for reasons
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`of cost and/or space that the same program parts are always to
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`be executed repeatedly, and it is also possible to alternate
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`among such fixed program parts during operation, e.g.,
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`manner of a wave reconfiguration. The possibilities of
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`providing and using such nonvolatile memories are the object
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`of other protective rights of the present applicant. It is
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`possible to store both volatile and nonvolatile data in the
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`in the
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`memory cells, e.g., for permanent storage of a BIOS program,
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`and nevertheless be able to use the memory cell for other
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`30
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`purposes.
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`The memory cell is preferably designed to be able to store a
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`sufficient variety of data to be executed and/or program parts
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`to be executed. It should be pointed out here that these
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`NYOl 1974077 v1
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`7
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`INTEL - 1004
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`Page 9 of 539
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`INTEL - 1004
`Page 9 of 539
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`program parts may be designed as program steps, each
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`specifying what an individual PAE,
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`PAE, i.e.,
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`in particular the assigned
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`in particular the function cell controlling the
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`is to do in the next step, and they may also
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`memory cell,
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`include entire configurations for field areas or other fields.
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`In such a case, it is readily possible for the sequencer
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`structure that has been created to issue a command on the
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`basis of which cell element field areas are reconfigured. The
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`function cell triggering this configuration then operates as a
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`load logic at the same time. It should be pointed out that the
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`configuration of other cells may in turn be accomplished in
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`such a way that sequencer type data processing is performed
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`there and it is in turn possible in these fields to configure
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`and/or reconfigure other cells in the course of program
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`[execution]. This results in an iterative configuration of
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`cell element areas, and nesting of programs having sequencer
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`structures and parallel structures is possible,
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`these
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`structures being nested one inside the other like babushka
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`dolls. It should be pointed out that access to additional cell
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`element fields outside of an individual integrated module is
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`possible through input/output cells in particular, which may
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`massively increase the total computation performance. It is
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`possible in particular when configurations occur in a code
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`part of a sequencer structure configured into a cell element
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`if necessary,
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`the configuration requirements
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`field to perform,
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`on an assigned cell element field which is managed only by the
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`particular sequencer structure and/or such requirements may be
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`issued to a configuration master unit to ensure that there is
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`uniform occupancy of all cell element fields. This therefore
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`results in a quasi—subprogram call by transferring the
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`required configurations to cells or load logics. This is
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`regarded as independently patentable. It should be pointed out
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`that the cells,
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`if they themselves have responsibility for
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`configuration of other cell element field areas, may be
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`NYOl 1974077 v1
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`8 ‘
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`INTEL - 1004
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`Page 10 of 539
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`INTEL - 1004
`Page 10 of 539
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`provided with FILMO structures and the like implemented in
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`hardware or software to ensure proper reconfiguration. The
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`possibility of writing to memory cells while executing
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`instructions,
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`thereby altering the code, i.e.,
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`be executed, should be pointed out.
`In a particularly
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`the program to
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`preferred variant, however,
`
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`is suppressed by appropriate control via the function
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`this type of self—modification
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`(SM)
`cell.
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`It is possible for the memory cell to send the information
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`10
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`stored in it directly or indirectly to a bus leading to the
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`function cell in response to the triggering of the function
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`cell controlling it. Indirect output may be accomplished in
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`particular when the two cells are adjacent and the information
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`requested by the triggering must arrive at the ALU~PAE via a
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`bus segment that is not directly connectable to the output of
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`the memory cell.
`In such a case the memory cell may output
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`data onto this bus system in particular via backward
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`registers. It is therefore preferable if at least one1 memory
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`cell and/or function cell has such a backward register, which
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`may be situated in the information path between the memory
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`cell and function cell.
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`In such a case,
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`these registers need
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`15
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`25
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`not necessarily be provided with additional functionalities,
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`although this is readily conceivable, e.g., when data is
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`requested from the memory cell for further processing,
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`corresponding to a traditional LOAD of a typical
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`microprocessor for altering the data even before it is loaded
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`to implement a LOAD++ command. Data
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`into the PAE, e.g.,
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`conduction through PAEs having ALUs and the like operating in
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`the reverse direction should be mentioned.
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`The memory cell is preferably situated to receive information
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`from the function cell controlling it,
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`information saving via
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`1 TN: omitting “von” (eine von Speicherzellem)
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`NYOl 1974077 v1
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`9
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`INTEL - 1004
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`Page 11 of 539
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`INTEL - 1004
`Page 11 of 539
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`an input/output cell and/or a cell that does not control the
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`In particular when data is to
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`memory cell also being possible.
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`be written into the memory cell from an input/output cell, it
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`is preferable if this input/output cell
`is also
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`(I/O—PAE)
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`controlled by the function cell. The address at which
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`information to be written into the memory cell or,
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`if
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`necessary,
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`cell
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`(PAE)
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`In such a case,
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`to also be transmitted directly to the function
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`is to be read, may also be transferred to the I/O—
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`In this connection it should be pointed
`PAE from the ALU—PAE.
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`out that this address may be determined via an address
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`translation table, an address translation buffer or an MMU
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`type structure in the I/OwPAE.
`this yields the
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`full functionalities of typical microprocessors. It should
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`also be pointed out that an I/O functionality may also be
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`integrated with a function cell means, a memory cell means
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`and/or a function cell means—memory cell means combination.
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`In a preferred variant, at least one input-output means is
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`thus assigned to the combination of function cells and memory
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`cells, whether as an integrated function cell and a memory
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`cell combination or as a function cell and/or memory cell
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`combination composed of separate units,
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`the input/output means
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`being used to transmit information to and/or receive
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`information from an external unit, another function cell,
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`function cell memory cell combination and/or memory cells.
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`The input—output unit is preferably likewise designed for
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`receiving control commands from the function cell and/or the
`function cell means.
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`In a preferred variant,
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`the control connection is designed to
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`transmit some and preferably all of the following commands:
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`30
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`OPCODE FETCH,
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`DATA WRITE INTERNAL,
`DATA WRITE EXTERNAL
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`NY01 1974077 v1
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`
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`3.0
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`
`
`INTEL - 1004
`
`Page 12 of 539
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`INTEL - 1004
`Page 12 of 539
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`DATA READ EXTERNAL,
`POINTER
`ADDRESS
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`ADDRESS
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`POINTER
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`ADDRESS
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`ADDRESS
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`PROGRAM
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`PROGRAM
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`PROGRAM
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`PROGRAM
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`POINTER
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`POINTER
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`POINTER
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`POINTER
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`POINTER
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`POINTER
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`WRITE INTERNAL,
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`WRITE EXTERNAL,
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`READ INTERNAL,
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`READ EXTERNAL,
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`WRITE INTERNAL,
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`WRITE EXTERNAL,
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`READ INTERNAL,
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`READ EXTERNAL,
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`STACK POINTER WRITE INTERNAL,
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`STACK POINTER WRITE EXTERNAL,
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`STACK POINTER READ INTERNAL,
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`STACK POINTER READ EXTERNAL,
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`PUSH,
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`15
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`POP,
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`PROGRAM POINTER INCREMENT.
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`This may be accomplished through a
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`corresponding bit width of
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`the control line and an associated
`decoding at the receivers.
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`The particular required control means and decoding means may
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`be provided inexpensively and with no problems. As it shows, a
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`practically complete sequencer capability of the arrangement
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`is obtained with these commands. It should also be pointed out
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`that a general~purpose processor data processing unit is
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`obtained in this way.
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`10
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`2O
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`25
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`The system is typically selected so that the function cell is
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`the only one able to access the control connection and/or a
`the control
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`bus segment,
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`i.e., bus system functioning as
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`The result is thus a
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`connection as a master.
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`system in which
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`the control line functions as a command line
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`provided in traditional processors.
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`30
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`such as that
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`The function cell and the memory cell,
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`preferably adjacent to one another.
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`
`NYOl 1974077 V1
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`11
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`The term
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`I/O cell, are
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`”adjacent" may be
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`INTEL - 1004
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`Page 13 of 539
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`INTEL - 1004
`Page 13 of 539
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`understood preferably as the cells being situated directly
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`side by side. "Directly" means in particular a combination of
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`such cells to form integrated units which are provided
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`repeatedly on the cell element field, i.e., as part of same to
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`form the field. This may mean an integral unit of memory cells
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`they are at least close
`and logic cells. Alternatively,
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`together. The system of the function cells and memory cells in
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`integrated, i.e., close, proximity to one another thus ensures
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`that there are no latency times, or at least no significant
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`latenCy times, between triggering and data input of t