® ‘0)
`
`Europaisches Patentamt
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`European PatentOflfce _
`Office européen des brevets
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`'® Publicationnumberaf'
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`O 071 727
`A1
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`@
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`EUROPEAN PATENT APPLICATION
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`I.
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`@ Application number;821osms
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`@ lnt.Cl.’: G 06 F 15/06
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`® Date offiling:23.06.82
`
`® Priority: 24.07.81 us 286426
`24.07.01 US 288424
`24.07.81 US 286425
`
`.
`@ Date of publication of application: 16.02.83
`Bulletin 83/7
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`® Designated Contracting States: DE FR es NL
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`® Restructurable integrated circuit.
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`@ A restructurable integrated circuit. including four 16-bit
`processors PRO, PR1, PR2, PR3. data and control memories
`68 and 78, and external interfaces 72, 73, 74. 75, 76 all
`mounted on a chip. The processors include reconfigurable
`connections through a status bus 52. microprogramming
`capability with dynamic logic array interpretation, and a
`multi-level flexible Interrupt management system, so that
`the processors PRO-PR3 may be reconfigured program-
`mably to operate independently, in lockstep. or as pipelined
`F processors. All processors PRO-PR3 are connected to data,
`control, and status buses 56, 14, and 52. In addition. exter-
`nal control. data. and status interfaces 72—76 are also
`h provided, connected through the respective corresponding
`busses 56. 14. and 52 to each of the processors PRO-PR3.
`N These external interfaces are connected to all of the inter-
`h connections which permit
`reconfigurability among the
`processors on a chip. and these external interfaces permit
`F coordination of the processors on more than one RIC chip.
`
`EP007
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`® Applicant: TEXAS INSTRUMENTS INCORPORATED,
`13500 North Central Expressway. Dallas
`Texas 75265 (08)
`
`® Inventor: Budzlnsld, Robert L. 1106 Edgewood Drive.
`Richardson Texas 75081 (US)
`Inventor: Thatte. Satieh M., 1304 Elk Grove, Richardson
`Texas 75081 (US)
`
`® Representative: Lelser, Gottfried, DlpL-lng. et ai,
`Patentanwilte Prinz. Bunke a: Partner Emsberger
`Strasse 19, 0.8000 Mllnchen so (as)
`
`
`
`"
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`couraouron: “nun
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`- INTERIUH‘
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`EXTERNAL I
`- DATAPOIT
`72
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`IAI IEIOIY
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`ACTORUM AG
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`INTEL - 1006
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`INTEL - 1006
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`n.
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`RESTRUCTURABLE INTEGRATED CIRCUIT
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`0071727
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`SPECIFICATION
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`Background of the Invention
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`5
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`This invention relates to a restructurable integrated
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`circuit which includes multiple 16—bit processors all
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`accessing a common memory, with the interconnections
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`between the processors being alterable in software so that
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`the restructurable IC may be operated in a variety of
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`different computing configurations.
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`A major difficulty in taking advantage of
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`the
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`possible economies offered by VLSI
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`technology is that few
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`prOSpective VLSI parts can be produced in sufficient
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`quantity to bring the price down to an attractive level.
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`In particular, since many applications impose their own
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`particular constraints on processor function, special
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`processors for such applications have been custom—
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`designed, at a necessarily high cost.
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`It is a particular object of the present invention to
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`satisfy the peculiar processing requirements of many
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`different applications by one common IC chip design, which
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`can therefore be manufactured in large quantities
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`economically.
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`In addition to a main processor,
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`it is often
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`1)
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`advantageous to use a dedicated processor for controlling
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`for memory
`I/O functions (such as CRT display),
`management, or for specialized arithmetic processing.
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`However, as noted above,
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`the high cost of custom VLSI
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`design has prevented optimal exploitation of
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`the
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`advantages provided by such dedicated processors.
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`It is a further object of the present
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`invention to
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`provide means for easily configuring a dedicated special-
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`purpose processor by means of a unsPecialized common IC.
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`It
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`is often particularly advantageous,
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`in
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`implementing such dedicated processors,
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`to integrate them
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`on a single chip with a general-purpose processor.
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`~ However, such structures require further specialization of
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`the design,
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`and are therefore subject
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`to cost
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`disadvantages as discussed above.
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`INTEL-1006
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`It is a further object of the present invention to
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`permit integration of a general-purpose processor with one
`or more special-purpose processors on a single chip, by
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`means of a general—purpose reconfigurable IC which can
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`5 easily be'manufactured in quantity.
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`7 A further disadvantage of custom VLSI design is that,
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`together with cost, yield, and reliability of the finished
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`part normally improve as the manufacturing history of the
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`part proceeds along the "learning curve". However, custom
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`lospecial—purpose designs are normally not manufactured in
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`large enough numbers over a large enough period of time to
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`permit exploitation of the progressive improvement of
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`cost and reliability.
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`invention is
`A further object of the present
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`15 therefore to provide a general purpose part which can be
`.7 manufactured in large quantity over a long period of time,
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`to permit exploitation of cost yield, and reliability
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`improvements obtained by progress along the "learning
`curve".
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`they often have
`Expensive as custom VLSI designs are,
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`the further disadvantage that the gate density is
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`relatively low. This is because, for a part which will be
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`produced in small quantities, it is not economical
`Spend the additional time and money to optimize ther
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`25 packing density.
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`Thus, it is a further object of the present invention
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`to provide an integrated circuit which can satisfy the
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`requirements of a custom integrated circuit while
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`retaining a high gate density.
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`Gate arrays provide an extremely flexible LSI or VLSI
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`part, and gate arrays do satisfy some special functions
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`(such as a high speed multiplier or a cross bar switch)
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`efficiently. However, gate arrays are not very well
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`adapted to supporting programmable systems, and the gate
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`35 density of a gate array is normally not as high as that of
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`Thus, it is'a further object of the present invention
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`to provide-a restructurable integrated circuit which has a
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`higher gate density than a gate array, and is better
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`INTEL-1006
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`(In
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`W:
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`INTEL - 1006
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`adapted to supporting a programmable system.
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`Where relatively large and complicated systems must
`be mathematically modelled, it is frequently desirable to
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`have a large array processor, where, even though the data
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`throughput capacity of each processor is relatively low,
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`‘the total data throughput is extremely high, due to the
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`large degree of parallelism. However, such array
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`processors have to date been relatively expensive, since
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`they were usually constructed as special-purpose systems.
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`Similarly, it is sometimes desirable to perform a
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`long series of computations on an extremely wide
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`multiple—precision word (e.g., where a complex orbital
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`system must be modeled over a very long period of time.)
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`In this case also, adaptation of existing systems has
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`15 normally imposed disadvantages of high cost,
`low speed, or.
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`invention
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`invention
`Thus, it is a further object of the present
`to provide a processor in an integrated circuit, such that
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`a number of these integrated circuits can be combined to
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`processing cheaply, without custom hardware design.
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`A further crucial disadvantage of custom VLSI designs
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`is that the design cycle time is unavoidably long, since
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`redesign and testing of hardware is required.
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`Thus, it is a further object of the present
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`to provide an integrated circuit which can be reconfigured
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`for custom applications solely by changes to software
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`and/or firmware.
`Additional background references on multiple
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`30 processing systems, dynamic architecture, and micro—
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`processor architecture generally,
`include the following:
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`Multiprocessors and Parallel Processing (ed. P. Enslow,
`Jr. 1974); A. Abd-Alla & A. Meltzer, Principles of. Digital
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`Computer Design (1976); C. Mead & L. Conway, Introduction
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`35 to VLSI Systems (1980); R. Krutz, Microprocessors and
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`Logic Design (1980); G. Myers, Advances in Computer
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`Architecture (1978); Baer, Multiprocessing Systems,
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`25 IEEE Transactions on Computers 1271 (1976); Thurber &
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`Wald, Associative and Parallel Processors,
`7 Computing
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`INTEL-1006
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`INTEL - 1006
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`4
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`Surveys 215 (1975); Kartashev & Kartashev, Dynamic
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`Architectures: Eroblems and Solutions, Computer Magazine,
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`July '78,
`26; Kartashev & Kartashev, A Multicomputer
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`System with Dynamic Architecture, 28 IEEE Transactions on
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`Computers 704 (1979); Kartashev & Kartashev, Super Systems
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`for the 80's, Computer Magazine, November 1980, at ll; and
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`Vick, Adaptable Architectures for Super Systems, Computer
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`Magazine, November 1980 at 17; all of which are hereby
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`.incorporated by reference.
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`It is often advantageous, particularly where
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`unsophisticated users are involved,
`to design a very high
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`level application language which is tailored to a specifier
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`job. However, such application languages, if embodied in
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`software, are normally very slow, and if embodied in
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`hardware, are normally very expensive.
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`It is thus a further object of the present invention
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`to provide means for economically providing VLSI
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`processors which are adapted to interpret any desired
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`application language.
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`The many advantages of multi—processor systems have
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`seldom been efficiently exploited, partly because it has
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`always been difficult to train programmers to adapt their
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`programming so as to be optimal on a multi—processorr
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`rather than a uniprocessor system. Thus, it is a further
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`object of the present invention to provide a system which
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`is easily reconfigurable between a multiprocessing and a
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`uniprocessing system, so that programmers may gradually
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`accustom themselves to the advantages and requirements of
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`A further difficulty with the exploitation of
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`hardware structures.
`Since much of the behavor of a
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`structure, and since all hardware structures yet suggested
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`appear to be optimized for one type of problem but not for
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`another, no multiprocessor hardware structure has yet been
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`achieved which appears to be a truly general—purpose
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`system.
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`Thus it is a further object of the present invention
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`INTEL-1006
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`INTEL - 1006
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`to provide a multi-processor hardware structure which is
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`reconfigurable, and which thereby provides a truly
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`general—purpose multiprocessor hardware structure.
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`A further difficulty which has arisen in many
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`5 multiprocessor systems is the problem of interprocessor
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`interference, which occurs when more than one processor
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`attempts to access the same area of memory.
`It is
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`possible to restrict the area of memory which may be
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`‘accessed by any one processor, but, while this avoids the
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`much of the advantage of a multiprocessor system.
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`Thus, it is a further object of the present invention
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`to provide a multiprocessor architecture which, while
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`permitting every processor to access any area of memory,»
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`15 protects data integrity.
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`Emulation of microprocessor languages and
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`architectures, and of micro— and minicomputer systems,
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`at present relatively expensive.
`If emulation could be
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`made cheaper, e.g. based on a single prOcessing chip,
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`the cheaper development and testing possible would permit
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`wider use of custom designed application systems, and
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`faster adoption of new innovations.
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`invention is to
`A further object of the present
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`provide a single-chip processor capable of versatile and
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`25 efficient emulation.
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`It would also be desirable to provide a
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`microprocessor architecture which would permit graceful
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`degradation in the event of failure. Thus, both
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`reliability and yield could be greatly improved, since the
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`30 first major hardware fault would not prevent function of a
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`chip, but would simply degrade its preformance marginally.
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`It is a further object of the present invention to
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`provide a microprocessing architecture which provides
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`graceful degradation, rather than catastrophic failure,
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`the event of hardware fault.
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`in
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`the advantages of
`Only minor exploration of
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`multiprocessor systems including large numbers of
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`processors has hetherto been undertaken, because of the
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`expense of multiple processors,
`the difficulty of
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`INTEL-1006
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`INTEL - 1006
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`interconnecting them, and the extreme difficulty of
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`specifying appropriate protocols for the interface between
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`processors in a large system.
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`Thus, it is a further object of the present
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`invention to provide processors which can easily be
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`combined into a multi-processor system including any
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`A further difficulty, if lC processors are to be made
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`capable of combination into multi-processor systems,
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`the provision of additional hardware on chip for interface
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`I/O communication, receipt
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`interprocessor communication with external processors‘
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`are functions which will require excess hardware if
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`implemented separately.
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`Thus, it is a further object of the present invention
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`to provide an external interface which can both handle I/O
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`communications inmediate interprocessor communication.
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`It is a further object of the present invention to
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`provide an interrupt managing structure,
`in each
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`processor, such that interrupts can be used both to govern
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`interprocessor communication and to transmit externally
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`generated interrupts.
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`When a change in operating function or structure of a
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`processor system is required, logic redesign is not only
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`expensive and difficult, but also time consuming.
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`Thus it is a further object of the present invention
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`to permit ready alteration of processor operation, at any
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`level, by reprogramming rather than by logic redesign.
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`It would be highly desirable to have a processor
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`hardware system to which an "architecture compiler" could
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`be applied.
`Such a compiler would permit programming of
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`the effective architecture of the system,
`in addition to
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`the other changes normally possible by programming.
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`35 However,
`to support such a compiler it is necessary to
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`have hardware which permits selective and programmable
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`reconfiguration of functional interconnections.
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`Thus, it is a further object of the present invention
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`to provide a processor architecture having the necessary
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`INTEL-1006
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`alterable functional structure to support an architecture
`compiler.
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`Summary of the Invention
`Th e
`p r e s e n t i n v e n t i o n p r o v i d e s fo r fo u r
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`5
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`15
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`microprogrammable 16-bit microprocessors on a single
`chip. Microprogramming capability is provided by a large
`PLA which is included in each process or. Each of the
`processors is connected to each of three main buses,
`10 namely the status bus, the data bus, and the control bus.
`Each p rocessor is connected to the status bus by a
`respective status bus multiplexer, which operates as a
`programmable interconnect. In accordance with the various
`configurations of the status bus connections which are
`th u s p o s s ibl e , t h e p r o c e s s ors m a y b e o perated
`independent l y (e.g. as four 16-bit processors), in
`lockstep (e.g. as one 64-bit processor), or pipelined.
`Thus, two major sources of programming flexibility are
`provided:
`the microprogramming flexibility provided by
`20 PLA interpretation, and the processor reconfiguration
`fle x i b i l i t y w h ich is p r o v i d e d by t h e use of the
`programmable status bus connections and by controlling the
`instruction streams interpreted by each proc�ssor.
`To exploit this flexibility in processor control,
`25 each chip level instruction is directed to one or more
`specific processors. Thus, when it is desired to operate
`the p r o cessors in a pipeline mode (where separate
`processors sequentially perform different operations on a
`single data stream), each processor is respectively
`30 instructed to perform the operation appropriate to its
`pos i t ion i n t he p i pe l i ne seq uence. In l o ckstep
`processing, one processor is designated as the master
`processor (to control sequencing etc.), and the other
`lockstepped processors are all controlled simultaneously.
`35 These modes of reconfiguration may also be combined, so
`that, e.g., a chip might be reconfigured to contain four
`independent 16-bit processors, two pipelined 32-bit
`processors,. one 4 8-bi t processor (three locks tepped 16-bi t
`processors) and one independent 16-bit processor, etc.
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`•
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`INTEL - 1006
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`Since the control bus may be segmented to carry plural
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`unrelated sequences of instructions,
`a multilevel
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`interrupt hierarchy is used, arbitrated by a single
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`control store manager,
`to arbitrate access to the control
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`The external
`interface controls (including an
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`external interrupt manager,
`two external status ports and
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`two external data ports) also permit processors on more
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`than one RIC chip to be linked together in the various
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`modes discussed above. In addition,
`the external interface
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`controls also control access to external memory, I/O's,
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`bus.
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`etc.
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`in
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`A substantial amount of on—chip RAM is provided”
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`which may be accessed by any of the processors. However,
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`each processor also has direct access to a primary
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`allocation of the on—chip RAM. All processors may
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`directly access their respective primary allocations of
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`RAM in parallel, but,
`to access other portions of RAM, a
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`processor must use the data bus, and therefore such
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`accesses must be arbitrated.
`Two design expedients
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`prevent hangups and deadlocks:
`first, 256 priority levels
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`are used coincidence of priority is thereby reduced.
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`SeCOnd, all interrupts are sent, and acknowledged,
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`parallel. Third, any processor which is unable to acquire-
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`all resources needed to proceed with execution releases
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`all previously acquired resources while it is waiting for
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`the necessary resources to become available.
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`In addition to these crucial elements, numerous
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`conventional elements are also used to fully implement the
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`For example, each processor includes an ALU, a
`design.
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`barrel shifter, a memory mapper, a microsequencer, etc.
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`The advantages of the present invention include all
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`objects of the invention discussed above, and others which
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`will be obvious to those skilled in the art. For example,
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`the hardware layout time of the RIC chip is reduced by a
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`factor of almost four, since much of the structure (e.g.,
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`all four processors)
`is replicated.
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`Of course,
`the processors need not be 16-bit
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`processors‘but may alternatively be 32-bit, 8—bit, etc.
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`the number of processors on a chip may not be
`INTEL-1006
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`Similarly,
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`35
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`\II
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`In;
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`"I
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`(I!
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`an
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`INTEL - 1006
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`9
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`exactly four, but may be three, or any number larger than
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`In fact,
`the maximum number of processors is
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`constrained simply by manufacturing technology, as smaller
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`geometries become practicable, it might be very desirable
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`to include large numbers of processors on a chip.
`In such
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`the interconnections, busses, and protocols would
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`remain the same. Of course, if the processors were other
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`than 16-bit,
`the width of the respective busses would have
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`to be changed correspondingly.
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`there is provided
`According to the present invention,
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`a restructurable integrated circuit, comprising a
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`monolithic substrate having: a plurality of processors; a
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`plurality of busses, each connected to all of said
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`processors; and means, connected to each of said
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`processors, for reconfiguring said processors selectively
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`so that said processors are operable in lockstep or
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`there is provided
`According to the present invention,
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`a restructurable integrated circuit, comprising a
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`monolithic substrate having: a plurality of processors; a
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`plurality of busses, each connected to all of said
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`processors; said busses comprising a status bus including
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`a plurality of lines said lines of said status bus
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`including synchronization and arithmetic linkage lines;
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`each said processor comprising a respective status bus
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`multiplexer connected to said respective processor and to
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`said status bus, said respective status bus multiplexer
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`selectively and programmably connecting or interrupting
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`selected lines of said status bus and selectively
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`connecting said respective processor to said status bus,
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`thereby selectively and programmably connecting said
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`respective processor through said status bus to adjacent
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`ones of said processors.
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`there is provided
`According to the present invention,
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`a restructurable integrated circuit, comprising a
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`monolithic substrate having: a plurality of processors; a
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`plurality of busses, each connected to all said
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`processors; each said processor comprising a dynamic logic
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`array (DLA) connected
`to receive commands
`provided to
`INTEL-1006
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`four.
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`case,
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`independently.
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`10
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`25
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`35
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`D)
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`INTEL - 1006
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`said respective processor said DLA comprising: an AND
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`matrix; an OR matrix;
`intermediate lines connecting said
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`AND matrix to said OR matrix; a plurality of input lines,
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`connected to a first one of the AND and OR matrices; and a
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`plurality of output lines connected to the other one of
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`said AND and OR matrices; at least one of said AND and OR
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`matrices of said DLA being arranged in rows and columns to
`define partitions within said respective matrix; each said
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`partition being selectively arranged to contain a selected
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`number of active elements disposed to implement a desired
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`logical function; and a plurality of control lines, each
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`said control line being connected to selectively enable or
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`disable said active devices in one or more of said
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`partitions, so that said DLA implements a selected logical
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`function in accordance with a state of said control lines;
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`whereby said DLA interprets commands provided to said
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`respective processor selectively in accordance with the
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`state of said control lines.
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`there is provided
`According to the present invention,
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`a restructurable integrated circuit, comprising a
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`monolithic substrate having: a plurality of processors; a
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`plurality of busses, each connected to all of said
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`processors; a RAM memory, said RAM memory comprising a»
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`plurality of RAM memory modules; said busses comprising a
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`data bus including a plurality of lines; and a plurality'
`of bus control units, each said bus control unit being
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`connected to one of said processors,
`to one of said RAM
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`memory modules, and to said data bus, said bus control
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`unit selectively connecting said processor to said data
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`bus or directly to said corresponding RAM memory module.7
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`According to the present invention,
`there is provided
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`a restructurable integrated circuit, comprising a
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`monolithic substrate having: a plurality of processors; a
`plurality of busses, each connected to all of said
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`processors; and means for reconfiguring each said
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`processor, so that each said processor selectively and
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`programmably is operated in lockstep with or independently
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`of one or more others of said processors on the samer
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`restructurable integrated circuit or on another similar
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`INTEL-1006
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`«I
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`(M
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`II!
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`I"
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`m
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`INTEL - 1006
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`0071727
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`restructurable integrated circuit.
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`there is provided
`According to the present invention,
`a restructurable integrated circuit, comprising a
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`monolithic substrate having: a plurality of processors; a
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`plurality of busses, each connected to all of said
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`processors; said busses comprising a control bus, said
`control bus comprising lines for transmitting commands,
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`and also lines for transmitting interrupt signals, each
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`said interrupt signal including bits indicating a priority
`and an interruptee processor among said processors,
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`wherein one of said interrupt signals initiates each
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`sequence of said commands; wherein each said processor
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`contains an interrupt manager, connected to said control
`to receive said interrupt signals, and wherein said:
`bus,
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`interrupt manager tests each successive one of said
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`interrupt signals to determine whether said respective
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`is
`processor which includes said interrupt manager
`designated by said successive interrupt signal as an
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`interruptee, wherein said interrupt manager stores the
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`priority of the one of said interrupt signals which
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`initiated whichever respective sequence of commands is
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`currently being executed by said processOr, and wherein
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`said interrupt manager compares the priority of each
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`successive one of said interrupt signals which is
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`addressed to said respective processor with the priority
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`of said respective interrupt signal which initiated
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`whichever respective sequence of commands is currently
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`being executed by said processor and provides a
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`corresponding context switch output; and wherein each said
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`respective processor also contains a scheduler, connected
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`to said context switch line of said interrupt manager,
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`said scheduler displacing a sequence of said commands
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`currently being executed by said corresponding processor
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`whenever said context switch line indicates that a newly
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`received interrupt signal includes a higher priority
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`a)
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`INTEL-1006
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`INTEL - 1006
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`0071727-
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`Brief Description of the Drawings
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`The present invention will now be described more
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`specifically with reference to the accompanying drawings
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`wherein:
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`the
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`a general overview of
`Figure l shows
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`restructurable IC according to the present invention;
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`Figure 2 shows a floor plan of a portion of the RIC,
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`including one processor in its entirety and one of each
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`kind of the external interfaces;
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`Figure 3 shows portions of the AND and OR portions of
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`a DLA, embodied in a NOR gate implementation;
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`Figure 4
`shows portions of the AND and OR matrixes
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`of a DLA embodied in a named gate implementation;
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`Figure 5 shows the structure of the control bus;
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`Figure 6 shows the relation between the central
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`control store controller and the four module controllers;
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`Figure 7 is a flowchart illustrating the operation of
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`the central control store controller and of the respective
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`module controller, where the control store is being
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`Figure 8 shows the connection of the daisy chained
`bus available line;
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`Figure 9 is a schematic diagram of major portions of
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`the ALU within each processor;
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`Figures 10 and ll respectively provide circuit
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`diagrams of portions of functional and carry chain blocks
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`within the ALU in each processor;
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`Figure 12 is a flow chart illustrating the structure
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`of the barrel shifter within each processor;
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`Figures 13, 14(a),
`l4(b) and l4(c) show examples of
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`shift and/or rotate operations performed by the barrel
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