Trials@uspto.gov
`571-272-7822
`
`Paper 72
`Date: April 9, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICROSOFT CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,1
`Patent Owner.
`
`IPR2018-016052
`Patent 7,620,800 B2
`
`
`
`
`
`
`
`
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`ARBES, Administrative Patent Judge.
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`1 Patent Owner filed updated mandatory notice information indicating that
`DirectStream, LLC (“DirectStream”) assigned the challenged patent to
`FG SRC LLC. Paper 69, 1. Accordingly, the caption for this proceeding
`has been changed.
`2 Cases IPR2018-01606 and IPR2018-01607 have been consolidated with
`this proceeding.
`
`
`
`
`571-272-7822
`
`Paper 72
`Date: April 9, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICROSOFT CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,1
`Patent Owner.
`
`IPR2018-016052
`Patent 7,620,800 B2
`
`
`
`
`
`
`
`
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`ARBES, Administrative Patent Judge.
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`1 Patent Owner filed updated mandatory notice information indicating that
`DirectStream, LLC (“DirectStream”) assigned the challenged patent to
`FG SRC LLC. Paper 69, 1. Accordingly, the caption for this proceeding
`has been changed.
`2 Cases IPR2018-01606 and IPR2018-01607 have been consolidated with
`this proceeding.
`
`
`
`
`
`IPR2018-01605
`Patent 7,620,800 B2
`
`INTRODUCTION
`I.
`A. Background and Summary
`Petitioner Microsoft Corporation filed three Petitions, collectively
`requesting inter partes review of claims 1–5, 7–9, 15, 17, 18, and 20–24
`of U.S. Patent No. 7,620,800 B2 (Ex. 1005, “the ’800 patent”) pursuant to
`35 U.S.C. § 311(a), as listed in the following chart.3
`Case Number
`Challenged Claims Petition
`
`IPR2018-01605 1, 8, 9, and 20
`
`Paper 1 (“Pet.”)
`
`IPR2018-01606 1, 7, 15, 17, and 24 Paper 1 (“-1606 Pet.”)
`
`IPR2018-01607 1–5, 18, and 21–23 Paper 1 (“-1607 Pet.”)
`
`On April 12, 2019, we instituted an inter partes review as to all challenged
`claims on all grounds of unpatentability asserted in the Petitions, and
`exercised our authority under 35 U.S.C. § 315(d) to consolidate the three
`proceedings and conduct the proceedings as one trial. Paper 21 (“Decision
`on Institution” or “Dec. on Inst.”). Patent Owner FG SRC LLC
`subsequently filed a Patent Owner Response (Paper 36, “PO Resp.”),
`Petitioner filed a Reply (Paper 49, “Reply”), and Patent Owner filed a
`Sur-Reply (Paper 59, “Sur-Reply”). Petitioner filed a Motion to Exclude
`(Paper 60, “Pet. Mot.”) certain evidence submitted by Patent Owner,
`to which Patent Owner filed an Opposition (Paper 63, “PO Opp.”) and
`Petitioner filed a Reply (Paper 66, “Pet. Mot. Reply”). Patent Owner filed a
`Motion to Exclude (Paper 61, “PO Mot.”) certain evidence submitted by
`Petitioner, to which Petitioner filed an Opposition (Paper 62, “Pet. Opp.”)
`
`
`3 Unless otherwise noted, references herein are to the exhibits filed in
`Case IPR2018-01605.
`
`2
`
`
`
`IPR2018-01605
`Patent 7,620,800 B2
`and Patent Owner filed a Reply (Paper 65, “PO Mot. Reply”). An oral
`hearing was held on February 4, 2020, and a transcript of the hearing is
`included in the record (Paper 71, “Tr.”).
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
`follow, we determine that Petitioner has shown by a preponderance of the
`evidence that claims 1–5, 7–9, 15, 17, 18, and 20–24 are unpatentable.
`
`
`B. Related Matters
`The parties indicate that the ’800 patent is the subject of the following
`district court cases: SRC Labs, LLC v. Microsoft Corp., No. 2:18-cv-00321
`(W.D. Wash.), and SRC Labs, LLC v. Amazon Web Servs., Inc.,
`No. 2:18-cv-00317 (W.D. Wash.). See Pet. 4–5; Paper 69, 1.
`
`
`C. The ’800 Patent
`The ’800 patent4 discloses “multi-adaptive processing systems and
`techniques for enhancing parallelism and performance of computational
`functions.” Ex. 1005, col. 1, ll. 40–43. Parallel processing “allows multiple
`processors to work simultaneously on the same problem to achieve a
`solution” in less time than it would take a single processor. Id. at col. 1,
`ll. 44–49. “[A]s more and more performance is required, so is more
`parallelism, resulting in ever larger systems” and associated difficulties,
`
`
`4 The ’800 patent is a continuation of U.S. Patent No. 7,225,324 B2
`(Ex. 1001, “the ’324 patent”), is challenged by Petitioner in
`Case IPR2018-01601. We enter a Final Written Decision in
`Case IPR2018-01601 concurrently with this Decision.
`
`3
`
`
`
`IPR2018-01605
`Patent 7,620,800 B2
`including “facility requirements, power, heat generation and reliability.”
`Id. at col. 1, ll. 53–61. The ’800 patent discloses that
`if a processor technology could be employed that offers orders
`of magnitude more parallelism per processor, these systems
`could be reduced in size by a comparable factor. Such a
`processor or processing element is possible through the use of a
`reconfigurable processor. Reconfigurable processors instantiate
`only the functional units needed to solve a particular application,
`and as a result, have available space to instantiate as many
`functional units as may be required to solve the problem up to
`the total capacity of the integrated circuit chips they employ.
`Id. at col. 1, l. 65–col. 2, l. 7. The ’800 patent describes a known issue
`where each processor in a multi-processor system is allocated a portion of a
`problem called a “cell” and “to solve the total problem, results of one
`processor are often required by many adjacent cells because their cells
`interact at the boundary.” Id. at col. 2, ll. 26–32. Passing intermediate
`results around the system to complete the problem requires using “numerous
`other chips and busses that run at much slower speeds than the
`microprocessor,” diminishing performance. Id. at col. 2, ll. 32–38, col. 5,
`ll. 16–28, Fig. 1 (depicting a conventional multi-processor arrangement).
`In an adaptive processor-based system, however, “any boundary data that is
`shared between . . . functional units need never leave a single integrated
`circuit chip,” reducing “data moving around the system” and improving
`performance. Id. at col. 2, ll. 39–49.
`
`
`
`4
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`IPR2018-01605
`Patent 7,620,800 B2
`Figure 2 of the ’800 patent is reproduced below.
`
`
`
`Figure 2 is “a functional block diagram of an adaptive processor 200
`communications path for implementing the technique of the present
`invention.” Id. at col. 5, ll. 29–32. Adaptive processor 200 includes
`adaptive processor chip 202, which is coupled to memory element 206,
`interconnect 208, and additional adaptive processor chips 210. Id. at col. 5,
`ll. 32–37. Adaptive processor chip 202 includes thousands of functional
`units (“FU”) 204 interconnected by “reconfigurable routing resources”
`inside adaptive processor chip 202, allowing functional units 204 to
`“exchange data at much higher data rates and lower latencies than a standard
`microprocessor.” Id. at col. 5, ll. 39–45.
`
`
`
`5
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`IPR2018-01605
`Patent 7,620,800 B2
`Figures 4A and 4B of the ’800 patent are reproduced below.
`
`
`
`Figure 4A depicts conventional sequential processing operation 400 where
`“nested Loops A (first loop 402) and B (second loop 404) are alternately
`active on different phases of the process.” Id. at col. 5, l. 65–col. 6, l. 2.
`Because first loop 402 must be completed before beginning second loop
`404, “all of the logic that has been instantiated is not being completely
`utilized.” Id. at col. 6, ll. 3–9. Figure 4B depicts “multi-dimensional
`process 410 in accordance with the technique of the present invention.” Id.
`at col. 6, ll. 11–14. “[M]ulti-dimensional process 410 is effectuated such
`that multiple dimensions of data are processed by both Loops A (first loop
`412) and B (second loop 414) such that the computing system logic is
`operative on every clock cycle.” Id. at col. 6, ll. 14–18. A “dimension” of
`data can be “multiple vectors of a problem, multiple plans of a problem,
`multiple time steps in a problem and so forth.” Id. at col. 6, ll. 25–28. The
`’800 patent discloses that available resources are utilized more effectively
`in the multi-dimensional process by “hav[ing] an application evaluate a
`problem in a data flow sense. That is, it will ‘pass’ a subsequent dimension
`
`6
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`IPR2018-01605
`Patent 7,620,800 B2
`of a given problem through the first loop 412 of logic concurrently with the
`previous dimension of data being processed through the second loop.” Id. at
`col. 6, ll. 19–25.
`The ’800 patent states that the disclosed process can be utilized for a
`variety of applications. Id. at col. 9, ll. 10–20. For example, seismic
`imaging applications, which “process echo data to produce detailed analysis
`of subsurface features” for oil and gas exploration, would “particularly
`benefit from the tight parallelism that can be found in the use of adaptive or
`reconfigurable processors” because they “use data collected at numerous
`points and consisting of many repeated parameters” and “the results of the
`computation on one data point are used in the computation of the next.” Id.
`at col. 9, ll. 25–34; see id. at col. 6, l. 30–col. 7, l. 37, Figs. 5A–5B, 6A–6B
`(describing a seismic imaging function that can be adapted to utilize the
`disclosed parallelism, where computational process 610 “loops over the
`depth slices as indicated by reference number 622 and loops over the shots
`as indicated by reference number 624”). Also, reservoir simulation
`applications, which “process fluid flow data in . . . oil and gas subsurface
`reservoirs to produce extraction models,” would benefit from the disclosed
`process because they define a three dimensional set of cells for the reservoir,
`utilize repeated operations on each cell, and “information computed for each
`cell is then passed to neighboring cells.” Id. at col. 9, l. 59–col. 10, l. 2; see
`id. at col. 7, l. 38–col. 8, l. 20, Figs. 7A–7D (describing “process 700 for
`performing a representative systolic wavefront operation in the form of a
`reservoir simulation function” in which “the computation of fluid flow
`properties are communicated to neighboring cells 710” without storing data
`in memory, “a set of cells can reside in an adaptive processor,” and “the
`pipeline of computation can extend across multiple adaptive processors,”
`
`7
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`IPR2018-01605
`Patent 7,620,800 B2
`where the process involves nested loops and systolic walls 712 and 714 of
`computation at different time sets), col. 8, l. 21–col. 9, l. 9, Figs. 8A–8C,
`9A–9C (describing two other processes for performing “a representative
`systolic wavefront operation”). Finally, the disclosed process may be used
`for genetic pattern matching applications, which “look[] for matches of a
`particular genetic sequence (or model) to a database of genetic records,”
`performing repeated operations to “compare[] each character in the model to
`the characters in [a particular] genetic record.” Id. at col. 11, ll. 42–52.
`
`
`D. Illustrative Claims
`Claim 1 of the ’800 patent is independent. Claims 2–5, 7–9, 15, 17,
`18, and 20–24 each depend from claim 1. Claims 1 and 15 recite:
`1. A method for data processing in a reconfigurable
`computing system,
`the reconfigurable computing system
`comprising at
`least one
`reconfigurable processor,
`the
`reconfigurable processor comprising a plurality of functional
`units, said method comprising:
`transforming an algorithm into a data driven calculation
`that is implemented by said reconfigurable computing system at
`the at least one reconfigurable processor;
`forming at least two of said functional units at the at least
`one reconfigurable processor to perform said calculation wherein
`only functional units needed to solve the calculation are formed
`and wherein each formed functional unit at the at least one
`reconfigurable processor interconnects with each other formed
`functional unit at the at least one reconfigurable processor based
`on reconfigurable routing resources within the at least one
`reconfigurable processor as established at formation, and
`wherein lines of code of said calculation are formed as clusters
`of functional units within the at least one reconfigurable
`processor;
`
`8
`
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`
`IPR2018-01605
`Patent 7,620,800 B2
`utilizing a first of said formed functional units to operate
`upon a subsequent data dimension of said calculation forming a
`first computational loop; and
`substantially concurrently utilizing a second of said
`formed functional units to operate upon a previous data
`dimension of said calculation generating a second computational
`loop wherein said implementation of said calculation enables
`said first computational loop and said second computational loop
`execute concurrently and pass computed data seamlessly
`between said computational loops.
`15. The method of claim 1 wherein instantiating includes
`establishing a stream communication connection between
`functional units.
`
`
`
`E. Evidence
`The pending grounds of unpatentability in the instant inter partes
`review are based on the following prior art:
`Jean-Luc Gaudiot, “Data-Driven Multicomputers in Digital
`Signal Processing,” Proceedings of the IEEE, Special Issue on
`Hardware and Software for Digital Signal Processing, vol. 75,
`no. 9, Sept. 1987, pp. 1220–1234 (Ex. 1010, “Gaudiot”);
`Duncan A. Buell, Jeffrey M. Arnold, & Walter J. Kleinfelder,
`SPLASH2: FPGAS IN A CUSTOM COMPUTING MACHINE (1996)
`(Ex. 1007, “Splash2”);
`Carl Ebeling et al., “Mapping Applications to the RaPiD
`Configurable Architecture,” Proceedings of
`the
`IEEE
`Symposium on FPGAs for Custom Computing Machines,
`Apr. 16–18, 1997, pp. 106–115 (Ex. 1009, “RaPiD”);
`Michael Rencher & Brad L. Hutchings, “Automated Target
`Recognition on SPLASH 2,” Proceedings of
`the IEEE
`Symposium on FPGAs for Custom Computing Machines,
`Apr. 16–18, 1997, pp. 192–200 (Ex. 1011, “Chunky SLD”);
`Yong-Jin Jeong & Wayne P. Burleson, “VLSI Array Algorithms
`and Architectures for RSA Modular Multiplication,” IEEE
`
`9
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`IPR2018-01605
`Patent 7,620,800 B2
`Transactions on Very Large Scale Integration (VLSI) Systems,
`vol. 5, no. 2, June 1997, pp. 211–217 (Ex. 1061, “Jeong”); and
`D. Roccatano et al., “Development of a Parallel Molecular
`Dynamics Code on SIMD Computers: Algorithm for Use of Pair
`List Criterion,” Journal of Computational Chemistry, vol. 19,
`no. 7, May 1998, pp. 685–694 (Ex. 1012, “Roccatano”).5
`Petitioner filed a declaration from Harold Stone, Ph.D. (Ex. 1003) with its
`Petition and a reply declaration from Dr. Stone (Ex. 1076) with its Reply.
`Patent Owner filed declarations from Jon Huppenthal (Ex. 2101), Houman
`Homayoun, Ph.D. (Exs. 2029, 2112), and Tarek El-Ghazawi, Ph.D.
`(Ex. 2166).
`
`
`F. Asserted Grounds
`The instant inter partes review involves the following grounds of
`unpatentability:
`Petition(s)
`
`35 U.S.C. § Reference(s)/Basis
`
`102(a),
`102(b)6
`
`Splash2
`
`103(a)
`
`Splash2
`
`Claim(s)
`Challenged
`1, 15, 18, 21,
`22
`
`1, 15, 18, 21,
`22
`
`IPR2018-01605,
`IPR2018-01606,
`IPR2018-01607
`IPR2018-01605,
`IPR2018-01606,
`IPR2018-01607
`
`
`5 When citing the prior art references and other exhibits, we refer to the page
`numbers in the bottom-right corner added by the filing party. See 37 C.F.R.
`§ 42.63(d)(2).
`6 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the
`challenged claims of the ’800 patent have an effective filing date before the
`effective date of the applicable AIA amendments, we refer to the pre-AIA
`versions of 35 U.S.C. §§ 102 and 103.
`
`10
`
`
`
`Claim(s)
`Challenged
`1, 15, 18, 21,
`22
`
`35 U.S.C. § Reference(s)/Basis
`
`103(a)
`
`Splash2, Gaudiot
`
`IPR2018-01605
`Patent 7,620,800 B2
`Petition(s)
`
`IPR2018-01605,
`IPR2018-01606,
`IPR2018-01607
`IPR2018-01605
`
`IPR2018-01605
`
`IPR2018-01605
`
`IPR2018-01605
`
`8, 9
`
`8, 9
`
`20
`
`20
`
`103(a)
`
`103(a)
`
`103(a)
`
`103(a)
`
`103(a)
`
`103(a)
`
`103(a)
`
`103(a)
`
`Splash2, RaPiD
`
`Splash2, RaPiD,
`Gaudiot
`Splash2, Jeong
`
`Splash2, Jeong,
`Gaudiot
`Splash2, Chunky
`SLD
`Splash2, Chunky
`SLD, Gaudiot
`Splash2, Roccatano
`
`Splash2, Roccatano,
`Gaudiot
`
`IPR2018-01606
`
`7, 17, 24
`
`IPR2018-01606
`
`7, 17, 24
`
`IPR2018-01607
`
`2–5, 22, 23
`
`IPR2018-01607
`
`2–5, 22, 23
`
`
`
`II. ANALYSIS
`A. Motions to Exclude
`The party moving to exclude evidence bears the burden of proof to
`establish that it is entitled to the relief requested—namely, that the material
`sought to be excluded is inadmissible under the Federal Rules of Evidence.
`See 37 C.F.R. §§ 42.20(c), 42.62(a). For the reasons discussed below,
`Petitioner’s Motion is granted-in-part, denied-in-part, and dismissed-in-part,
`and Patent Owner’s Motion is denied-in-part and dismissed-in-part.
`
`
`11
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`IPR2018-01605
`Patent 7,620,800 B2
`
`1. Petitioner’s Motion to Exclude
`Exhibits 2101, 2065, 2075, and 2091: Petitioner moves to exclude the
`entirety of the declaration (Ex. 2101) of Mr. Huppenthal, one of the named
`inventors of the ’800 patent, “as not being relevant to any issue on which
`trial has been instituted, and for lacking foundation, containing hearsay,
`and/or causing undue prejudice.” Pet. Mot. 3–6. Petitioner argues that the
`declaration includes “irrelevant narrative discussion of [Mr. Huppenthal’s]
`participation in reconfigurable computing” and statements “either based on
`hearsay or lack of personal knowledge.” Id. at 3–4. Petitioner also moves to
`exclude paragraphs 80 and 82–86 of the declaration based on
`Mr. Huppenthal’s alleged “refusal to answer questions concerning those
`portions of the declaration” during cross-examination. Id. at 1–3.
`Petitioner also moves to exclude three transcripts (Exs. 2065, 2075,
`2091) of depositions of Petitioner’s declarants from other inter partes
`reviews as “not being relevant to any issue on which trial has been instituted,
`for containing hearsay, and/or causing undue prejudice.” Id. at 6–7.
`Petitioner argues that allowing the transcripts in the record would be “highly
`prejudicial as they present themselves with the indicia of expert testimony
`while being totally devoid from the necessary context of the matters from
`which they originate.” Id. Patent Owner cites Exhibits 2065 and 2075 in its
`Response, but does not cite Exhibit 2091 in its Response or Sur-Reply.
`Petitioner’s Motion is dismissed as moot, as we do not rely on the
`cited portions of the testimony in a manner adverse to Petitioner in this
`Decision. As explained below, even if the testimony is considered, we are
`not persuaded by Patent Owner’s arguments regarding the state of the art or
`alleged nonobviousness of the challenged claims, and Patent Owner has not
`
`12
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`IPR2018-01605
`Patent 7,620,800 B2
`shown proof of secondary considerations that would support a conclusion of
`nonobviousness. See infra Sections II.E–II.J.
`Exhibit 2112: Petitioner moves to exclude paragraphs 41, 145, 180,
`181, and 247 of the declaration of Dr. Homayoun, which refer to Exhibits
`2066 and 2101. Pet. Mot. 8–9. Because we do not exclude those exhibits,
`we also dismiss as moot Petitioner’s Motion with respect to Exhibit 2112.
`Exhibits 2066–2074, 2076, 2078–2099, 2102–2104, 2106, 2107, 2110,
`2113–2134, 2140–2152, 2156, 2163, 2165, and 2170: Petitioner moves to
`exclude a number of exhibits as “not being relevant to any issues on which
`trial has been instituted, lacking foundation, and/or causing undue prejudice”
`because the exhibits were not discussed or cited, or “only cited
`superficially,” in Patent Owner’s Response and Sur-Reply. Pet. Mot. 7–8.
`Petitioner’s Motion is dismissed as moot, as we do not rely on the exhibits in
`a manner adverse to Petitioner in this Decision. We note, however, that in
`evaluating Petitioner’s asserted grounds of unpatentability, we only consider
`substantive arguments made by the parties in their papers during trial (i.e.,
`the Petitions, Response, Reply, and Sur-Reply). To the extent a document is
`filed in the record but never discussed in a paper, there is no substantive
`argument pertaining to that document that can be considered.
`Exhibit 2170: Petitioner moves to exclude Exhibit 2170 under
`Federal Rules of Evidence 401–403 as cumulative of Exhibit 1007.
`Pet. Mot. 8. Both exhibits are copies of Splash2. Dr. El-Ghazawi refers to
`the document in his declaration with the numeral “1007.” Ex. 2166 ¶ 40.
`To ensure a clear record, we grant Petitioner’s Motion, expunge Exhibit
`2170, and refer herein to Exhibit 1007. See 37 C.F.R. §§ 42.7(a), 42.6(d)
`(“A document already in the record of the proceeding must not be filed
`
`13
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`IPR2018-01605
`Patent 7,620,800 B2
`again, not even as an exhibit or an appendix, without express Board
`authorization.”).
`Portions of Patent Owner’s Response: Petitioner moves to exclude
`portions of Patent Owner’s Response referring to the exhibits that Petitioner
`seeks to exclude. Pet. Mot. 9. Patent Owner’s Response is a paper with
`attorney arguments, not evidence that may be excluded.7 Further, we do not
`exclude any of the exhibits referred to in the identified portions of the
`Response. Petitioner’s Motion is denied as to Patent Owner’s Response.
`
`
`2. Patent Owner’s Motion to Exclude
`Exhibits 1074, 1077, and 1079: Patent Owner moves to exclude three
`technical documents filed by Petitioner with its Reply.
`First, Patent Owner moves to exclude Exhibits 1074 and 1079 as
`unauthenticated under Federal Rule of Evidence 901. PO Mot. 6–7.
`“To satisfy the requirement of authenticating or identifying an item of
`evidence, the proponent must produce evidence sufficient to support a
`finding that the item is what the proponent claims it is.” Fed. R. Evid.
`901(a). Certain evidence, though, is “self-authenticating” and “require[s] no
`extrinsic evidence of authenticity in order to be admitted.” Fed. R. Evid.
`902. Exhibit 1074 is an article by Maya Gokhale and Ron Minnich titled
`“FPGA Computing in a Data Parallel C,” and includes an IEEE trade
`inscription, copyright symbol, and International Standard Book Number
`(ISBN) on the first page (“0-8186-3890-7/93 $03.00 © 1993 IEEE”). It is
`
`
`7 Petitioner did not seek authorization to file a motion to strike Patent
`Owner’s Response. See Patent Trial and Appeal Board Consolidated Trial
`Practice Guide (Nov. 2019), 80–81, available at https://www.uspto.gov/
`TrialPracticeGuideConsolidated (“Trial Practice Guide”).
`
`14
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`IPR2018-01605
`Patent 7,620,800 B2
`self-authenticating under at least Federal Rule of Evidence 902(6) (“Printed
`material purporting to be a . . . periodical.”) and 902(7) (“An inscription,
`sign, tag, or label purporting to have been affixed in the course of business
`and indicating origin, ownership, or control.”). Exhibit 1079 is an excerpt
`from a book by Kevin Skahill titled “VHDL for Programmable Logic.”
`It includes a copyright notice (“Copyright © 1996 by Addison-Wesley
`Publishing, Inc.”), Library of Congress catalogue information, and
`hand-written library catalogue information. Ex. 1079, Cover 3, v. Petitioner
`points out where the book is available from “several well-known book
`sellers.” Pet. Opp. 4 & n.2. It is authenticated at least as an ancient
`document under Federal Rule of Evidence 901(b)(8) because it “is in a
`condition that creates no suspicion about its authenticity,” “was in a place
`where, if authentic, it would likely be,” and “is at least 20 years old when
`offered.” Nothing about either exhibit suggests that it is not what it points to
`be, and Patent Owner does not point to anything in particular in the exhibits
`that would indicate otherwise. See PO Mot. 6–7; PO Mot. Reply 1–4.
`Second, Patent Owner moves to exclude Exhibits 1074, 1077, and
`1079 as containing inadmissible hearsay under Federal Rule of Evidence
`802. PO Mot. 7. Patent Owner states that Petitioner in its Reply “cites each
`of these documents to prove the truth of technical matters allegedly asserted
`in such documents, i.e. to support Petitioner’s specific factual assertions
`regarding a technical issue.” Id. We are not persuaded. Patent Owner does
`not identify any particular “statement” in any of the exhibits that is being
`offered “to prove the truth of the matter asserted in the statement,” and thus
`fails to meet its burden to prove inadmissibility as hearsay. See Fed. R.
`Evid. 801(c); 37 C.F.R. § 42.20(c). Even if Patent Owner had done so,
`Petitioner cites the exhibits to show what a person of ordinary skill in the art
`
`15
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`IPR2018-01605
`Patent 7,620,800 B2
`would have known at the time of the ’800 patent and, with respect to Exhibit
`1074 in particular, how a person of ordinary skill in the art would have
`understood another reference relied on by Patent Owner that cites the article.
`See Reply 7, 17, 33; Pet. Opp. 5–6; Ex. 2169, 37–38, 208. The exhibits are
`not being offered for the truth of any particular matter discussed in the
`references. Finally, Exhibits 1074 and 1079 also are admissible under
`Federal Rule of Evidence 803(16), which provides as an exception to the
`hearsay rule “[a] statement in a document that was prepared before January
`1, 1998, and whose authenticity is established.” See 1074, 94 (“1993” date);
`Ex. 1079, Cover 3, v (“1996” date).
`Third, Patent Owner moves to exclude Exhibit 1077 as “irrelevant to
`the patent and claim construction issues in dispute.” PO Mot. 7–8. Exhibit
`1077 is an excerpt of certain pages of the Microsoft Computer Dictionary
`(5th ed. 2002). Patent Owner argues that Exhibit 1077 “is extrinsic evidence
`pertaining to Petitioner’s proffered definitions from the Microsoft Computer
`Dictionary of ‘data structure’ and ‘data path,’ neither of which are claim
`terms in the patent.” PO Mot. 7. Federal Rule of Evidence 401 provides
`that “[e]vidence is relevant if: (a) it has any tendency to make a fact more or
`less probable than it would be without the evidence; and (b) the fact is of
`consequence in determining the action.”
`Petitioner submits Exhibit 1077 in support of its arguments regarding
`the interpretation of disputed claim language, specifically the term “stream
`communication.” Reply 29. The meaning of this phrase is “of consequence
`in determining” whether challenged claim 15 is unpatentable over the
`asserted prior art, and Exhibit 1077 provides insight as to the meaning of
`words used in both parties’ proposed interpretations. See infra Section
`II.C.4. Exhibit 1077 has some “tendency to make a fact more or less
`
`16
`
`
`
`IPR2018-01605
`Patent 7,620,800 B2
`probable than it would be without the evidence” and is relevant under
`Federal Rule of Evidence 401. Thus, there is no basis to exclude Exhibit
`1077. We also note that Patent Owner appears to have filed a full copy of
`the dictionary as Exhibit 2065, and the same pages filed as Exhibit 1077
`(pages 144–145) that Patent Owner seeks to exclude are in the exhibit that
`Patent Owner filed. Further, the record contains numerous other dictionary
`references filed by both parties, including Exhibits 1025, 1059, 2024–2026,
`and 2038. Patent Owner’s Motion is denied as to Exhibits 1074, 1077, and
`1079.
`
`Exhibit 1076: Patent Owner also moves to exclude paragraphs 15–17
`of the reply declaration of Dr. Stone, which refer to Exhibit 1074 “for the
`first time,” under Federal Rules of Evidence 402 and 403. PO Mot. 8.
`Because we find no basis to exclude Exhibit 1074, we also deny Patent
`Owner’s Motion with respect to Exhibit 1076. To the extent Patent Owner’s
`position is that Petitioner’s Reply and Dr. Stone’s reply declaration exceed
`the proper scope of a reply, we address those arguments below. See infra
`Section II.E.2.a.2; Trial Practice Guide, 79 (“A motion to exclude is not a
`vehicle for addressing the weight to be given evidence—arguments
`regarding weight should appear only in the merits documents. Nor should a
`motion to exclude address arguments or evidence that a party believes
`exceeds the proper scope of reply or sur-reply.”).
`Exhibits 1075 and 1078: Patent Owner moves to exclude certain
`portions of the transcript of the deposition of Dr. Homayoun because the
`questions asked were “vague, ambiguous, call[] for a legal conclusion, and
`misleading.” PO Mot. 9–11 (citing Ex. 1075, 27:4–12, 65:5–17). Patent
`Owner also moves to exclude a portion of the transcript of the deposition of
`Dr. El-Ghazawi because the question asked was “vague, ambiguous, and
`
`17
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`
`
`IPR2018-01605
`Patent 7,620,800 B2
`calls for a speculative answer.” Id. at 11 (citing Ex. 1078, 65:12–17). Patent
`Owner’s Motion is dismissed as moot, as we do not rely on the disputed
`portions of the testimony in rendering our Decision.
`
`
`B. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art for a challenged
`patent, we look to “1) the types of problems encountered in the art; 2) the
`prior art solutions to those problems; 3) the rapidity with which innovations
`are made; 4) the sophistication of the technology; and 5) the educational
`level of active workers in the field.” Ruiz v. A.B. Chance Co., 234 F.3d 654,
`666–667 (Fed. Cir. 2000). “Not all such factors may be present in every
`case, and one or more of them may predominate.” Id.
`Petitioner’s declarant, Dr. Stone, testifies that a person of ordinary
`skill in the art at the time of the ’800 patent would have had “an advanced
`degree in electrical or computer engineering, or computer science with
`substantial study in computer architecture, hardware design, and computer
`algorithms,” and “at least three years’ experience working in the field,” or
`alternatively “a bachelor’s degree covering those disciplines and at least four
`years working [in] the field.” Ex. 1003 ¶ 45. According to Dr. Stone,
`[s]uch a person would also have been knowledgeable about the
`programming, design and operation of computer systems based
`on
`reconfigurable components
`such as FPGAs
`(field
`programmable gate arrays) and CPLDs (complex programmable
`logic devices), including computer systems for performing
`systolic and data driven calculations. That person would also
`have been familiar with hardware description languages such as
`[Very High Speed Integrated Circuit Hardware Description
`Language (VHDL)] that could be used to configure FPGAs and
`CPLDS that serve as components of reconfigurable computer
`systems. Finally, as demonstrated by many of the references
`
`18
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`
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`IPR2018-01605
`Patent 7,620,800 B2
`discussed [in Dr. Stone’s declaration], such a person would also
`have been familiar with various other areas of technology that by
`2002 had relied on high performance and parallel computing
`systems, such as genetic sequence comparisons,
`image
`processing, data mining, and processing related to proteins and
`organic structures.
`
`Id.
`
`Patent Owner states that it “does not dispute the level of education and
`skill promoted by [Dr. Stone],” and Patent Owner’s declarant,
`Dr. Homayoun, “agree[d] with Dr. Stone’s assessment of the level of
`ordinary skill in the art,” noting that such an individual also would have
`been “experienced in developing with high-level languages (C and Fortran),
`hardware description languages, and the unique problems involved with
`programming FPGAs and FPGA based systems.” See PO Resp. 29;
`Ex. 2029 ¶ 17; see also Ex. 2112 ¶ 133 (“In general, I would agree to the
`level of education and skill promoted by [Petitioner’s] expert [for the
`’800 patent].”). Dr. Homayoun further expands on his understanding of
`what a person of ordinary skill in the art at the time of the ’800 patent would
`have known and considered. Ex. 2112 ¶¶ 133–146. For example,
`Dr. Homayoun testifies that in addition to the technical background set forth
`in Dr. Stone’s definition, a person of ordinary skill in the art would have
`“considered all of the state of the art [described in Dr. Homayoun’s
`declaration] in the design of computer architecture, . . . [i]ncluding the issues
`of reconfigurable programming, processor speed, FPGA speed, and
`cost/benefit analysis of overhead introduction as applied to [high
`performance computing (HPC)] applications.” Id. ¶ 133. Also, according to
`Dr. Homayoun, an ordinarily skilled artisan would have “consider[ed] the
`technical problems [the ’800 patent was] attempting to solve” without using
`
`19
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`IPR2018-01605
`Patent 7,620,800 B2
`the patent “as a technical road-map to then conflate the technical problem
`with the solution,” and “would have considered the drawbacks in HPC
`computing and the deficiencies in FPGA systems and computer architecture
`design considerations at the time of the disclosed inventions.” Id. ¶ 140.
`Patent Owner similarly argues in its Response that a person of ordinary skill
`in the art would have “considered” all of these issues. PO Resp. 18–30.
`We have ev
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