Trials@uspto.gov
`571-272-7822
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`Paper 19
`Date: October 29, 2019
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS AMERICA, INC. and
`ASUS COMPUTER INTERNATIONAL, INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner
`____________
`
`Case IPR2017-020211
`Patent 6,243,315 B1
`____________
`
`
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`JUDGMENT
`Final Written Decision
`Determining Some Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`
`1 Case IPR2018-00047, filed by ASUS Computer International, Inc.
`(“ASUS”), has been joined with this proceeding.
`
`
`
`
`571-272-7822
`
`
`
`
`
`
`
`Paper 19
`Date: October 29, 2019
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS AMERICA, INC. and
`ASUS COMPUTER INTERNATIONAL, INC.,
`Petitioner,
`
`v.
`
`JAMES B. GOODMAN,
`Patent Owner
`____________
`
`Case IPR2017-020211
`Patent 6,243,315 B1
`____________
`
`
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`
`JUDGMENT
`Final Written Decision
`Determining Some Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`
`1 Case IPR2018-00047, filed by ASUS Computer International, Inc.
`(“ASUS”), has been joined with this proceeding.
`
`
`
`
`
`IPR2017-02021
`Patent 6,243,315 B1
`
` I. INTRODUCTION
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`Samsung Electronics America, Inc. and ASUS Computer International, Inc.
`(collectively “Petitioner”) challenge the patentability of claims 1–20 (“the
`challenged claims”) of U.S. Patent No. 6,243,315 B1 (Ex. 1001, “the
`’315 patent”2), owned by James B. Goodman (“Patent Owner”).
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision, issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73,
`addresses issues and arguments raised during trial. For the reasons
`discussed below, we determine that Petitioner has shown by a preponderance
`of the evidence that claims 1, 5, 10, and 16 of the ’315 patent are
`unpatentable but has not shown by a preponderance of the evidence that
`claims 2–4, 6–9, 11–15, and 17–20 are unpatentable.
`
`A. Procedural History
`
`On August 29, 2017, Samsung Electronics America, Inc. filed a
`Petition requesting an inter partes review of claims 1–20 of the ’315 patent.
`Paper 2 (“Pet.”). The Petition is supported by the declaration testimony of
`Dr. Andrew Wolfe. Ex. 1002. Patent Owner filed a Preliminary Response.
`Paper 6 (“Prelim. Resp.”).
`On October 12, 2017, ASUS Computer International, Inc. (“ASUS”)
`filed a Petition requesting inter partes review of claims 1–20 of the ’315
`patent on the same grounds and arguments presented in Case IPR2017-
`02021 and requested joinder with Case IPR2017-02021. See Case IPR2018-
`00047, Papers 2, 3. Patent Owner filed a Preliminary Response. Case
`IPR2018-00047, Paper 7.
`
`
`2 Citations are to IPR2017-02021 unless otherwise indicated.
`
`2
`
`
`
`IPR2017-02021
`Patent 6,243,315 B1
`On March 9, 2018, we instituted an inter partes review of the
`challenged claims in IPR2017-02021. Paper 7 (“Decision on Institution” or
`“Dec. on Inst.”). On March 20, 2018, we granted ASUS’s request for inter
`partes review and for joinder of the IPR2018-00047 proceeding with
`IPR2017-02021. IPR2018-00047, Paper 9. On June 1, 2018, Patent Owner
`filed a Patent Owner Response. Paper 10. On August 24, 2018, Petitioner
`filed a Reply. Paper 11 (“Reply”).
`A hearing was held on November 16, 2018. A transcript of the
`hearing has been entered into the record. Paper 18 (“Tr.”).
`
`B. Related Proceedings
`
`Petitioner identifies the following litigations as related proceedings:
`Goodman v. Samsung Electronics America, Inc., Case No. 1:17-cv-05539
`(S.D.N.Y.); Goodman v. Hewlett-Packard Co., Case No. 4:16-cv-03195
`(S.D. Tex.); Goodman v. ASUS Computer Int’l, Inc., Case No. 4:16-cv-
`03232 (S.D. Tex.). Pet. 2.
`Patent Owner further identifies the following litigations as related
`proceedings: Goodman v. ASUS Computer Int’l, Case No. 17-cv-05542
`(N.D. Cal.) (transferred from the S.D. Tex.); Goodman v. Lenovo (United
`States) Inc., Case No. 17-cv-06782; and Goodman v. Acer American Corp.,
`Case No. 17-cv-07297. See Prelim. Resp. 2; IPR2018-00047, Prelim.
`Resp. 3.
`We also note that the ’315 patent was the subject of a Final Written
`Decision in HP Inc. v. Goodman (Case IPR2017-01994) in which we
`determined claims 1 and 5 were not shown to be unpatentable but that claims
`10 and 16 were shown to be unpatentable. IPR2017-01994, Paper 16. The
`’315 patent was also the subject of a petition for inter partes review in
`
`3
`
`
`
`IPR2017-02021
`Patent 6,243,315 B1
`SMART Modular Technologies, Inc. v. Goodman, Case IPR2015-01675, in
`which the Board instituted inter partes review and subsequently granted the
`parties’ joint motion to terminate. See IPR2015-01675, Paper 20.
`
`C. The ’315 patent
`
`The ’315 patent is directed to memory systems having volatile solid
`state memory devices that retain information when an electrical power
`source is applied but lose their memory contents when power is removed.
`Ex. 1001, 2:54–58, 3:46–52. To reduce energy consumption and preserve
`memory contents, volatile memory devices are placed in low power “self-
`refresh mode” when the memory system is not receiving requests for access.
`See id. at 3:46–54 (stating the “low power mode utilizes significantly less
`electrical current than when the memory device is in the operating mode or
`powered up mode”), 3:25–30 (stating “placing the memory devices into a
`power down self-refresh mode . . . will maintain the data using a minimum
`of electrical power”). The memory system of the ’315 patent has a control
`device interposed electrically between the memory devices and a central
`processing unit (“CPU”). Id. at 3:54–56. The control device senses CPU
`access of the memory devices and conditions the memory devices to an
`operating mode condition prior to allowing access to the information
`contained therein. Id. at 3:56–59. The control device also places the solid
`state memory devices into a low power standby mode when it “senses the
`termination of a memory cycle.” Id. at 3:59–62.
`Figure 1 of the ’315 patent, reproduced below, illustrates a preferred
`embodiment in which address and control busses are electrically isolated
`from the memory devices when the memory devices are in a power down
`self refresh mode. Id. at 5:60–63.
`
`4
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`IPR2017-02021
`Patent 6,243,315 B1
`
`
`As shown in Figure 1 of the ’315 patent above, control device 15 is
`interdisposed between address buss 17 and address buss 20 (id. at 5:50–52)
`as well as in between control buss 22 and control buss 24 (id. at 5:54–56).
`Control devices 15 isolates address buss 17 and control buss 22 from
`memory devices 5 when the memory devices are in a power down self
`refresh mode. Id. at 5:60–63. By isolating the memory devices from control
`buss 22 and address buss 17, control device 15 prevents errant signals from
`erroneously changing or affecting the data being retained by memory
`devices 5. Id. at 5:63–67.
`Figure 1 also shows row address select (“RAS”) control lines 26 and
`write enable (“WE”) control lines 28, which are connected to memory
`access enable control device 30. Id. at 6:1–3. Memory access enable
`control device 30 receives signals from the CPU indicating that a memory
`
`5
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`IPR2017-02021
`Patent 6,243,315 B1
`access is pending. Id. at 6:3–5. Memory access enable control device 30
`then signals control device 15 to bring memory devices 5 up to a normal
`operating mode. Id. at 5:56–59, 6:5–8. Memory access enable control
`device 30 can also signal control device 15 to indicate when memory
`devices 5 are to be placed in a power down mode. Id. at 5:56–59.
`Another preferred embodiment of the ’315 patent is shown in the
`block diagram of Figure 4, reproduced below. Id. at 4:41–42.
`
`
`Figure 4 of the ’315 patent, shown above, is a block diagram of a
`preferred embodiment of the invention that switches the voltage source from
`the system electrical source input on line 140 to battery 146 when the input
`voltage level is less than a fixed amount and electrically isolates address and
`control lines. Id. at 9:41–46. As shown in Figure 4, control device 115 is
`interdisposed between address buss 117 and address bus 120 (id. at 9:16–20)
`and between control buss 122 and control buss 124 (id. at 9:20–23).
`
`6
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`IPR2017-02021
`Patent 6,243,315 B1
`Figure 4 “also shows RAS, row address select lines, 126 and WE,
`write enable, 128 control lines connected to” control device 115. Id. at
`9:24–26. The “system input electrical power source line 140 and control
`lines 122 and address lines 117 are inputs into control device 115.” Id. at
`9:31–33. The outputs from control device 115 are address lines 120 control
`lines 124 and voltage line 143. Id. at 9:33–34. Voltage line 143 supplies
`power at a predetermined voltage level to the memory devices. Id. at 9:36–
`37.
`
`Control device 115 compares the input voltage on line 140 against a
`fixed reference voltage; when the input voltage level is less than the fixed
`reference voltage, the output electrical voltages source is switched from the
`system electrical source input on line 140 to battery 146. Id. at 9:41–43.
`Control device 115 then electrically isolates the “memory devices 105 from
`. . . control lines 122 and address lines 177” to prevent errant signals. Id. at
`9:43–47.
`
`D. Illustrative Claims
`
`Of the claims challenged by Petitioner, only claims 1 and 10 are
`
`independent and are reproduced below.3
`1. A memory system for use in a computer system, said
`memory system comprising:
`[a] a plurality of volatile solid state memory devices that
`retain information when an electrical power source is
`applied
`to
`said memory devices within a
`predetermined voltage range and capable of being
`placed in a self refresh mode; said memory devices
`having address lines and control lines;
`
`
`3 Paragraph breaks and bracketed letters have been added for ease of
`reference and for consistency with nomenclature utilized by Petitioner.
`
`7
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`IPR2017-02021
`Patent 6,243,315 B1
`[b] a control device for selectively electrically isolating
`said memory devices from respective address lines
`and respective control lines so that when said memory
`devices are electrically isolated, any signals received
`on said respective address lines and respective control
`lines do not reach said memory devices; and
`[c] a memory access enable control device coupled to said
`control device and to said control lines for determining
`when said memory system is not being accessed and
`for initiating a low power mode for said memory
`system wherein said control device electrically
`isolates said memory devices and places said memory
`devices in said self refresh mode, thereby reducing the
`amount of electrical energy being drawn from an
`electrical power supply for said computer system.
`Id. at 13:18–40.
`10. A memory system for use in a computer system, said
`memory system comprising:
`[a] a plurality of volatile solid state memory devices that
`retain information when an electrical power source
`having a voltage greater than a predetermined voltage
`is applied to said devices; said memory devices having
`address lines and control lines;
`[b] said computer system including a first electrical power
`source for operating said computer and being capable
`of producing a first voltage applied to said memory
`devices;
`[c] a control device for monitoring said first voltage to
`determine when said first voltage is less than said
`predetermined voltage and for selectively electrically
`isolating said memory devices from respective address
`lines and respective control lines so that when said
`memory devices are electrically isolated, any signals
`received on said respective address
`lines and
`respective control lines do not reach said memory
`devices; and
`[d] a second electrical power source operable for
`
`8
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`IPR2017-02021
`Patent 6,243,315 B1
`supplying a second voltage to said memory devices
`greater than said predetermined voltage;
`[e] said control device being operable for disconnecting
`said first electrical power source from said memory
`devices and connecting said second electrical power
`source to said memory devices when said first voltage
`is less than said predetermined voltage;
`[f] whereby, data in said memory devices is preserved by
`said second electrical power source when said first
`electrical power source fails to maintain at least said
`predetermined voltage on said memory devices, and
`said memory devices are isolated from errant signals.
`Id. at 13:65–14:32.
`
`E. Prior Art and Asserted Grounds
`
`Petitioner asserts that claims 1–20 are unpatentable on the following
`
`grounds:
`
`Claims Challenged
`1, 5
`10, 16
`2–4, 6–9
`11–15, 17–20
`1, 5
`10, 16
`
`35 U.S.C. §
`§ 102(e)
`§ 103
`§ 103
`§ 103
`§ 103
`§ 103
`
`Basis
`
`Dell4
`Dell and Abe5
`Dell and JESD21-C6
`Dell, Abe, and JESD21-C
`Ooishi7 and Palaniswami8
`Ooishi, Palaniswami, and Abe
`
`
`
`
`4 U.S. Patent No. 6,327,664 (filed April 30, 1999, issued Dec. 4, 2001)
`(Ex. 1004, “Dell”)
`5 U.S. Patent No. 5,590,082 (issued Dec. 31, 1996) (Ex. 1005, “Abe”)
`6 JEDEC STANDARD No. 21-C, Release 7, Configurations for Solid State
`Memories, Electronics Indus. Assoc. Jan. 1997 (Ex. 1006, “JESD21-C”).
`7 U.S. Patent No. 6,172,928 (issued Jan. 9, 2001) (Ex. 1008, “Ooishi”).
`8 U.S. Patent No. 6,144,219 (issued Nov. 7, 2000) (Ex. 1009,
`“Palaniswami”).
`
`9
`
`
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`IPR2017-02021
`Patent 6,243,315 B1
`
`II. DISCUSSION
`A. Level of Ordinary Skill in the Art
`
`In determining whether an invention would have been obvious at the
`time it was made, we consider the level of ordinary skill in the pertinent art
`at the time of the invention. Graham v. John Deere Co, 383 U.S. 1, 17
`(1966). Petitioner contends a person of ordinary skill in the art at the time of
`the alleged invention of the ’315 patent (a “POSITA”) would have had, inter
`alia, a bachelor’s degree in electrical, electronics, computer engineering; or
`the equivalent training, and would have had approximately 2 to 3 years of
`experience in computer systems, circuits, electronics, or a related discipline.
`Pet. 9; Ex. 1002 ¶¶ 27–30. Patent Owner does not contest Petitioner’s
`description of the level of ordinary skill. See PO Resp. 8.
`Based on our review of the ’315 patent, the cited prior art, and
`Dr. Wolfe’s testimony, we determine a specific finding regarding ordinary
`skill level is not required as the prior art reflects an appropriate level. See
`Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (explaining that
`specific findings regarding ordinary skill level are not required “where the
`prior art itself reflects an appropriate level and a need for testimony is not
`shown”). However, to the extent a specific finding regarding the level of
`skill is required, we find Petitioner’s articulation of a person of ordinary skill
`in the art is consistent with the teachings of the prior art and adopt
`Petitioner’s description of a POSITA as someone who “would have had a
`bachelor’s degree in electrical, electronics, or computer engineering; or the
`equivalent training, and would have had approximately two to three years of
`experience in computer systems, circuits, electronics, or a related
`discipline.” See Pet. 9.
`
`10
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`
`
`IPR2017-02021
`Patent 6,243,315 B1
`
`B. Claim Construction
`
`In an inter partes review filed before November 13, 2018, such as
`here, we construe claim terms in an unexpired patent according to their
`broadest reasonable construction in light of the specification of the patent in
`which they appear. 37 C.F.R. § 42.100(b) (2017)9; Cuozzo Speed Techs.,
`LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016) (upholding the use of the
`broadest reasonable interpretation standard); Office Patent Trial Practice
`Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012). Consistent with the
`broadest reasonable construction, claim terms are presumed to have their
`ordinary and customary meaning as understood by a person of ordinary skill
`in the art in the context of the entire patent disclosure. In re Translogic
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`Petitioner asserts that under the broadest reasonable construction, the
`plain meaning of the phrase “selectively electrically isolating said memory
`devices from respective address lines and respective control lines,” found in
`independent claims 1 and 10, “in the context of conventional memory
`devices and signals is that such signals are inhibited from arriving at the
`given memory devices.” Pet. 10 (citing Ex. 1002 ¶ 47). In its Preliminary
`Response, Patent Owner did not identify any claim terms as warranting
`explicit construction but did argue the claims of the ’315 patent require that
`“all address and control lines are electrically isolated from the memory
`
`
`9 This rule has been amended for later filed cases. See 37 C.F.R.
`§ 42.100(b)(2018); see also Changes to the Claim Construction Standard for
`Interpreting Claims in Trial Proceedings Before the Patent Trial and Appeal
`Board, 83 Fed. Reg. 51,340, 51,340 (Oct. 11, 2018) (stating “[t]his rule is
`effective on November 13, 2018 and applies to all IPR, PGR, and CBM
`petitions filed on or after the effective date”).
`
`11
`
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`IPR2017-02021
`Patent 6,243,315 B1
`devices in the self refresh mode to avoid erratic signals from damaging or
`otherwise corrupting the data in the memory.” Prelim. Resp. 2 (emphasis
`added). Patent Owner argued, inter alia, the asserted prior art reference (i.e.,
`Dell) did not anticipate the challenged claims of the ’315 patent because
`Dell did not isolate a control line (i.e., clock enable (“CKE”) line) from its
`memory bank, even when the memory bank is in a power down state. See
`id. at 11.
`In our Decision on Institution, we disagreed with Patent Owner’s
`argument that the claims required electrically isolating all address and
`control lines from the memory device. Dec. on Inst. 12–13. We explained
`that the ’315 patent identifies a number of address and control lines but only
`discusses electrically isolating certain of those address and control lines. Id.
`at 13. Specifically, we identified the embodiment of Figure 1, which the
`’315 patent describes as electrically isolating lines on control bus 22 and
`address bus 17 but does not describe as electrically isolating RAS and WE
`control lines 26 or 28. Id. We also identified the embodiment of Figure 4,
`which the ’315 patent describes as electrically isolating control lines 122 and
`address lines 117 but does not describe as electrically isolating RAS and WE
`control lines 126 or 128. Id.
`In its Response, Patent Owner again argues that claims 1 and 10
`require all address and control lines to be electrically isolated from the
`memory devices to avoid erratic signals from corrupting data in the memory
`devices. See, e.g., PO Resp. 14–16. Patent Owner contends the ’315 patent
`“makes it clear that the claimed invention is to protect the data in the
`memory devices during self refresh from errant signals which might reach
`the memory devices.” PO Resp. 14 (citing Ex. 1001, 4:11–24, 5:63–67).
`
`12
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`IPR2017-02021
`Patent 6,243,315 B1
`Petitioner replies the claims only require “isolation from ‘respective
`address lines and respective control lines’––not all address lines and all
`control lines.” Reply 9–10. Petitioner argues Patent Owner
`mischaracterizes the stated purpose of the ’315 Patent, which is to isolate the
`memory from only the specifically identified address lines and control
`lines—not every single conceivable signal. Id. at 7 (citing Ex. 1001, 5:63–
`67).
`
`Based upon a review of the full record, we determine the broadest
`reasonable construction consistent with the Specification of a control device
`“for selectively electrically isolating said memory devices from respective
`address lines and respective control lines so that when said memory devices
`are electrically isolated, any signals received on said respective address lines
`and respective control lines do not reach said memory devices” as recited in
`independent claims 1 and 10 requires that the control device electrically
`isolate the memory devices from all address and control lines that
`communicate with the memory devices.10
`The plain language of the claims requires that the selected memory
`devices are electrically isolated from their respective address and control
`lines. See Ex. 1001, 13:26–28, 14:11–18. In accordance with the plain and
`ordinary meaning, the reference in claim 1 to “respective address lines” and
`“respective control lines” is inclusive of all such lines for the selected
`memory device.
`We further find that a claim construction limited to isolating all of a
`selected memory device’s address and control lines is consistent with the
`
`
`10 We note that the same claim construction issue was presented in IPR2017-
`01994 and that we have adopted the same construction in both proceedings.
`IPR2017-01994, Paper 16, 11–17.
`
`13
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`IPR2017-02021
`Patent 6,243,315 B1
`purpose of such isolation expressed in claims 1 and 10, i.e., “so that when
`said memory devices are electrically isolated, any signals received on said
`respective address lines and said respective control lines do not reach said
`memory devices.” Id. at 13:27–30, 14:15–18 (emphasis added).
`Our construction is also consistent with the Specification of the ’315
`patent, which explains that the invention prevents “errant control and
`address signals to the memory devices” by “electrically isolating the
`memory devices from signals received on the control lines and address
`lines.” Id. at 3:15–24. The ’315 patent states that when the memory devices
`are electrically isolated from the respective address lines and respective
`control lines, “any signals received on said respective address lines and
`respective control lines do not reach the memory devices.” Id. at 4:16–24;
`see also id. at 3:25–30 (stating the “memory system maintains the integrity
`of the data retained by the memory devices by isolating the devices from the
`external power source, control lines and address lines”); id. at 5:63–67 (“By
`isolating the memory devices from the control buss 22 and address buss 17
`the control device 15 prevents errant signals from erroneously changing or
`affecting the data being retained by the memory devices 5.”). We are
`persuaded by Patent Owner’s argument that the purpose of the invention––to
`prevent errant control and address signals from reaching the memory
`devices––would not be achieved if errant signals on some control lines were
`able to reach the memory devices.
`The ’315 patent states that RAS and WE control lines 26, 28 are
`connected to memory access enable control device 30. Ex. 1001, 6:1–3.
`There is no express teaching that RAS control line 26 and WE control
`line 28 communicate with memory device 5. As such, there is no teaching
`in the ’315 patent that memory devices 5 would need to be electrically
`
`14
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`IPR2017-02021
`Patent 6,243,315 B1
`isolated from RAS and WE control lines 26, 28 to prevent errant signals on
`these control lines from reaching the memory devices.
`Similarly, the ’315 patent states that RAS and WE control lines 126
`and 128 of Figure 4 are “connected to the control device” but does not state
`that the RAS and WE control lines communicate with memory devices.
`Ex. 1001, 9:24–26. Rather, the ’315 patent states that the outputs from the
`control device are address lines 120 and control lines 124 and that these
`outputs are inputs to the memory devices. Id. at 9:33–36. There is no
`disclosure in the ’315 patent that the RAS and WE control lines are inputs to
`the memory devices. As such, there is no teaching in the ’315 patent that
`memory devices 5 would need to be electrically isolated from RAS and WE
`control lines 126, 128 to prevent errant signals on these control lines from
`reaching the memory devices.
`Therefore, for the foregoing reasons, we determine the broadest
`reasonable construction consistent with the Specification of a control device
`“for selectively electrically isolating said memory devices from respective
`address lines and respective control lines so that when said memory devices
`are electrically isolated, any signals received on said respective address lines
`and respective control lines do not reach said memory devices” as recited in
`independent claims 1 and 10 requires that the control device electrically
`isolate the memory devices from all address and control lines that
`communicate with the memory devices. This construction is the same as our
`construction in Case IPR2017-01994. See IPR2017-01994, Paper 16, 14.
`We determine that no further claim construction is required to resolve the
`issues in dispute. See Nidec Motor Corp. v. Zhongshan Broad Ocean Motor
`Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (stating that only claim terms in
`
`15
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`Patent 6,243,315 B1
`controversy need to be construed and only to the extent necessary to resolve
`the controversy).
`
`C. Principles of Law
`
`To establish anticipation, each and every element in a claim, arranged
`as recited in the claim, must be found in a single prior art reference. Net
`MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008);
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
`2001). Each element of the challenged claim must be found, either
`expressly or inherently, in the single prior art reference. Verdegaal Bros.,
`Inc. v. Union Oil Co. of Cal., 814 F.2d 628, 631 (Fed. Cir. 1987). While the
`elements must be arranged or combined in the same way as in the claim,
`“the reference need not satisfy an ipsissimis verbis test,” i.e., identity of
`terminology is not required. In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir.
`2009); In re Bond, 910 F.2d 831, 832 (Fed. Cir. 1990). Thus, the dispositive
`question is whether one skilled in the art would have reasonably understood
`or inferred from a prior art reference that every claim element is disclosed in
`that reference. Eli Lilly v. Los Angeles Biomedical Research Inst. at
`Harbor–UCLA Med. Ctr., 849 F.3d 1073, 1074–75 (Fed. Cir. 2017). Still
`further, “it is proper to take into account not only specific teachings of the
`reference but also the inferences which one skilled in the art would
`reasonably be expected to draw therefrom.” In re Preda, 401 F.2d 825, 826
`(CCPA 1968).
`A claim is unpatentable under 35 U.S.C. § 103(a) if “the differences
`between the subject matter sought to be patented and the prior art are such
`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
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`Patent 6,243,315 B1
`subject matter pertains.” The question of obviousness is resolved on the
`basis of underlying factual determinations, including: (1) the scope and
`content of the prior art; (2) any differences between the claimed subject
`matter and the prior art; (3) the level of skill in the art; and (4) objective
`evidence of nonobviousness, i.e., secondary considerations11. See Graham,
`383 U.S. at 17–18. Additionally, the obviousness inquiry typically requires
`an analysis of “whether there was an apparent reason to combine the known
`elements in the fashion claimed by the patent at issue.” KSR Int’l Co. v.
`Teleflex Inc., 550 U.S. 398, 418 (2007) (citing In re Kahn, 441 F.3d 977,
`988 (Fed. Cir. 2006) (requiring “articulated reasoning with some rational
`underpinning to support the legal conclusion of obviousness”)).
`To prevail on its challenges, Petitioner must demonstrate by a
`preponderance of the evidence that the claims are unpatentable. 35 U.S.C.
`§ 316(e); 37 C.F.R. § 42.1(d). “In an [inter partes review], the petitioner has
`the burden from the onset to show with particularity why the patent it
`challenges is unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d
`1356, 1363 (Fed. Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter
`partes review petitions to identify “with particularity . . . the evidence that
`supports the grounds for the challenge to each claim”)). This burden never
`shifts to Patent Owner. See Dynamic Drinkware, LLC. v. Nat’l Graphics,
`Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015) (citing Tech. Licensing Corp. v.
`Videotek, Inc., 545 F.3d 1316, 1326–27 (Fed. Cir. 2008)) (discussing the
`burden of proof in inter partes review). Furthermore, Petitioner does not
`satisfy its burden of proving obviousness by employing “mere conclusory
`
`
`11 The parties have not provided any evidence or argument directed to
`secondary considerations, and therefore, secondary considerations do not
`constitute part of our analysis.
`
`17
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`IPR2017-02021
`Patent 6,243,315 B1
`statements,” but “must instead articulate specific reasoning, based on
`evidence of record, to support the legal conclusion of obviousness.” In re
`Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016).
`
`D. Overview of the Asserted Art
`
`1. Dell (Ex. 1004)
`Dell, titled “Power Management on a Memory Card Having a Signal
`Processing Element,” describes a memory module having individually
`addressable banks of memory chips that can be placed into a higher or lower
`power state by a system memory controller or digital signal processor
`(“DSP”). Ex. 1004, at [54], 1:48–63. The memory module of Dell is able to
`selectively and expeditiously reduce power to individual banks of memory
`(or portions thereof) when they are not being accessed. Id. at 1:40–45.
`
`2. Abe (Ex. 1005)
`Abe is directed to a memory control circuit for initiating a self-refresh
`mode for a dynamic random access memory (“DRAM”) when the power
`supply voltage is lowered and for the self-refresh mode to consume less
`power. Ex. 1005, 1:5–10, 1:48–56. Abe discloses a main power supply and
`an auxiliary power supply, wherein the auxiliary supply is used for self
`refresh functions when the main power supply is cut off. Id. at 3:5–8.
`
`3. JESD21-C: Configurations for Solid State
`Memories (Ex. 1006)
`Petitioner asserts JESD21-C is a January 1997 publication of a
`JEDEC industry standard for memory devices. See Pet. 37. As an initial
`matter, we must determine whether Petitioner has made a threshold showing
`that JESD21-C is a prior art printed publication under 35 U.S.C. § 102(b).
`To qualify as a printed publication, a document must have been sufficiently
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`IPR2017-02021
`Patent 6,243,315 B1
`accessible to the public interested in the art before the critical date. In re
`Cronyn, 890 F.2d 1158, 1160 (Fed. Cir. 1989). A reference is deemed
`publically accessible upon a satisfactory showing that such document has
`been disseminated or otherwise made available to the extent persons
`interested and ordinarily skilled in the subject matter or art exercising
`reasonable diligence can locate it. Kyocera Wireless Corp. v. ITC, 545 F.3d
`1340, 1350–51 (Fed. Cir. 2008). Petitioner asserts JESD21-C was published
`January 1997 and is prior art under pre-AIA 35 U.S.C. § 102(b). Pet. 37–38.
`As support, Petitioner relies upon the Declaration of John J. Kelley (“the
`Kelley Declaration”), the current President of the Solid State Technology
`Association of the Joint Electron Device Engineering Council (“JEDEC”).
`See Ex. 1007 ¶ 2. Mr. Kelly states that JEDEC specification JESD21-C,
`Configurations for Solid State Memories, Release 7 (January 1997), a copy
`of which is attached to his declaration as Exhibit 17, “was made publicly
`available in January 1997.” Id. ¶¶ 4, 7. Mr. Kelley testifies that in January
`1997 copies of the entire JESD21-C volume “would . . . have been available
`for purchase by anyone in the public” and that “pages comprising the
`specifically updated modules would have been sent to those who subscribed
`to the annual updating service for JESD21-C.” Id. ¶ 6.
`Patent Owner does not dispute that JESD21-C qualifies as prior art
`under 35 U.S.C. § 102(b). See PO Resp. 7. Based on the current record, we
`determine JESD21-C qualifies as a prior art printed publication under
`§ 102(b).
`
`4. Ooishi (Ex. 1008)
`Ooishi is directed to a semiconductor memory device that reduces
`power consumption during a self-refresh operation. Ex. 1008, 1:41–43. The
`memory device of Ooishi has both a normal mode and a power down mode,
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`IPR2017-02021
`Patent 6,243,315 B1
`and further includes a self-refresh circuit that generates a refresh address
`signal when in power down mode. Id. at 1:44–50; 1:56–58. Ooishi also
`discloses a first power supply tha
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