`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-018411
`
`
`PETITIONER’S DEMONSTRATIVES FOR ORAL ARGUMENT
`
`
`1 Case IPR2017-01842 has been consolidated with this proceeding.
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICEUNITED STATES PATENT AND TRADEMARK OFFICE
`
`----------------------------------------------------------------
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARDBEFORE THE PATENT TRIAL AND APPEAL BOARD
`----------------------------------------------------------------
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. MANU
`
`
`v. v.
`GODOO KAISHA IP BRIDGE 1
`
`
`
`Inter Partes es Review Internterr Pter Partees eview Re
`
`
`
`
`
`
`
`
`
`
`Nos. IPR2017PR201177 1841 and IPR2011717-77--01841 and IPR2017171 -7-01842010 177 0
`U.S. Patent No. 7,893,501
`
`PETITIONER’S ORAL ARGUMENT
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`1
`
`
`
`Proposed Agenda
`
`Technology Background
`Overview of the ’501 Patent
`Overview of the Prior Art
`Undisputed Issues
`Obviousness of Claims
`Issues Raised by Patent Owner and Responses
`– Claim 1: whether applied prior art discloses a transistor
`that includes an active region
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`2
`
`
`
`Technology Background
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`3
`
`
`
`Basic Elements of a MISFET (Transistor)
`
`MISFETs include:
`– an active region made
`of a substrate, located
`between the shallow
`trench isolation regions
`(STI);
`– a gate insulating film
`(red);
`– a gate electrode
`(orange);
`– source and drain regions
`including a silicide layer
`(green); and
`– other elements such as
`sidewalls (purple)
`
`Example metal-insulator-semiconductor
`field effect transistors (MISFETs) from
`Plummer textbook (1st ed. 2000):
`
`Plummer at 86 (Ex. 1008) (annotated); see also Petition at
`6-7, Paper 2; Shanfield Decl., ¶¶33-44 (Ex. 1002); Rabaey
`at 42-43 (Ex-1010)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`4
`
`
`
`Active Regions
`
`Textbooks such as Plummer and Rabaey explain transistors are built in
`an active region, which is isolated from other active regions
`
`Plummer at 53 (Ex. 1008); see also Petition at 7-13, Paper 2; Shanfield Decl., ¶¶37-44 (Ex.
`1002); Reply at 7-8, Paper 22; Shanfield Reply Decl., ¶13 (Ex. 1027); D.I. at 8-9
`
`Rabaey at 42 (Ex. 1010); see also Petition at 7-13, 26, Paper 2; Shanfield Decl., ¶¶37-44,
`66 (Ex. 1002); Reply at 7-8, Paper 22; Shanfield Reply Decl., ¶13 (Ex. 1027); D.I. at 8-9
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`5
`
`
`
`Overview of the ’501 Patent
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`6
`
`
`
`The ʼ501 Patent
`
`Claimed MISFET includes:
`– an active region 1a made
`of a substrate 1;
`– a gate insulating film 5
`(red);
`– a gate electrode 6a
`(orange);
`– source and drain regions
`3a, 4a including a silicide
`layer (green); wherein:
`– the gate electrode 6a
`(orange) protrudes from a
`silicon nitride film 8a
`(blue).
`
`’501 Patent at 3:19-64, Fig. 1 (Ex. 1001); see also Petition
`at 15, Paper 2; Shanfield Decl., ¶¶45-46 (Ex. 1002)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`7
`
`
`
`’501 Patent File History
`
`Claims repeatedly rejected until amended to recite
`allegedly novel “protruding gate”
`’501 patent specification does not mention or
`identify any advantages of “protruding gate”
`
`August 5, 2010 Response at 8 (Ex. 1003); see also Petition at 1-2,
`19-21, Paper 2; Shanfield Decl., ¶¶53-56 (Ex. 1002)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`8
`
`
`
`The ʼ501 Patent, Claim 1
`
`’501 Patent at claim 1 (Ex. 1001)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`9
`
`
`
`Overview of the Prior Art
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`10
`
`
`
`Igarashi
`
`Igarashi’s MISFET includes
`each of the claimed elements,
`including the allegedly novel
`protruding gate:
`– an active region made of a
`substrate 1;
`– a gate insulating film 2
`(red);
`– a gate electrode 3
`(orange);
`– source and drain regions 4,
`including a silicide layer 5
`(green); wherein:
`– the gate electrode 3
`(orange) that protrudes
`from a silicon nitride film 8
`(blue).
`
`Igarashi at Fig. 12 (Ex. 1004); see also
`Petition at 16-17, Paper 2; Shanfield Decl., ¶¶47-48
`(Ex. 1002)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`11
`
`
`
`Igarashi
`
`Igarashi expressly
`discloses formation of
`active region made of a
`substrate 1 using trench
`method.
`
`Igarashi at [0068] (Ex. 1004)
`
`Igarashi at Fig. 1 (Ex. 1004)
`
`Igarashi at Fig. 12 (Ex. 1004)
`
`Petition at 16-17, 22-23, Paper 2; Shanfield Decl., ¶¶47-48, 60 (Ex. 1002)
`12
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Woerlee
`
`Secondary reference Woerlee expressly shows the
`active region made of the semiconductor substrate
`between two isolation regions
`
`Woerlee at 4:66-5:5 (Ex. 1006)
`
`Woerlee at Fig. 13 (Ex. 1006)
`
`Petition at 27-32, Paper 2; Shanfield
`Decl., ¶¶ 67-73 (Ex. 1002)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`13
`
`
`
`Undisputed Issues
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`14
`
`
`
`Undisputed Issues: “protruding gate”
`
`There is no dispute that Igarashi discloses the
`allegedly novel “protruding gate”
`
`’501 Patent at Fig. 1 (Ex. 1001)
`
`Igarashi at Fig. 12 (Ex. 1004)
`
`Petition at 14-16, 41-46, Paper 2; Shanfield Decl.,
`¶¶45-48, 91-102 (Ex. 1002)
`15
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`
`
`Undisputed Issues: “protruding gate”
`
`In fact, Patent Owner cites Igarashi’s disclosure as evidence of the
`purported advantages of the allegedly novel “protruding gate”:
`
`IPR2017-01843 POPR at 32 (emphasis added), Paper 6; see also
`Reply at 1, Paper 22
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`16
`
`
`
`Other Undisputed Issues
`
`Except for claimed “active region,” Patent Owner does
`not dispute instituted grounds disclose all other
`limitations
`– Patent Owner does not dispute that claimed “active region”
`was known in the art
`– In related IPR 2017-01843, Patent Owner does not dispute
`primary reference Misra discloses this limitation
`Patent Owner does not dispute references in the
`instituted grounds would have been obvious to
`combine
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`17
`
`Reply at 1-2, Paper 22
`
`
`
`Obviousness of the Claims
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`18
`
`
`
`ʼ501 Patent – MISFET That Includes an “Active Region”
`
`’501 Patent at claim 1 (Ex. 1001)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`19
`
`
`
`Igarashi Discloses Claimed “Active Region”
`
`Dr. Shanfield explains how Igarashi’s disclosure of forming an
`“active element region” made of “semiconductor substrate 1”
`would have been understood and how it discloses the claimed
`MISFET that includes an active region
`
`Igarashi at [0068] (Ex. 1004)
`
`Igarashi at Fig. 12 (Ex. 1004) (annotated)
`
`Petition at 24-27, Paper 2; Shanfield Decl., ¶¶64-66 (Ex. 1002)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`20
`
`
`
`Woerlee Confirms Obviousness of
`Claimed “Active Region”
`
`Secondary reference Woerlee expressly discloses MISFETs that
`include an active region made of the semiconductor substrate
`Woerlee expressly shows the active region formed between two
`isolation regions
`
`Woerlee at 4:66-5:5 (Ex. 1006)
`
`Woerlee at Fig. 13 (Ex. 1006)
`
`Petition at 27-32, Paper 2; Shanfield
`Decl., ¶¶ 67-73 (Ex. 1002)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`21
`
`
`
`Woerlee Confirms Obviousness of
`Claimed “Active Region”
`
`To the extent not expressly disclosed, secondary
`reference Woerlee confirms it would have been obvious
`to form Igarashi’s “active element region” in Igarashi’s
`“substrate 1” using the “trench method” (STI)
`
`Woerlee at Fig. 13, 4:66-5:5 (MISFET
`includes “active region 4” made of
`“semiconductor body 1” between
`“isolating regions 3”) (Ex. 1006)
`
`Igarashi at Fig. 12 (Ex. 1004) (annotated), [0068]
`(MISFETs include “active element region” made of
`“semiconductor substrate 1” formed using the
`“trench method” of isolation)
`Petition at 27-37, Paper 2; Shanfield Decl.,
`¶¶ 67-81 (Ex. 1002)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`22
`
`
`
`Issues Raised by Patent Owner
`and Responses
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`23
`
`
`
`Issues Raised by Patent Owner
`
`Claim 1: whether applied prior art discloses a
`transistor that includes an “active region”
`– First, Patent Owner argues the claims require a “one-to-
`one correspondence” between an active region and a
`MISFET
`– Second, Patent Owner argues Igarashi’s express disclosure
`of an “active element region” does not apply to Igarashi’s
`Fig. 12 embodiment
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`24
`
`
`
`Response to Patent
`Owner’s First Argument
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`25
`
`
`
`The Board Properly Rejected Patent Owner’s
`Narrow View of “an active region”
`
`D.I. at 8, Paper 10
`
`D.I. at 9, Paper 10
`
`Reply at 1, 3, Paper 22
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`26
`
`
`
`Patent Owner’s Response Advances the Same Argument
`
`Patent Owner no longer advances its rejected
`construction
`But Patent Owner still attempts to read-in a
`requirement of a “one-to-one correspondence”
`
`Response at 26, 74; Reply at 5, Paper 22
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`27
`
`
`
`Patent Owner’s Interpretation Improperly Reads
`Limitations into the Claims
`
`Patent Owner attempts to
`read-in the requirements,
`which are not recited Claim 1:
`– “region in which a single
`transistor is formed”
`(POR at 74)
`– “one-to-one correspondence”
`(POR at 76)
`No basis for importing any of
`these IPR-induced limitations
`
`Response at 26, 74, Paper 20;
`Reply at 3, 5, Paper 22
`
`’501 Patent at claim 1 (Ex. 1001)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`28
`
`
`
`Patent Owner’s Expert Admits
`“Includes” Is Open-Ended
`
`Q. And similarly, from your work on
`patent cases, do you have an
`understanding of what the term
`“includes” means in the context of
`patent claims?
`A. My general – the general instruction I
`received in patent cases is that
`“includes” means that it has at least
`these features.
`Q. Are those the understandings you
`applied in your analysis in this case?
`A. The standard that I applied for
`includes would essentially, yes, that it
`has at least these elements.
`Glew Tr. at 94:20-95:7 (Ex. 1024)
`Reply, 20-21, Paper 22; Glew Sur-Reply Tr. at 93:15-22 (Ex. 1029) (confirming he stands by his
`prior testimony); Sur-Sur-Reply at 2-3, Paper 33
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`’501 Patent at claim 1 (Ex. 1001)
`
`29
`
`
`
`There Is No Dispute That Igarashi’s MISFET Includes
`Each Identified Component of an “Active Region”
`
`Q. What are the components of an active region?
`A. Well, a region is a geographical distinction. What’s in that geographical
`distinction can vary, but it would include, at least, the source gate and
`drain regions or actually the source channel and drain regions for a
`typical transistor.
`
`Glew Sur-Reply Tr. at 70:5-12 (Ex. 1029)
`
`Igarashi’s source and drain regions, including silicide
`layer (4 and 5) (green)
`Petition at 16-17, 23, 39-41; Igarashi at [0044], [0068], Fig. 12 (Ex. 1004); Sur-Sur-Reply at 3, Paper 33
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`30
`
`
`
`Textbooks Cited in Petition Confirm an Active Region
`Is Not Limited to a Single Transistor
`
`Contrary to the assertions in the POR, the textbooks
`cited in the Petition recognize an active region can
`include “transistors” (plural)
`
`Plummer at 53 (Ex. 1008)
`
`Rabaey at 42 (Ex. 1010)
`
`Reply at 7, Paper 22; Petition at 7-8, 26, Paper 2
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`31
`
`
`
`Petitioner’s Reply Confirms an Active Region
`Is Not Limited to a Single Transistor
`Contrary to Patent Owner’s assertion that “a transistor’s active
`region refers to a region in which a single transistor is formed,”
`Agata shows MOSFET 10a and MOSFET 10b (green) formed in
`active region 2 (blue)
`
`Agata at Fig. 2 (Ex. 1025) (annotated)
`
`Reply at 11-12, Paper 22; Agata at 5:18-19, 5:33-38, Fig. 2 (Ex. 1025);
`Shanfield Reply Decl., ¶17 (Ex. 1027)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`32
`
`
`
`Patent Owner and Its Expert Concede an Active Region
`Can Have Multiple Transistors
`
`Patent Owner’s response had argued an active region can
`have only a single transistor:
`– Arguing “a transistor’s active region refers to a region in which a single
`transistor is formed” (POR at 74) (emphasis added)
`After reviewing Agata, Patent Owner and its expert concede
`an active region can have multiple transistors:
`– Admitting “the active region of a multi-transistor device in Agata and
`Rashed has multiple transistors”(PO’s Sur Reply at 2) (emphasis
`omitted)
`– Admitting “multiple transistors exist in an active region of a multi-
`transistor device” (Glew Sur Reply Decl., ¶ 6) (emphasis omitted)
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`33
`
`Sur-Sur-Reply at 1-2, Paper 33
`
`
`
`PO’s Expert Unable to Answer Basic Questions About
`Whether a MISFET Includes an Active Region
`
`Dr. Glew was unable to say whether the MISFET in his
`drawing of “a MISFET that includes an active region” (left)
`still includes an active region when the isolation regions
`are spaced further apart (right)
`
`Ex. 1028, Figure 1
`
`Ex. 1028, Figure 2
`
`Glew Sur-Reply Tr. at 16:4-23 (Ex. 1029);
`Sur-Sur-Reply at 2, Paper 33
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`34
`
`
`
`PO’s Expert Unable to Answer Basic Questions About
`Whether a MISFET Includes an Active Region
`
`Dr. Glew was unable to say whether the MISFET in his
`drawing of “a MISFET that includes an active region” (left)
`still includes an active region when a second MISFET is
`added (right)
`
`Ex. 1028, Figure 1
`
`Ex. 1028, Figure 3
`
`Glew Sur-Reply Tr. at 19:3-11 (Ex. 1029); Sur-Sur-Reply at 2, Paper 33
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`35
`
`
`
`PO’s Expert Unable to Answer Basic Questions About
`Whether a MISFET Includes an Active Region
`
`Patent Owner’s expert initially testified an “active
`region” is “the region where the transistor is
`formed.” (Glew Tr., Ex. 1024, 43:10-14)
`
`On Sur-Reply Cross, when asked whether each
`transistor in Igarashi’s Fig. 12 “includes an area
`where the transistor is formed,” Patent Owner’s
`expert testified this was “not an opinion I've given or
`analyzed.” (Glew Sur-Reply Tr., 63:10-20 (Ex. 1029))
`
`Sur-Sur-Reply at 2-3, Paper 33
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`36
`
`
`
`Dr. Glew Hasn’t Thought Through How His Interpretation
`of “includes” Applies to All Challenged Claims
`Claim 10 recognizes that the “active region” of claim 1 may be
`“divided by an isolation region”
`
`ʼ501 Patent, claim 10 (Ex. 1001)
`Dr. Glew admitted this requirement of claim 10 “doesn’t make
`physical sense” under his interpretation of claim 1
`Q. Could a person of skill in the art form an isolation region that
`divides the active region that’s included in the MISFET?
`* * *
`It’s nothing I’ve opined on. It doesn’t make physical sense to
`me.
`
`A.
`
`Dr. Glew at 66:23-67:3 (Ex. 1029)
`
`Glew Sur-Reply Tr. at 66:23-67:3 (Ex. 1029); Sur-Sur-Reply at 3, Paper 33
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`37
`
`
`
`Patent Owner Cannot Reconcile Its Interpretation in This
`IPR With Its Own Infringement Contentions
`Patent Owner asserts in this proceeding that it is “uncontroverted” that
`the claims allow only a “single” transistor in the active region, while
`arguing the opposite in district court
`
`Patent Owner’s Interpretation In IPR
`
`Patent Owner’s Interpretation
`In District Court
`
`POR at 74, Paper 20
`
`Infringement Contentions at 32 (Ex. 1021)
`Sur-Sur-Reply at 2, Paper 33; Reply at 6-7, Paper 22
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`38
`
`
`
`Patent Owner Offers Claim Construction for Different
`Terms in Each Proceeding
`
`Patent Owner offers constructions for different terms in each
`proceeding, despite both proceedings addressing the same
`challenged patent and claims.
`
`In IPR2017-01841, Patent Owner only offers construction of
`an “active region made of a semiconductor substrate.”
`
`In IPR2017-01843, Patent Owner only offers construction of a
`“silicon nitride film.”
`
`These constructions are not offered to provide an
`understanding of the claims terms, but rather as a vehicle to
`argue patentability independently in each proceeding
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Reply at 5, Paper 22
`
`39
`
`
`
`Response to Patent
`Owner’s Second Argument
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`40
`
`
`
`Igarashi Expressly Discloses “an active region”
`Igarashi uses common reference numerals for substrate 1 where
`active region is formed
`
`Igarashi at Figs. 1, 12, [0068], [0117] (Ex. 1004)
`This uniform numbering scheme for common features is
`undeniably evident when the two figures in Igarashi are viewed
`side by side
`
`Petition, 22-25, Paper 2; Reply at 17-18, Paper 22; DI, 19-20, Paper 10
`Shanfield Decl., ¶¶ 25-26 (Ex. 1002); Shanfield Reply Decl., ¶26 (Ex. 1027)
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`41
`
`
`
`Dr. Glew Agrees That Common Reference Numerals
`Describe Common Features
`
`“… Figure 9 shows the isolation region in a different
`embodiment, but I also understand that the isolation
`region 2 would be substantially similar…”
`
`“…it uses the same Item No. 2, which indicates to me
`that it is going to be substantially similar to the other
`uses of Item 2.”
`
`Glew Tr. at 81:8-24 (Ex. 1024);
`Reply at 17-18, Paper 22
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`42
`
`
`
`Patent Owner Does Not Dispute Combinability of
`Igarashi and Woerlee
`
`Patent Owner Does Not Dispute Combinability of Igarashi
`and Woerlee
`Patent Owner argues that Petition relies on Woerlee only
`for the location of the active region, not for forming the
`active region in Fig. 12 embodiment, ignoring express
`statements in Petition:
`
`Petition at 31, Paper 2; id. at 32; POR, 37
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`43
`
`
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Opening-44
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Demonstratives for Oral Argument
`
`
`
`
`
`Dated: September 5, 2018 Respectfully Submitted,
`
`/Michael Smith /________________
`Michael H. Smith, Reg. No. 71,190
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Demonstratives for Oral Argument
`
`CERTIFICATE OF SERVICE
`I hereby certify that, on September 5, 2018, I caused a true and correct copy of the
`
`foregoing materials:
`
` Petitioner’s Demonstratives for Oral Argument
`
`to be served via email on the following counsel of record as listed in Patent
`
`Owner’s Mandatory Notices:
`
`Gerald B. Hrycyszyn, Registration No. 50,474
`GHrycyszyn-PTAB@wolfgreenfield.com
`
`Richard F. Giunta, Registration No. 36,149
`RGiunta-PTAB@wolfgreenfield.com
`
`Edmund J. Walsh, Registration No. 32,950
`EWalsh-PTAB@wolfgreenfield.com
`
`Joshua Miller, admitted pro hac vice
`Joshua.Miller@wolfgreenfield.com
`
`Wolf, Greenfield & Sacks, P.C.
`600 Atlantic Avenue
`Boston, Ma 02210
`
`Respectfully Submitted,
`
`___/ Michael Smith/__________
`Michael H. Smith
`Registration No. 71,190
`
`