DOCKET NO.: 2003195-00123US1 and US2
`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-018411
`
`PETITIONER’S SUR-SUR-REPLY PURSUANT TO JULY 20, 2018 ORDER
`
`1 Case IPR2017-01842 has been consolidated with this proceeding.
`
`
`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-018411
`
`PETITIONER’S SUR-SUR-REPLY PURSUANT TO JULY 20, 2018 ORDER
`
`1 Case IPR2017-01842 has been consolidated with this proceeding.
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`Claim 1 recites a transistor (MISFET) that includes conventional features
`
`such as an active region, a source, a drain, and a gate. Pet., 1, 8, 14. The Petition
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`demonstrated how Igarashi’s Fig. 12 MISFETs include these elements. Pet., 17,
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`23-33, 39-41. This is true whether Igarashi’s Fig. 12 is viewed as having one
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`active region or more than one active region. Pet. 24-33; Reply, 19-22. PO
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`attempted to distinguish Igarashi by arguing “active region” requires one-to-one
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`correspondence between a MISFET and an active region. E.g., POR, 74-75;
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`POPR, 29-30. Agata (Ex. 1025) and Rashed (Ex. 1026) unambiguously show
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`multiple transistors formed in an “active region,” refuting PO’s position. Reply,
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`10-13. PO does not dispute this. Sur-reply, 1-3. Likewise, Dr. Glew backed away
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`from his prior testimony and testified he had no opinion on the term “active
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`region.” Compare Ex. 2007, ¶¶62-85, 148-149 with Ex. 1029, 46:1-47:6.
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`PO’s sur-reply instead argues the MISFETs in Igarashi’s Fig. 12 do not
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`“include” an active region. The Board has rightly rejected this argument. DI, 9.
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`PO’s sur-reply does not alter this conclusion.
`
`First, PO’s argument that the Reply mischaracterized Dr. Glew’s testimony
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`fails. Sur-reply, 2. It did not. Compare Reply, 20-21 with Ex. 1024 at 94:13-95:7.
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`Dr. Glew confirms that he stands by his testimony that “includes” is an open-ended
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`term like comprises. Ex. 1029, 93:15-22; Ex. 1024 at 94:13-95:7. The term
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`“includes” does not prevent the MISFET from including other features or prevent
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`1
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`
`
`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`
`other MISFETS from being formed in the same active region. Moreover, PO’s
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`supposed “one-to-one correspondence” (Sur-reply, 1-3) is directly contradicted by
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`PO’s infringement contentions. Reply, 6-7, citing Ex. 1021, 32. Ex. 1027, ¶11.
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`PO’s contradictory positions cannot be reconciled, nor does PO even try.
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`Second, Dr. Glew’s inability to answer basic questions on cross shows his
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`attempts to reconcile his testimony with Agata and Rashed are not credible. For
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`example, when Dr. Glew’s drawing of a MISFET that “includes” an active region
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`(Ex. 1028, Fig. 1) was reproduced with the isolation regions spaced further apart
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`(Ex. 1028, Fig. 2), Dr. Glew was unable to say whether the same MISFET still
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`“included” an active region. Ex. 1029, 16:4-23. Similarly, when Petitioner
`
`attempted to obtain Dr. Glew’s opinion of whether the MISFET would still
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`“include” an active region if a second transistor were added, Dr. Glew refused to
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`draw a second transistor and testified he had no opinion. Ex. 1029, 19:3-11.
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`Dr. Glew was also unable to say whether the device in Igarashi’s Fig. 12
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`“includes” an active region, demonstrating that his attempts to distinguish Agata
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`and Rashed are not credible. Ex. 1029, 62:5-63:9. Dr. Glew’s answers on cross-
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`examination also reveal the superficial nature of his analysis. Dr. Glew previously
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`testified that “the active region is the region where the transistor is formed.” Ex.
`
`1024, 43:10-14. When asked on cross whether “each transistor in Figure 12
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`2
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`
`
`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`
`
`includes an area where the transistor is formed,” he testified, “[T]his is not an
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`opinion I've given or analyzed.” Ex. 1029, 63:10-20.
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`Third, Dr. Glew’s testimony confirms PO’s position “doesn't make physical
`
`sense.” When asked whether, under his interpretation, the active region of claim 1
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`could be divided by isolation regions (as recited in claim 10), Dr. Glew testified
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`that “it doesn't make physical sense.” Ex. 1029, 66:23-67:3; Ex. 1001, claim 10.
`
`Fourth, Dr. Glew confirms that Igarashi’s Fig. 12 MISFETs “include” an
`
`active region. When asked what components are in an active region, Dr. Glew
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`testified that it “would include, at least… the source channel and drain regions for
`
`a typical transistor.” Ex. 1029, 70:5-12. There is no dispute that Igarashi’s
`
`identified “active region” includes these same components. See e.g., Petition, 16-
`
`17, 23, 39-41, citing Ex. 1002, ¶¶47-48, 88-90, Ex. 1004, Fig. 12, [0044], [0068].
`
`Fifth, PO’s attempt to rebut Dr. Shanfield’s showing that “all functional
`
`MOSFET transistors have an active region” fails. PO has not identified a single
`
`reference that describes a MISFET as not including an active region—because all
`
`functional transistors include an active region. E.g., Reply, 10-11; Pet. 7-13.
`
`Dated: August 8, 2018 Respectfully Submitted,
`
`/Michael Smith/________________
`Michael H. Smith, Reg. No. 71,190
`
`
`
`3
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`
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`
`PETITIONER’S LIST OF EXHIBITS FOR
`IPR2017-01841
`
`Exhibit
`
`Description
`
`1001
`
`U.S. Patent No. 7,893,501
`
`1002
`
`Declaration of Stanley R. Shanfield, Ph.D. Regarding U.S. Patent
`No. 7,893,501, Claims 1, 4, 7, 9-11, 14, 16-18, and 23-25
`(“Shanfield Decl.”)
`
`1003
`
`Applicant’s Amendment and Response dated August 6, 2010
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`U.S. Patent Publication No. 2002/0145156 to Igarashi et al.
`(“Igarashi”)
`
`U.S. Patent No. 5,960,270 to Misra et al. (“Misra”)
`
`U.S. Patent No. 6,406,963 to Woerlee et al. (“Woerlee”)
`
`Notice of Allowance dated October 15, 2010
`
`J. Plummer et al., Silicon VLSI Technology: Fundamentals,
`Practice and Modeling, (1st ed. 2000)
`
` W.O. Publication No. 2002/043151 with certified English
`translation (“Shimizu”)
`
`J. Rabaey et al., Digital Integrated Circuits, at 40-44 (2d ed. 2003)
`(“Rabaey”)
`
`S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits:
`Analysis and Design, (2d. ed. 2003) (“Kang”)
`
`K. Maex, Simply irresistible silicides, Physics World, at 35-39
`(Nov. 1995)
`
`1013
`
`U.S. Patent No. 6,806,584
`
`1
`
`
`
`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`
`
`Exhibit
`
`Description
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`B. Deal, Current Concepts in Passivation and Encapsulation of
`Semiconductor Devices, 10th Electrical Insulation Conf., at 63-68
`(Sept. 1971)
`
`T. Ogura et al., A Shallow Trench Isolation with SiN Guard-Ring
`for Sub-Quarter Micron CMOS Technologies, Symposium on
`VLSI Technology Digest of Technical Papers, at 210-211 (1998)
`
`U.S. Patent No. 6,509,234
`
`U.S. Patent No. 5,726,479
`
`U.S. Patent No. 6,512,266
`
`U.S. Patent No. 6,350,661 (“Lim”)
`
`December 19, 2017 Conference Call Transcript
`
`Infringement contentions dated February 1, 2017 for U.S. Patent
`7,893,501 from Godo Kaisha IP Bridge 1 v. Xilinx, Inc., Case No.
`Case No. 2:17-cv-00100 (E.D. Tex.)
`
`A. Allan et al., 2001 Technology Roadmap For Semiconductors,
`Excerpts from the Executive Summary and three chapters of The
`International Technology Roadmap for Semiconductors, 2001
`edition, International Sematech, Austin, Texas, 2001
`
`1023
`
`Declaration of Alexander D. Glew, Ph.D. in IPR2016-00386
`
`1024
`
`1025
`
`1026
`
`1027
`
`Deposition Transcript of Alexander D. Glew, Ph.D.
`June 14, 2018
`
`U.S. Patent No. 5,389,810 (“Agata”)
`
`U.S. Patent No. 8,618,607 (“Rashed”)
`
`Reply Declaration of Stanley R. Shanfield, Ph.D.
`
`
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`2
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`
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`
`
`Exhibit
`
`1028
`
`1029
`
`Description
`
`Exhibit to Deposition of Alexander D. Glew, Ph.D.
`Deposition Transcript of Alexander D. Glew, Ph.D.
`August 1, 2018
`
`
`
`
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`3
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`
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`CERTIFICATE OF SERVICE
`I hereby certify that, on August 8, 2018, I caused a true and correct copy of the
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`foregoing materials:
`
` Petitioner’s Sur-Sur-Reply Pursuant to July 20, 2018 Order
`
` Exhibits 1028-1029
`
` Petitioner’s Updated Exhibit List
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`to be served via email on the following counsel of record as listed in Patent
`
`Owner’s Mandatory Notices:
`
`Gerald B. Hrycyszyn, Registration No. 50,474
`GHrycyszyn-PTAB@wolfgreenfield.com
`
`Richard F. Giunta, Registration No. 36,149
`RGiunta-PTAB@wolfgreenfield.com
`
`Edmund J. Walsh, Registration No. 32,950
`EWalsh-PTAB@wolfgreenfield.com
`
`Joshua Miller, admitted pro hac vice
`Joshua.Miller@wolfgreenfield.com
`
`Wolf, Greenfield & Sacks, P.C.
`600 Atlantic Avenue
`Boston, Ma 02210
`
`Respectfully Submitted,
`
`___/Michael Smith/__________
`Michael H. Smith
`Registration No. 71,190
`
`
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