`
`DOCKET NO.: 2003195-00123US1 and US2
`Filed By: David L. Cavanaugh, Reg. No. 36,476
`Dominic E. Massa, Reg. No. 44,905
`Michael H. Smith, Reg. No. 71,190
`1875 Pennsylvania Ave. NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
`Petitioner
`
`v.
`
`GODO KAISHA IP BRIDGE 1
`Patent Owner.
`
`Case IPR2017-018411
`
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
`
`
`
`
`1 Case IPR2017-01842 has been consolidated with this proceeding.
`
`
`
`
`
`
`
`Table of Contents
`
`I.
`II.
`
`III.
`
`Page
`Introduction ...................................................................................................... 1
`Patent Owner’s Interpretation of “an active region made of a semiconductor
`substrate” is Inappropriately Narrow ............................................................... 3
`Igarashi and Woerlee Disclose the Claimed “Active Region” ...................... 14
`A.
`Patent Owner’s Imagined Inherency Argument
`Mischaracterizes Dr. Shanfield’s testimony ....................................... 15
`Igarashi Discloses a MISFET that Includes an “Active Region” ....... 19
`Patent Owner’s Attacks on Dr. Shanfield’s Testimony are
`Purely a Distraction ............................................................................. 22
`Patent Owner Again Incorrectly Argues that the Petition Relies
`on Woerlee Only for the Location of the Active Region .................... 25
`IV. Conclusion ..................................................................................................... 28
`
`B.
`C.
`
`D.
`
`i
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`
`
`
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`I.
`
`INTRODUCTION
`Patent Owner’s Response (“Response”) confirms that the challenged claims
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`are unpatentable. There is no dispute that Igarashi discloses the allegedly novel
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`“protruding gate” that provided the basis for allowance.2 Moreover, Patent Owner
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`(“PO”) does not dispute that the instituted grounds expressly disclose every
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`limitation of the challenged claims, except the “active region.” Nor does PO
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`dispute that the references would have been obvious to combine. Instead, PO
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`merely repeats the same arguments that it already raised in its Patent Owner’s
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`Preliminary Response (“POPR”3) that Igarashi’s disclosure somehow lacks an
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`“active region,” one of the most basic aspects of a semiconductor device. These
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`arguments were correctly rejected by the Board in the Institution Decision (“DI”)
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`and fail again here.
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`2 In fact, PO actually cites Igarashi as evidence that the purported advantages of the
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`“protruding gate” were well-known. Ex. 2007, ¶¶45-50; see also IPR2017-01843
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`POPR, 32 (“[A] POSA would have understood that … causing the gate electrode
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`to protrude above the silicon nitride … would advantageously reduce parasitic
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`capacitance. Indeed, Igarashi teaches this explicitly.”), 30-36; IPR2017-01843
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`POR, 23-25; IPR2017-01843 Ex. 2208, ¶¶45-50.
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`3 Unless otherwise specified with the “-01842” prefix, references to exhibits and
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`papers herein are to those filed in Case IPR2017-01841.
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`
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
`
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`First, PO again attempts to limit the “active region” to a single transistor,
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`which the Board correctly rejected in the DI. DI, 8-9. PO’s interpretation of
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`“active region” is inappropriately narrow. Moreover, PO does not even attempt to
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`reconcile its outcome driven interpretation with its infringement contentions,
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`which identify an alleged “active region” with multiple transistors, directly
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`contradicting the arguments the PO advances before the Board. Nothing in the
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`’501 patent or any other evidence supports such a narrow interpretation, nor can
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`PO’s interpretation of “active region” withstand basic technical scrutiny.
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`
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`Second, PO again incorrectly argues that the Fifth Embodiment described in
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`Igarashi does not teach shallow trench isolation (“STI”) regions forming an active
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`region and that the Petition relies on Woerlee only for the location of the STI
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`regions, not formation of STI regions in Igarashi’s fifth embodiment. Response,
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`37. The Board correctly rejected this argument and should do so again here. DI,
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`19-20. The Petition is clear that a POSITA would have understood that the
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`disclosure of the features in Igarashi common to its different illustrations—
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`including the STI regions—are applicable to the Fifth Embodiment shown in, for
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`example, Figure 12. See e.g., Petition, 22 (“A POSITA would have understood
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`that the disclosure of the features in Igarashi common to different illustrations are
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`applicable to the embodiment shown in Figure 12 because the same reference
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`numerals are used to describe common features of Igarashi’s disclosure.”)
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`Moreover, the Petition is clear that it would have been obvious to apply Igarashi’s
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`undisputed teaching of an active region to the Fifth Embodiment. DI, 16 (quoting
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`Petition, 32) (“Petitioner also provides several reasons why a person of ordinary
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`skill in the art would have ‘appl[ied] Woerlee’s teachings to Igarashi by forming
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`Igarsahi’s active region in the substrate and defining it with STI regions that divide
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`the active region.’”)
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`As set forth in the Petition and confirmed below, the challenged claims of
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`the ’501 patent would have been obvious under the cited prior art references and,
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`accordingly, Petitioner respectfully requests that the Board cancel all challenged
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`claims.
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`II.
`
`PATENT OWNER’S INTERPRETATION OF “AN ACTIVE REGION
`MADE OF A SEMICONDUCTOR SUBSTRATE” IS
`INAPPROPRIATELY NARROW
`PO claims that “there is no dispute that under BRI, ‘an active region made of
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`a semiconductor substrate’ is ‘an area of the semiconductor substrate defined by an
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`isolation region where the transistor is formed.’” Response, 26. PO then advances
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`an unduly narrow interpretation of this proposed construction that seeks to limit the
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`active region to having only a single transistor, as it sought to do through a
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`different construction in the POPR, which the Board properly rejected. Response
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`74; POPR, 25, 29; DI, 9. Nothing in the ’501 patent or prior art requires such a
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`
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
`
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`one-to-one correspondence. Under PO’s inappropriately narrow interpretation,
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`PO’s proposed construction for “an active region made of a semiconductor
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`substrate” is indeed disputed. Ex. 1027, ¶7.
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`First, PO already tried to advance its narrow view of an “active region” in
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`the POPR, proposing the following construction: “a region of a semiconductor
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`substrate dedicated to the MISFET and defined by isolation regions that isolate the
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`MISFET from other transistors formed in the substrate.” POPR, 25. PO then (as it
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`does again in the Response) further interpreted its construction to require a single
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`transistor. POPR, 29 (arguing the “‘active region’ refers to a region dedicated to a
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`single transistor”); Response, 74 (arguing “active region refers to a region in which
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`a single transistor is formed”).4 The Board properly rejected this position in the
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`DI, highlighting examples of active regions in the prior art having more than one
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`transistor:
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`“For example, Plummer describes that “regions between these
`[isolation] layers, where transistors will be built, are called the ‘active’
`regions of the substrate” (Ex. 1008, 53), and Rabaey describes “active
`regions” as “the regions where transistors will be constructed” (Ex.
`1010, 42). Nothing about these descriptions connotes a requirement
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`4 Emphasis added unless otherwise noted.
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`for a one-to-one correspondence of active regions-to-transistors, as
`Patent Owner contends.”
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`DI, 9. Ex. 1027, ¶8.
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`Now in its Response, PO has merely reworded its prior construction but still
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`attempts to interpret the new construction in the same way already rejected by the
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`Board. That is, PO is forcing an additional “one-to-one correspondence”
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`requirement into its interpretation of an “active region.” (POPR, 25; Response,
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`26.)5 Ex. 1027, ¶9.
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`Second, Petitioner does not agree with PO’s construction as PO interprets it.
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`As noted above, PO mistakenly claims that there is no dispute as to this
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`construction and that the only dispute between the parties relates to whether the
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`claim requirement that “the MISFET includes: an active region” is met by the prior
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`art relied upon in the grounds. Response, 26-27. To support this assertion, PO
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`5 PO’s Responses in this proceeding and in related IPR2017-01843 also make clear
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`its constructions are driven by attempting to avoid the prior art because PO offers
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`constructions for different terms in each Response, despite those Responses both
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`addressing the same challenged patent and claims. Compare IPR2017-01841
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`Response (construing only the term “active region made of a semiconductor
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`substrate”) with IPR2017-01843 (construing only the term “silicon nitride film”).
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
`
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`adopts language similar to that used in the Petition and during Dr. Shanfield’s
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`deposition, but then proposes interpreting this language in the same manner as its
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`previously rejected construction. Id., 27-28. This unilateral statement by PO does
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`not signal Petitioner’s agreement with the incorrect interpretation that an active
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`region contains only one transistor. There is nothing in the ’501 patent or prior art
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`that prohibits multiple transistors from being formed in an active region, or that
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`requires each transistor to be isolated from any other transistor. Ex. 1027, ¶10.
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`Third, PO cannot reconcile its incorrect interpretation with its own
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`infringement contentions in the co-pending litigation, which identify an alleged
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`“active region” having multiple transistors and which were made of record in this
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`proceeding (over PO’s opposition) months before PO filed its response. As
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`highlighted by PO’s infringement contentions, the alleged “active region” shown
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`in blue contains at least four transistors:
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`Ex. 1021, 32. Ex. 1027, ¶11.
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`PO’s inconsistent positions on an “active region” infect its arguments
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`throughout its Response. For example, PO argues that the MISFET must “include”
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`the entirety of the active region. Response, 16. This is simply another indirect
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`way of PO rearguing its rejected construction requiring a one-to-one
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`correspondence of active regions-to-transistors and is directly contradicted by PO’s
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`own district court infringement allegations, which allege the opposite. Patent
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`Owner cannot have it both ways. Ex. 1027, ¶12.
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`Fourth, as recognized by the Board, the Petition and the semiconductor
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`textbooks cited in the Petition consistently recognize the “active region” as the
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`region where transistors are formed. Ex. 1027, ¶13. For example:
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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` “The active regions are found between the shallow trench isolation regions
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`(STI). (See Rabaey at 42-43 (Ex-1010).) The active regions are where the
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`transistors are formed. (Id. at 42.)” Petition, 7; Plummer at 86 (Ex-1008).
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` “[T]he manufacturing process for a MISFET ‘starts with the definition of the
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`active regions—these are the regions where transistors will be
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`constructed.’” Petition, 26 (quoting Ex-1010); see also Petition, 8; DI, 8-9.
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`And indeed, a region bounded by isolation regions where transistors are
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`formed is precisely what is shown in Igarashi, as identified by the Petition:
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` “A POSITA would have understood that Igarashi discloses an active region
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`made of the semiconductor substrate 1 because Igarashi discloses: ‘First, an
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`insulating film for isolating elements is formed on a silicon semiconductor
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`substrate 1. Element isolation is performed using methods such as the
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`LOCOS method or the trench method. Thereafter, ion implantation is
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`performed to the active element region for forming the well and controlling
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`the threshold value.’ (Igarashi at [0068] (Ex-1004).)” Petition, 25.
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` “The use of the ‘trench method’ confirms the ‘active element region’ (active
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`region) is made of the semiconductor substrate 1 because according to the
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`trench method the active region is formed in the substrate and defined by the
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`STI regions.” Petition, 26. Ex. 1027, ¶13.
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`Fifth, PO’s reliance on the exemplary embodiments of the ’501 to argue that
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`“[e]very embodiment in the specification includes a single transistor in an active
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`region bounded by isolation regions” does not compel an interpretation of “active
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`region” having only a single transistor. Response, 28-29, 74. For example, where
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`PO cites to the description of Figure 1 (Response, 28, citing Ex. 1001, 3:21-23),
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`that figure shows only “a cross-sectional view illustrating a semiconductor device
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`according to a first embodiment of the present invention.” Ex. 1001, 3:19-21.
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`Where PO cites to various descriptions of manufacturing process steps (e.g.,
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`Response, 28, citing Ex. 1001, 6:22-26, 9:38-39, 10:53-54, 12:25-28), those steps
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`are directed to “the first embodiment,” “modified example[s]” of the first
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`embodiment, or “a second embodiment.” Ex. 1001, 6:18-21, 9:32-35, 10:48-50,
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`12:21-24. Critically, nothing in the specification or claims of the ’501 patent states
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`that the “active region” can only contain a single transistor. Ex. 1027, ¶14.
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`Moreover, the cited figures in the ’501 patent only show a “cross-sectional”
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`(i.e., from the side) view of the example embodiments (the “plane view” of Figure
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`9 is directed to a different, “third embodiment”). Ex. 1001, 2:47-3:7, Figs. 1-8; see
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`also, Ex. 1024, 79:6-80:15 (confirming that “the views of the first embodiment and
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`its modifications are all cross-sectional views,” which “merely show[] what can be
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`viewed in one cutaway.”). As Dr. Shanfield confirms, these cross-sectional
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`perspectives do not foreclose on the existence of additional transistors within the
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`active regions, placed in the axis directed into and out from the page. Thus, even
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`the exemplary embodiments cited by PO may have multiple transistors in the
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`active region. Ex. 1027, ¶15.
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`Because neither the specification nor the claims of the ’501 patent limit the
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`“active region” to a one-to-one correspondence of active regions-to-transistors, PO
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`cannot rely on its presumptions about certain exemplary embodiments depicted in
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`the drawings to support a narrowing interpretation of the “active region.” Ex.
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`1027, ¶15; see Skedco, Inc. v. Strategic Operations, Inc., 685 F. App'x 956, 960
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`(Fed. Cir. 2017) citing MBO Labs., Inc. v. Becton, Dickinson & Co., 474 F.3d
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`1323, 1333 (Fed. Cir. 2007) (“[A] claim is not limited to inventions looking like
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`those in the drawings.”)
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`Finally, PO’s interpretation of an “active region” does not make technical
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`sense. For example, all functional MOSFET transistors have an active region and
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`Dr. Glew cites no evidence to the contrary. As Dr. Shanfield explains, a POSITA
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`would understand that the active region is electrically isolated from other active
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`regions with isolation regions. Nothing about this understanding precludes
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`multiple transistors from being formed within the active region. In the case where
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`two transistors share a drain, electrical isolation is not required between the
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
`
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`transistors and both transistors are formed within the same active region. Ex.
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`1027, ¶16.
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`Dr. Shanfield also identifies additional examples in the prior art that rebut
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`PO’s technically flawed position and confirm the understanding that more than one
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`transistor can exist in an active region, as set forth in the Petition. For example,
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`U.S. Patent No. 5,389,810 to Agata (“Agata”) describes a “plurality of pairs of
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`MOSFETs 10 [] arranged in a row in the active region 2.” Ex. 1025, 5:18-19.
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`First MOSFET 10a and second MOSFET 10b make up an example pair which, as
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`shown, share “source region 11.” Id., 5:37-38. Critically, both MOSFET 10a and
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`MOSFET 10b (annotated below in green) are formed and exist in the same “active
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`region 2,” (annotated below in blue) as shown in the annotated Figure 2 of Agata
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`below. Id., 5:33-37.
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`Id., Figure 2; Ex. 1027, ¶17.
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`Dr. Shanfield also explains that isolation regions are designed to isolate one
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`active region from another active region, not each transistor from every other
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`transistor. That is, the isolation regions do not necessitate a one-to-one
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`correspondence of active regions-to-transistors as PO asserts. For example, when
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`observing a plan view laying out a configuration of semiconductor devices, it
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`becomes evident that an active region can include more than one transistor. U.S.
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`Patent No. 8,618,607 to Rashed et al. (“Rashed”) illustrates such a plan view,
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`describing a device that “includes a continuous active region defined in a
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`semiconducting substrate, first and second transistors formed in and above the
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`continuous active region.” Ex. 1026, Abstract. Rashed even acknowledges that
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`the prior art teaches the formation of multiple devices in a single active region, as
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`shown for example in its Figure 1. Ex. 1026, 1:55-58 (“A plurality of PFET
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`devices 20P1-2 are formed in and above the active region 12PA and a plurality of
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`PFET devices 20P3-4 are formed in and above the active region 12PB.”). Ex.
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`1027, ¶18.
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`
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`Dr. Glew states that semiconductor devices have been made without
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`isolation regions and cites a single patent from the 1980’s stating that a retrograde
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`doping profile may be used “with or without trench dielectric isolation structures.”
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`Ex. 2007, ¶¶112-113, citing Ex. 2014 at 5:41-47. These examples are misleading.
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`First, even transistors that do not use isolation regions such as STI still have active
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`regions—otherwise, the transistors would simply not function. The absence of an
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`isolation region does not signify the absence of an active region. Second, by the
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`time of the alleged invention in 2003, virtually all transistors included isolation
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`regions. A POSITA at the time of the alleged invention would not have
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`understood Igarashi to be implemented in a manner that omitted isolation regions
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`or structures (such as STI) because: (i) the transistors commonly used by then were
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`too small for spacing alone to be a functional alternative to isolation regions or
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`structures (such as STI); and (ii) Igarashi expressly discloses the use of isolation
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`regions and such isolation regions would have been obvious in view of Woerlee.
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`Ex. 1027, ¶19; Petition, 25-27; Ex. 1024, 111:18-25 (admitting that using spacing
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`rather than isolation “would not be a typical solution” for memory cells in the 2003
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`timeframe).
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`Accordingly, PO’s interpretation of an “active region” is inappropriately
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`narrow, forecloses substantial portions of the technical field, and is purely designed
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`to escape the overwhelming prior art. Ex. 1027, ¶20.
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`III.
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`IGARASHI AND WOERLEE DISCLOSE THE CLAIMED “ACTIVE
`REGION”
`PO again incorrectly argues that the Fifth Embodiment described in Igarashi,
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`itself, does not teach STI regions forming an active region. Response, 37. The
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`U.S. Patent 7,893,501
`IPR2017-01841
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`Board has already rejected this argument: “[W]e find it is clear from Igarashi that
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`the disclosure of ‘active element region[s]’ discussed in paragraph 68 with respect
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`to the ‘First Embodiment’ is equally applicable to the ‘Fifth Embodiment’ upon
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`which Petitioner primarily relies.” DI, 18-20. Ex. 1027, ¶21.
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`A.
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`Patent Owner’s Imagined Inherency Argument Mischaracterizes Dr.
`Shanfield’s testimony
`PO attempts to mischaracterize Dr. Shanfield’s testimony, claiming that he
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`has advanced a “new” inherency argument by suggesting that isolation regions
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`were present in that embodiment because they were necessary for the device to
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`work. Response, 12. Ex. 1027, ¶22. PO’s strawman argument should be rejected.
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`The Response asserts that “[Dr.] Shanfield testified that every embodiment
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`must be isolated using LOCOS or the trench method to ‘have a functional
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`integrated circuit.’ Ex.-2009, 98:10-13.” Response, 45. But in the context of the
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`surrounding testimony omitted from the Response (bracketed below), it is clear
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`that Dr. Shanfield’s testimony is directed to the understanding of one of ordinary
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`skill in the art when reading Igarashi and not inherency:
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`“[Someone of skill in the art, reading this, would understand that what
`Igarashi means is, I'm going to describe the method for manufacturing
`the semiconductor device of the first embodiment. …. Clearly isolation
`is required in any embodiment.
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`U.S. Patent 7,893,501
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`Petitioner’s Reply to Patent Owner’s Response
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`And so, for example, it says ‘Element isolation is performed using
`methods such as LOCOS or trench method.’]
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`“A person of skill in the art would understand that that applies to all
`the embodiments, because you wouldn't have a functional integrated
`circuit without it.”
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`Ex. 2009, 97:19-98:13; see also id., 99:6-21 (“Someone of skill in the art will
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`understand there has to be an isolation. LOCOS and the trench method were the
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`alternatives at the time, and, of course, [Igarashi’s] got to be referring to every
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`embodiment. It couldn’t be interpreted any other way.”). Ex. 1027, ¶23.
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`PO also cites the following testimony to support its own invented inherency
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`argument: “And that’s understood to apply to all the embodiments. There’s no way
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`electrically it can be not isolated.” Response, 45, citing Ex. 2009, 100:24-101:10
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`(emphasis by PO). But again, when Dr. Shanfield’s testimony is taken in context,
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`his response is clearly intended only to correct PO’s misinterpretation of Igarashi:
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`[No, but it -- that's -- if you're attempting to imply that it doesn't have
`isolation, then it's a misreading of the end of paragraph 68. It says
`‘Element isolation is performed using methods such as LOCOS or the
`trench method.’] And that’s understood to apply to all the
`embodiments. There’s no way electrically it can be not isolated.
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`Ex. 2009, 101:3-7 (omitted testimony in brackets). Ex. 1027, ¶24.
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`In other words, and consistent with both the Petition and his first declaration,
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`Dr. Shanfield is confirming in this testimony that a person of ordinary skill, when
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`reading Igarashi, would have understood that the disclosure of the features in
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`Igarashi that are common to different illustrations are applicable to the
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`embodiment shown in Figure 12 because the same reference numerals are used to
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`describe common features of Igarashi’s disclosure. Ex. 1027, ¶24.
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`Moreover, inherency is irrelevant in this case because—putting aside the fact
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`that neither Petitioner nor Dr. Shanfield has ever raised an inherency argument in
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`this case—Igarashi expressly discloses an active region. Petition, 25, citing Ex.
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`1004, [0068] (discussing the formation of the “active element region”). Ex. 1027,
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`¶25.
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`The Petition is also clear that a “POSITA would have understood that the
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`disclosure of the features in Igarashi common to different illustrations are
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`applicable to the embodiment shown in Figure 12 because the same reference
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`numerals are used to describe common features of Igarashi’s disclosure.” Petition,
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`22. For example, “semiconductor substrate 1” where the active region is formed is
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`a common feature between Figure 1 (Embodiment 1) and Figure 12 (Embodiment
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`5). In fact, Dr. Glew admitted that he used the same approach to interpret the ’501
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`patent, admitting that he based his assessment of the ’501 patent’s first
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`Petitioner’s Reply to Patent Owner’s Response
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`embodiment on the ’501 patent’s third embodiment because “it uses the same Item
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`No. 2, which indicates to me that it is going to be substantially similar to the other
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`uses of Item 2.” Ex. 1024, 81:8-24. This uniform numbering scheme for common
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`features (which also includes elements numbered 2-6) is undeniably evident when
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`the two figures in Igarashi are viewed side by side. Ex. 1027, ¶26.
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`Figures 1 and 12 of Igarashi showing a uniform numbering scheme for common
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`
`
`
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`features (Ex. 1004)
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`This same reasoning applies to common features, like the isolation regions, even if
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`they are not specifically shown in the figures. As noted in the Petition, where
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`features differ between figures, the differences are described in the disclosure of
`
`Igarashi. Petition, 22-23, citing Ex. 1004, [0117] and Ex. 1002, ¶60; see also, Ex.
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`1024, 111:13-112:3 (confirming that a POSITA at the relevant time would not rely
`
`on spacing the devices in Figure 12 of Igarashi so far apart that isolation would not
`
`be needed). Ex. 1027, ¶26.
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`- 18 -
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
`
`
`Moreover, the Petition showed that Igarashi’s isolation region teachings
`
`were applicable to its Figure 12 embodiment. Specifically, the Petition cites
`
`Figure 12, which shows the “semiconductor substrate 1.” Petition, 25. Then, the
`
`Petition explains that a POSITA would have understood that the semiconductor
`
`substrate 1 in Fig. 12 has an active region because Igarashi expressly discloses an
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`“active element region” made of the semiconductor substrate 1. Petition 25-26,
`
`citing Ex. 1004, [0068]; Ex. 1002, ¶66; Ex. 1010, 42-43. Ex. 1027, ¶27.
`
`Accordingly, both the Petition and Dr. Shanfield’s testimony have been clear
`
`and consistent throughout this proceeding: Igarashi discloses the “active region” of
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`the challenged claims in connection with its Fifth Embodiment. Moreover, as
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`discussed below in Section III.D, the Petition also demonstrated it would have
`
`been obvious to form the active region disclosed in Igarashi in semiconductor
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`substrate 1 of Igarshi’s Fifth Embodiment in view of the teachings of Woerlee. Ex.
`
`1027, ¶28.
`
`B.
`Igarashi Discloses a MISFET that Includes an “Active Region”
`A person of ordinary skill would have viewed the region between the two
`
`STI in Igarashi where the two transistors are formed as an “active region” formed
`
`between those two STI. As noted in the Petition: “The use of the ‘trench method’
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`confirms the ‘active element region’ (active region) is made of the semiconductor
`
`substrate 1 because according to the trench method the active region is formed in
`- 19 -
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
`
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`the substrate and defined by the STI regions. Petition, 25-26, citing Ex, 1010, 42-
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`43 (explaining that the manufacturing process for a MISFET “starts with the
`
`definition of the active regions—these are the regions where transistors will be
`
`constructed. All other areas of the die will be covered with a thick layer of silicon
`
`dioxide (SiO2) called the field oxide. This oxide acts as the insulator between
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`neighboring devices, and it is either grown (as in the process of Figure 2-1) or
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`deposited in etched trenches (Figure 2-2)—hence, the name trench insulation.”)
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`As discussed in Section II above with respect to Agata and Rashed (and PO’s
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`district court infringement contentions), it is visibly clear that Igarashi discloses the
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`claimed “active region” of the ’501 patent. Ex. 1027, ¶29.
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`As discussed below, Dr. Shanfield was asked during his deposition whether
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`this active region would be considered one active region or two active regions.
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`Under either view, Igarashi’s disclosure meets the claim limitations because the
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`MISFETs in either case include an active region bounded by STI. Under the first,
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`each MISFET includes an active region because each transistor is formed in the
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`active region between the STI. There is nothing that precludes multiple transistors
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`from being formed in the active region, nor does the claim require that each
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`transistor have its own active region that is separated from other active regions by
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`isolation regions. See Section II, above; Ex. 1025. Indeed, Dr. Glew admitted that
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`- 20 -
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`the term “includes” in claim 1 means “that it has at least these features.” Ex. 1024,
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`94:20-95:7. Under the second, each transistor includes an active region because
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`there are two transistors and two active regions. Ex. 1027, ¶¶30-31.
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`PO’s (and Dr. Glew’s) arguments against Igarashi’s “active region” are
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`internally inconsistent. For example, in its Response, PO first argues that the
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`entire region bounded by isolation regions is not the formation region for any
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`transistors. Response, 17-18. Yet, in the very next sentence, PO concedes that this
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`region is the formation region for at least two transistors. Response, 18 (“It is
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`undisputed that there are at least two transistors in Igarashi’s Fig. 12.”). Ex. 1027,
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`¶32.
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`PO’s attempt to argue that Igarashi’s Figure 12 embodiment somehow does
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`not have an active region because it is a memory device also fails. Response, 33-
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`34. When asked to provide examples of known devices having “active regions,”
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`Dr. Glew admitted that there were various types of devices—including “logic and
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`memory devices”—that would have “active regions.” Ex. 1024, 97:7-18. Ex.
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`1027, ¶33.
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`And, as Dr. Glew confirmed in his declaration, Igarashi’s Fifth Embodiment
`
`shown in Figure 12 “comprises a portion of a memory cell”—precisely the type of
`
`- 21 -
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
`
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`device that Dr. Glew would expect to have an “active region.” Ex. 2007, ¶¶91-92;
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`see also, Ex. 1024, 110:23-111:4. Ex. 1027, ¶33.
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`C.
`
`Patent Owner’s Attacks on Dr. Shanfield’s Testimony are Purely a
`Distraction
`PO desperately attacks Dr. Shanfield in its Response for allegedly not
`
`answering the question of whether Igarashi shows one active region or two active
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`regions. Response, 13-14. However, Dr. Shanfield repeatedly tried to explain how
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`this was not a distinction relevant to the challenged claims or his analysis. When
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`PO persisted in trying to get Dr. Shanfield to say it was one active region or two,
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`Dr. Shanfield testified truthfully that this was not a question that made sense
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`- 22 -
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`U.S. Patent 7,893,501
`IPR2017-01841
`Petitioner’s Reply to Patent Owner’s Response
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`technically.6 Dr. Shanfield was not unable or unwilling to answer the question. To
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`the contrary, he repeatedly and patiently answered PO’s questions over two full
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`days of deposition and even stayed in deposition for over an hour beyond PO’s
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`allotted seven hours on the second day. Ex. 1027, ¶34. The trouble for PO is not
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`that Dr. Shanfield did not provide an answer—it is that PO just did not like the
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`answer he gave.
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`For example, in the very passage PO cites to support Dr. Shanfield’s alleged
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`non-answers (PO cites Ex. 2010, 437:23-438:10, omitting lin
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