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`Significance of JEDEC DIMM Module
`Wednesday, September 25, 2002
`
`By: Cecil Ho, CST, Inc.
`
`Significance of JEDEC DIMM Module
`Abstract
`
`Tuesday, April 25, 2017
`
`Previous Next
`
`Non-JEDEC compliance memory modules have been flooding the market resulting in unstable
`computer systems and confusion. System integrators and consumer are easily tempted by the
`short-term cost saving without knowing its long-term consequence. This article investigates the
`design process in JEDEC Raw cards. It highlights the details on proper memory module design.
`Whether it is clock net, stub length, termination resistor, or impedance control, they all involve
`thousands of hours of simulation and engineering. The resulting Gerbers are offered free of charge
`to you. It might make you think differently next time you pick up a memory module.
`
`General
`
`We are seeing DIMM modules with only half of the number of bypass capacitors. We see DIMM
`modules with screened on resistors with value vary 30% across the same board. We see DIMM
`modules made out of 4 layer printed circuit boards instead of 6 layer boards. We see DIMM
`module that has the correct circuitry but fail to work in the computer system. We see deceptive
`memory module manufacturers cut all corners to reduce cost and to gain sales. On the other hand,
`we are frustrated at the many memory modules that do not work properly in our computer system.
`That is when JEDEC, the semiconductor standard setting committee, gets into the play. A unified
`standard on memory modules is needed to make sure every memory module work in every
`computer. With a unified standard, we can therefore, enjoy the benefit of state-of-the-art and at the
`same time attending the lowest price.
`
`Polaris Innovations Ltd. Exhibit 2004
`Kingston v. Polaris, IPR2017-00974
`
`1
`
`

`

`Why is JEDEC Important?
`
`JEDEC is an organization made up of 300 plus member companies from all over the world. They
`consist of memory vendor companies like Micron, Samsung, Infineon, Hynix and Nanya. Memory
`module manufacturers like Kingston, Smart Modular, and Wintec. Connector manufacturers like
`Molex, and Foxconn. Memory user companies like Sun Micro, Silicon Graphics, and HP. Tester
`companies like Tektronix, Agilent and CST. Chipset companies like Nvidia, Via and SIS.
`
`All these companies realize that the only way to have the best price for memory and its associated
`system is to promote one mainstream technology for the entire industry. Therefore, these
`companies get together 4 times a year all into one room with their difference set aside and to
`concentrate on formulating a standard memory that the industry can accept. The result is robust
`design memory devices and modules that will work reliably in the computer systems. This standard
`becomes the minimum requirement for the memory market. It is recognized by all OEM computer
`manufacturers and is supported by the entire industry.
`
`Member companies worked together on specification, simulation, prototyping, example design, test
`parameters and system validations. A guideline is set down so that all JEDEC compatible
`memories will be functionally inter-changeable with similar performances
`
`Developing a JEDEC Memory Specification
`
`JEDEC has been looking ahead for the needs of the semiconductor memory industry in advance
`of many years. It started the work on DDR memory back in 1997. Through its effort, DDR is now
`the mainstream memory in the computer industry. JEDEC has just now completed the specification
`for DDR-II which should fill the market by 2005. The next task is DDR-III which is expected to
`materialize by 2007
`
`JEDEC’s design procedure starts out with series of survey to users and semiconductor vendors.
`The user companies are asked what they would want while vendor companies are asked on what
`they can practically produced economically not now but several years down the line. The user
`companies have to look at the memory bandwidth required to support their applications down the
`line. Whether it is video streaming, 4G handset or fiber-to-home networking, system companies
`have to forecast their memory requirements in speed, feature, and in density. The semiconductor
`vendors are asked to look at their process technology down the line. The challenge is placed
`before them for tighter line width technologies. Memory cores working at 2.5V power supply today
`will have to go to 1.8V and 1.2V to gain the extra speed and bandwidth in a few years.
`
`One of the major tasks for JEDEC is to assign pin-out for memory device and memory modules.
`Whether it is for the memory chip or the memory module, pin-out assignment is no small task. Trial
`layouts of the motherboard and the DIMM have to be done to find the optimum routing. Special
`attention is applied to minimize lead inductance and to accommodate a universal pin-out for all
`different die sizes in the future. Not to mention mechanical support and reliability standards
`
`While users are eager to use memories that would give them the most timing margin workable
`timing tolerance) for systems, vendors are fighting for uniform specifications that every one can
`
`Polaris Innovations Ltd. Exhibit 2004
`Kingston v. Polaris, IPR2017-00974
`
`2
`
`

`

`agree and produce. Either it is the hold time, latency, or clock duty cycle tolerance, semiconductor
`vendors want to achieve maximum yield with their process. JEDEC, the standardization committee
`gets to be the mediator when "wants" and "needs" comes into conflict.
`
`Simulation Plays a Key Role in JEDEC Memory Design
`
`In digital circuit design, we used to say, "It’s only ones and zeros, will work either way you hook it
`up". Well, in a 333MHz memory circuit, the statement is no longer true. Every line segment (stub)
`becomes a transmission line that can get echoes back to distort the original waveform. Therefore,
`a transmission line model must be simulated and examined for echoes and waveform distortions.
`Series resistor and termination resistors must be examined for the best value and performance.
`That is why you see stub lengths on a memory DIMM fully defined in the JEDEC design
`specifications.
`
`Before the engineer has a chance to build the system, he must also figure out how much timing
`margin his system has before hand. He takes the worst cases tolerance on hold time, clock
`jittering, and a lot of other factors into the calculation and comes up with an "eye pattern"
`simulation that tells how much margin the system has when incorporated with the memories.
`
`After all these simulation and calculations, the engineer might decide on one particular impedance
`value for the PC board to give best performance. He has, therefore, layout his PC board for a fixed
`impedance (for example 60 ohm). He then use line width, dielectric, and layer stack specification
`to set his PCB impedance. Formulae and application software are available to do these
`calculations. The result is constant and stable impedance on the PCB to avoid signal distortion
`
`Polaris Innovations Ltd. Exhibit 2004
`Kingston v. Polaris, IPR2017-00974
`
`3
`
`

`

`and to work at the highest frequency possible.
`
`Engineers also like to add measurement coupons (blank lines) on their PC board for practical
`measurement of the actual impedance. In such case, a TDR (Termination Dependent Return Loss)
`measurement is taken at the PC board manufacturing to determine the accuracy of the board
`impedance. The impedance control can also be examined with a cross-section of the PC board
`measured under a microscope.
`
`Memory Module Prototyping
`
`Polaris Innovations Ltd. Exhibit 2004
`Kingston v. Polaris, IPR2017-00974
`
`4
`
`

`

`JEDEC members provide a large number of example designs of PC board for memory modules. It
`is usually called the Raw Cards as they are supplied in the common PCB layout format call the
`Gerber format. Any engineer can take this "Gerber" file to a PCB fabrication shop and have a PCB
`made.
`
`These "Raw Cards", contributed by the JEDEC member companies are simulated, analyzed, and
`carefully designed to provide robust operations in the computer. These Gerber files are generally
`open for downloading to everybody in the industry
`
`Before these Gerbers are released, actual memory modules are usually built and verified against
`the design and simulation results. Any disagreement are studied and corrected before final
`release.
`
`Memory Module System Validation
`
`JEDEC members put these Raw Cards to test in different motherboards to verify their functionality
`in the system. The motherboard memory sockets are usually fully populated. Functional test is
`performed at 4 temperature/voltage extreme corners (low and high) to uncover any problem in the
`actual operational environment. Clock arrival at the memory chip is also checked for skews and
`delays with the help of a JEDEC Standard Clock Reference Board.
`
`JEDEC Standard Clock Reference Board
`
`JEDEC members have determined that if common design modules are to work with every
`motherboard, the module clock skew is a very critical factor. Therefore, JEDEC has designed a
`Clock Reference Board to be used for an industry wide uniform calibration. Many versions of the
`Clock Reference Boards are made over time for the different generations of memory technologies.
`There is the 133MHz CRB for 133Mhz SDRAM modules. There are also CRB for the PC2100
`DIMM as well as a new version for the PC2700 DIMM
`
`The Clock Reference Board is a standard clock generator split into different clock paths on the
`CRB. One path goes to a standard clock termination load while the other clock paths end into
`DRAM chips. This provides the engineer with a mechanism to measure and to calibrate the clock
`arrival
`time to the chips on the module with an oscilloscope. Any unwanted skew can, therefore, be
`corrected by adding capacitors to the feedback of the clock PLL (phase lock loop).
`
`These CRB’s are manufactured in one batch of PCB and one batch of uniform component to
`minimize the variations. The result is the best way to unify the industry on clock arrival time and
`thus the assurance of modules will work in different systems.
`
`Proper Memory Module Manufacturing, Meeting JEDEC Standard
`
`A well design JEDEC module cannot realize its full potential if it is not manufactured properly. As
`the DIMM operational frequency goes up, so as the need for tighter manufacturing process. A
`good memory module manufacturer usually have a solder paste screening machine that gives him
`
`Polaris Innovations Ltd. Exhibit 2004
`Kingston v. Polaris, IPR2017-00974
`
`5
`
`

`

`good control on the amount of solder paste dispensed. The process engineer is aware of the
`importance of freshness and the quality of his soldering paste. A good module manufacturer also
`has a precision Chip-Mounter (Pick-n-Place) machine for automatic placement of his DRAM chips
`and associated components. The loaded boards are then placed into a reflow oven to complete
`the solder joints.
`
`Proper DIMM Module Testing, Key to Success
`
`Module manufacturers also need testers to test their module for assembly problems and process
`damages. There are tester companies among JEDEC members that design testers based on
`JEDEC memory module specifications. As a result, the JEDEC quality can be pass-on to the final
`user.
`
`There are basically two classes of memory module testers that are made for JEDEC DIMM testing.
`The ATE (automatic test equipment) class tester allows virtually any arbitrary waveform generated
`to simulate almost any conditions that the memory modules can encounter in the computer
`system. These machines are infinitely flexible and programmable. They are good for production as
`well as fault analysis. The only drawback is the cost that can run into millions of US dollars.
`
`Another type of memory module tester straightly made for memory module production test. It takes
`the assumption that the DRAMs have been tested in the semiconductor manufacturing process.
`Therefore, only functional test have to be applied to catch assembly errors and process damages
`during the module manufacturing process. This class of tester is most popular in the module
`manufacturing industry.
`
`On top of that, a good test process control record is needed to satisfy ISO9000 requirements.
`Robotic mechanical handlers are usually used with memory module testers to realize good test
`process control. Robotic test handlers would separate the good module from the bad module
`automatically and confidently. It would also keep an account and record of the module faults
`detected. It can also trace and track modules to the manufacturing date, DRAM batch, and the
`machine it was tested on even months after the DIMM has left the factory.
`
`Polaris Innovations Ltd. Exhibit 2004
`Kingston v. Polaris, IPR2017-00974
`
`6
`
`

`

`Conclusion
`
`In summary, good working memory modules have been designed for you by JEDEC, the industry
`standard setting committee. It is free for your access. Through JEDEC, unified DRAM and DIMM
`specifications have been generated and are available to memory and memory module
`manufacturers. All you have to do is to follow JEDEC guideline in choosing memory modules and
`not fall for the cost cutters. You will be able to build your good computer with stable and reliable
`memories that would last for a long long time.
`
`By: Cecil Ho, CST Inc
`Copyright © 2002 CST, Inc. All Rights Reserved
`
`Email Article
`
`Printer Format
`
`Previous Next
`
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`Copyright © 1994 - 2017 CST, Inc. All Rights Reserved
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`Polaris Innovations Ltd. Exhibit 2004
`Kingston v. Polaris, IPR2017-00974
`
`7
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