(12) United States Patent
`Hardee
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,195,302 B1
`Feb. 27, 2001
`
`USOO6195302B1
`
`(54) DUAL SLOPE SENSE CLOCK GENERATOR
`
`(75)
`
`Inventor: Kim C. Hardee, Colorado Springs, CO
`(Us)
`
`3/1997 Wilson et al. .
`5,614,856
`5,638,333 * 6/1997 Lee
`5,666,074
`9/1997 Chun -
`5,822,262
`10/1998 Hasimoto et al. .
`
`365/205
`
`(73) Assignee:
`
`United Memories, Inc., Colorado
`Springs, CO (US)
`
`FOREIGN PATENT DOCUMENTS
`
`WO 98/25272
`
`6/1998 (W0) .
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`Pawnt is extended or adjusted under 35
`U-S-C- 154(k)) by 0 days-
`
`OTHER PUBLICATIONS
`Changhyun, Kim, “Basic Dram Operation”, Feb. 1998,
`Samsung Electronics.
`
`(21) Appl. No.: 09/492,726
`(22) Filed:
`
`. 27 2000
`Jan
`’
`Related US. Application Data
`(60) ligg‘gisional application No. 60/118,737, ?led on Feb. 5,
`
`* cited by examiner
`
`Primary Examiner—Huan Hoang
`(74) Attorney, Agent, or Firm—Stuart T. Langley; William
`J: Kublda; Hogan & Hartson LLP
`(57)
`ABSTRACT
`
`(51) Int CL?
`(52) US. Cl.
`
`(58) Field of Search
`
`’
`
`GHC 7/00
`365/194
`327/51’
`’
`365/205 207
`365/149 194 327/5’1 57’
`’
`’
`’
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`
`
`900152 9590092 1400661
`
`
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`A memory device including a plurality of sense ampli?ers
`distributed about an integrated circuit chip, Where each sense
`ampli?er has a poWer node for receiving current. A conduc
`tor couples the poWer nodes of a number of sense ampli?ers
`together. A loW-impedance poWer supply conductor extends
`to each sense ampli?er and a local drive transistor is
`provided for each sense ampli?er. A timer unit generates an
`output signal controlling the local drive transistors. A ?rst
`component Within the timer unit causes the output to change
`from a ?rst logic level toWards a second logic level at a ?rst
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`Page 1 of 10
`
` SAMSUNG EXHIBIT 1001
`
`

`
`U.S. Patent
`
`Feb. 27, 2001
`
`4f01LI06hS
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`US 6,195,302 B1
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`Page 2 of 10
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`

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`U.S. Patent
`
`‘CB
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`10027:2b.
`
`Sheet 2 of 4
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`US 6,195,302 B1
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`Page 3 of 10
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`

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`U.S. Patent
`
`Feb. 27, 2001
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`Page 4 of 10
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`

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`U.S. Patent
`
`Feb. 27, 2001
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`Sheet 4 0f 4
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`Page 5 of 10
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`

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`US 6,195,302 B1
`
`1
`DUAL SLOPE SENSE CLOCK GENERATOR
`
`This application claims the bene?t of Provisional No.
`60/118,737 ?led Feb. 5, 1999.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates, in general, to integrated
`circuits and, more particularly, to sense ampli?ers in inte
`grated circuit memory devices.
`2. Relevant Background
`Semiconductor memory devices include sense ampli?ers
`to sense Weak signal levels from storage capacitors and
`amplify those Weak signals to levels suf?cient to drive other
`circuitry. Similar devices are used in other integrated circuit
`devices that sense, hold, and amplify signal levels. In a
`typical dynamic random access memory (DRAM) circuit, a
`data bit is stored as charge in a storage capacitor. A number
`of these storage capacitors are served by a single sense
`ampli?er. During reading, Writing, and refresh operations
`appropriate addressing signals are applied to couple one of
`the capacitors through a bit line to a latch node of the sense
`ampli?er. Before accessing one of the capacitors, the bit
`lines are equalized to a selected precharge voltage during a
`precharge operation. The selected precharge voltage is usu
`ally a voltage midWay betWeen logic high level and a logic
`loW level.
`When an address-selected capacitor is coupled to one of
`the bit lines feeding into a sense ampli?er the charge stored
`in the capacitor alters the signal on the bit line moving it
`incrementally toWards either a logic high or a logic loW
`level. Because it is desirable to make the storage capacitor
`as small as possible, the bit line may only move a feW
`hundred millivolts or less from the equalization level. The
`sense ampli?er serves to amplify this small signal level to
`drive the bit line to either a logic high or logic loW voltage
`level depending on the direction in Which the bit line moved
`With respect to the equalization level.
`Sense ampli?ers typically comprise a latch circuit formed,
`for eXample, by a pair of cross-coupled high gain inverters.
`Atypical latch circuit has tWo latch nodes that each serve as
`a differential input coupled to sense a signal on the bit line
`during sensing to drive the bit line to the logic levels. It is
`desirable that sense ampli?ers accurately sense the bit line
`signal and quickly set the latch outputs. During read
`operations, each latch output is coupled to a data input/
`output (I/O) line by a pass transistor as soon as the latched
`output is available. To reduce access time, it is desirable to
`activate the pass transistor as soon as possible after the latch
`output is stable. Also, it is desirable to make the pass
`transistor relatively large to couple the latched signal to the
`data line quickly and With little signal loss. HoWever, to use
`a large pass transistor the latch must be strong in order to
`hold the latched signal When coupled to the parasitic load
`presented by the data lines.
`The latches Within the sense ampli?ers typically comprise
`P-channel ?eld effect transistors (FETs) coupled to a posi
`tive poWer supply such as VDD by a P-channel FET driver
`sWitch, also referred to as a “high-side” driver. Similarly,
`N-channel FETs in the latches are coupled to a relatively
`negative poWer supply (such as V55 or ground) using an
`N-channel driver sWitch, also referred to as a “loW-side”
`driver. For convenience, the latch poWer supply nodes are
`designated herein as an LN node (i.e., a node coupling the
`loW-side driver sWitch to the N-channel FET devices Within
`the latch) and an LP node (i.e., a node coupling the
`P-channel FET devices Within the latch to the high-side
`driver switch).
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`In a standby or precharge mode the driver sWitches are
`turned off so that the latch lacks suf?cient poWer to drive a
`signal on the latch output nodes. In this standby mode, the
`latch input nodes folloW the signal to be sensed. To read data
`from the memory cell, the driver transistors are turned on
`thereby enabling the latch to amplify the sensed signal on the
`bit lines and drive the latch output nodes to appropriate logic
`levels.
`In DRAM devices, for eXample, rapid driver turn-on can
`cause the sense amp to latch to an incorrect state due to the
`effects of capacitance and transistor imbalances Within the
`sense ampli?er. During overly rapid turn on, parasitic cou
`pling through transistors in each sense ampli?er may pull
`both differential latch nodes of the sense ampli?er toWard
`either a logic HIGH or logic LOW depending on Whether
`loWer drive transistors or upper drive transistors turned on
`?rst. Because one of the drive transistors is typically imple
`mented using N-channel devices and the other using
`P-channel devices, it is common that the N-channel side Will
`turn on ?rst. To counter this problem the driver transistors
`are desirably activated sloWly during initial sensing to alloW
`the sense ampli?er to accurately latch the bit line value.
`HoWever, after initial sensing has begun, the sense amps are
`preferably turned on hard to quickly amplify the differential
`voltage on the latch nodes (i.e., the bit lines) to minimize
`access time. This type of sensing is referred to herein as
`“dual-speed” sensing.
`In many DRAM designs, the LN and LP nodes are shared
`among a plurality of sense ampli?ers. These designs alloW
`the driver sWitches to be implemented With large, loW
`impedance sWitches. By loW impedance it is meant that they
`are loW impedance With respect to the transistors in the latch
`itself including pass transistors that couple the latch output
`nodes to the data line. These strong driver sWitches ensure
`that the sense ampli?ers can be turned on hard When
`necessary. Dual-speed sensing is provided by implementing
`the driver sWitch With tWo or more transistors of different
`size. For eXample, a small transistor having high
`on-resistance is activated ?rst to provide the initial sensing.
`After a preselected delay, a larger transistor having loW
`on-resistance is activated to turn the latch devices on hard.
`HoWever, shared drivers result in long LN and LP lines in
`large memory devices such as 64 M, 256 M, and larger
`memory arrays. Parasitic impedance in the long lines results
`in voltage drops or sagging When a high current ?oWs in the
`LN and/or LP lines. An eXample case is illustrated by a
`group of sense ampli?ers sharing LN and LP lines, in Which
`only one sense ampli?er at the end of long LN and LP line
`is trying to sense a “0” and all other sense ampli?ers are
`sensing a “1”. When the sense ampli?ers are simultaneously
`activated, the large number of sense ampli?ers that are
`sensing a logic “1” Will disturb the voltage at distant
`locations on the LN line. Asense ampli?er that is coupled to
`that portion of the LN line Will take longer to sense a logic
`“0”. Hence, the sense ampli?er performance is sensitive to
`the pattern of 1’s and O’s stored in the memory. To accom
`modate this pattern sensitivity, the DRAM must be operated
`using access timing that Will alloW the sloWest sense ampli
`?er to accurately sense and drive the stored value regardless
`of the pattern. It is desirable to minimize pattern sensitivity
`to improve cell access speed.
`To minimize pattern sensitivity, each sense ampli?er may
`be provided With its oWn local driver transistors. In a typical
`memory device the poWer supply busses are distributed
`throughout the chip area. Each sense ampli?er can be
`coupled to a nearby poWer supply bus using short, loW
`impedance interconnect through a local drive transistor.
`
`Page 6 of 10
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`

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`US 6,195,302 B1
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`3
`However, the local drive transistors must be signi?cantly
`smaller than the shared drive transistors. These smaller drive
`transistors limit the sense ampli?er’s ability to drive the data
`I/O line. High switching current in the latch can destabilize
`the sense ampli?er by alloWing the LN and LP nodes to drift
`impermissibly far from the poWer supply bus voltages.
`It is not practical to implement dual slop sensing using the
`dual transistor technique described above in a local drive
`transistor design because of the chip area consumed by tWo
`transistors required for each sense ampli?er. Instead, dual
`speed sensing is provided With local drive sWitches by
`generating control signals to the driver transistors that settle
`temporarily at a level betWeen a logic loW (i.e., V55) and a
`logic high (i.e., VDD). After a predetermined delay time, the
`control signals continue to the full logic levels to turn the
`driver transistors, and so the latch devices, on hard. This type
`of design is described in US. Pat. No. 5,334,890 titled
`“SENSE AMPLIFIER CLOCK DRIVER” issued Aug. 2,
`1994 and incorporated herein by reference. This design
`distributes the driver transistors reducing pattern sensitivity.
`HoWever, to provide suf?ciently stable LN and LP nodes the
`control signals to the local drive transistors must have
`carefully controlled signal levels, timing, and sleW. Hence,
`local driver designs require relatively compleX control cir
`cuitry that increases the overall siZe overhead of the design
`to levels that may be inappropriate for some applications.
`A need remains for a sense ampli?er design and method
`for operating a sense ampli?er that provides dual slope
`sensing and is compatible With large shared driver designs as
`Well as local driver designs that offer pattern insensitivity.
`Moreover, a need eXits for a high speed sense ampli?er that
`can be implemented With simple, compact circuitry for high
`capacity memory designs.
`SUMMARY OF THE INVENTION
`
`10
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`The present invention involves a memory circuit having a
`plurality of sense ampli?ers Where each ampli?er includes a
`poWer node for receiving current from a poWer supply. One
`or more driver sWitches couple each poWer node to a poWer
`supply bus node. The poWer nodes of a plurality of the
`plurality of sense ampli?ers are coupled together to provide
`a shared poWer node. Pass transistors are used to couple
`output nodes of each of the plurality of sense ampli?ers to
`data lines. A sense clock circuit provides a control signal to
`the one or more driver sWitches such that the control signal
`comprises an initial phase With a preselected initial rate of
`voltage change and a ?nal phase With a rate of voltage
`change that is faster than the initial rate of change.
`In another aspect the present invention involves a method
`for operating a memory device by generating a dual slope
`control signal for controlling the operation of sense ampli?er
`driver transistors in an integrated circuit memory device. A
`sense ampli?er drive transistor is provided having a control
`terminal coupled to receive the control signal and having a
`poWer node for supplying current to a preselected number of
`sense ampli?ers. The control signal is placed at a level
`selected to turn off the driver transistors. A signal to be
`sensed is coupled to a latch node of the sense ampli?er and
`charge is supplied from an eXternal poWer supply to the
`sense ampli?er driver transistor through a ?rst impedance.
`After a delay, additional charge is supplied to the sense
`ampli?er driver transistor through a second impedance at a
`second rate.
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 shoWs a group of sense ampli?ers in a memory
`circuit in accordance With the present invention;
`
`65
`
`4
`FIG. 2 illustrates in schematic diagram form a portion of
`a memory device including an embodiment in accordance
`With the present invention;
`FIG. 3 shoWs a timer circuit generating clock signals in
`accordance With the present invention; and
`FIG. 4 illustrates Waveforms resulting for an embodiment
`of the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The present invention involves a memory device having
`a sense ampli?er With LN and LP nodes shared among a
`number of sense ampli?ers. In one embodiment, local drive
`transistors (i.e., drive transistors associated With each sense
`ampli?er) supply current to the shared LN and LP nodes. In
`an alternative embodiment, a single drive transistor is asso
`ciated With each shared LN and LP node and drives current
`to the associated node. A timer circuit generates control or
`clock signals to the control electrodes of the local drive
`sWitches such that the control signal has a ?rst phase With
`sloW rate of change (e.g., dv/dt) and a ?nal phase With higher
`rate of change. It is contemplated that more than tWo phases
`may be used, but it is signi?cant that the initial phase alloW
`for sloW, gentle turn on While the sense ampli?ers are
`sensing the stored signal and the ?nal phase alloWs for rapid
`turn on to increase access speed.
`In accordance With the local drive transistor implemen
`tation of the present invention, the drive transistors are
`distributed so that they are physically and electrically close
`to each sense ampli?er providing improved pattern sensi
`tivity in large memory devices. Also, shared LN and LP
`nodes enable the local drive transistors to operate coopera
`tively in parallel to provide a strong (i.e., loW impedance)
`coupling betWeen the sense ampli?ers and the poWer supply
`nodes thereby enhancing sense ampli?er stability and sens
`ing speed.
`FIG. 1 illustrates a portion of a memory device, shoWn
`generally at 100, in accordance With the present invention.
`A group of sense ampli?ers 101a—101c are shoWn, but more
`or feWer sense ampli?ers may be included in a group of
`sense ampli?ers. Sense ampli?ers 10la—101c include a pair
`of pchannel transistors and a pair of n-channel transistors.
`The gate electrode of one p-channel transistor is coupled to
`the gate electrode of one of the n-channel transistors to form
`a ?rst latch node 102. The gate electrode of the other
`p-channel transistor is coupled to the gate electrode of the
`other n-channel transistor to form a second latch node 103.
`Additional circuitry that couples latch nodes 102 and 103 to
`bit lines and data I/O lines is described in greater detail With
`reference to FIG. 3. FIG. 1 illustrates the present invention
`embodied in a dynamic random access memory (DRAM).
`Other types of memory devices and integrated circuitry can,
`hoWever, make use of the teachings of the present invention.
`Asigni?cant feature in accordance With the present inven
`tion as shoWn in FIG. 1 is that local driver transistors 104
`and 106 are provided for each sense ampli?er 101a—101c,
`but the LN and LP nodes are also shared among a plurality
`of sense ampli?ers 101a—101c. As described in greater detail
`hereinafter, a control signal (LPB) driving transistors 104
`comprises a dual-slope signal. Similarly, a control signal
`(LNB) driving transistors 106 comprises a dual-slope signal.
`The con?guration in accordance With the present invention
`alloWs the local driver transistors 104 and 106 to be small to
`reduce overall chip area. Yet, because local drive transistors
`104 and 106 are coupled in parallel via the shared LN and
`LP nodes, they operate cooperatively to provide suf?cient
`
`Page 7 of 10
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`US 6,195,302 B1
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`5
`drive capacity to stabilize the LN and LP nodes during
`switching. This feature simpli?es the requirements placed
`on the LNB and LNP signals resulting in simpli?ed control
`circuitry (shoWn in FIG. 3).
`FIG. 2 shoWs a single sense ampli?er 101 With associated
`circuitry typical in a DRAM application. Storage capacitors
`201 are selectively coupled to bit lines 202 through access
`sWitches 203 in response to address signals supplied to Word
`lines 204. In FIG. 2, signal lines are labeled With mnemonic
`labels to ease understanding. In general, an “R” suf?X
`indicates a right-side signal line and an “L” suf?X indicates
`a left-side signal line. Complementary signals are identi?ed
`With a “B” (i.e., bar) suf?X indicating that the signal is
`inverted. Word lines are identi?ed as “WL”, bit lines as
`“BIT”, and latch nodes as “LAT ”. Operations described in
`terms of either a left side or right side components are
`readily implemented on the other side in a similar manner.
`Just prior to a read operation, a pair of bit lines 202 such
`as left-side non-inverted bit line labeled BITL and inverting
`bit line BITLB are equaliZed at some voltage betWeen a
`logic high and a logic loW signal. In operation, When one
`Word line 204 (labeled WL) is activated, a selected storage
`capacitor 201 is coupled to a bit line and incrementally
`moves the bit line to a relatively positive or relatively
`negative voltage depending on the stored charge. The terms
`“relatively positive” and “relatively negative” mean relative
`voltage levels With respect to the equalized voltage.
`To access a storage capacitor 201 on the left side, left side
`bit lines BITBL and BITL are coupled to the latch nodes
`LATB and LAT through transistor 206 by activation of the
`isolation left (ISOL) signal line. Similarly, right side bit lines
`BITBR and BITR are coupled to latch nodes LAT B and LAT
`through transistors 207 by activation of the isolation right
`(ISOR) signal line. In typical operation, once the ISOL or
`ISOR signal is set, the appropriate WL is activated to couple
`the storage capacitor 201 to the LAT or LATB node of sense
`amp 101.
`Shortly after the WL signal is activated, the LPB signal is
`driven to a logic loW coupling VCCI to sense amp 101
`through drive transistor 104. Similarly, the LNB signal is
`driven high to couple sense amp 101 to ground or VSS
`through drive transistor 106. As described hereinbefore,
`LPB and LNB signals drive a number of transistors 104 and
`106, respectively. Preferably, LNB and LPB are generated
`by a circuit such as that shoWn in FIG. 3 that generates LNB
`and LBP both as dual slope signals. Once sense amp 101 is
`poWered the signals on LAT and LATB begin to separate
`under the in?uence of sense amp 101. As this separation
`occurs, the rate of change in the LNB and LPB signals (e.g.,
`dv/dt) can increase to drive LAT and LATB quickly to the
`appropriate logic levels. The column select signal, labeled
`YSE in FIG. 2, is activated to couple the LAT and LAT B
`signals to the data line (D) and inverted data line (DB)
`respectively.
`FIG. 3 shoWs in block diagram form a circuit useful in
`generating the dual slope LPB and LNB control signals
`described hereinbefore. As shoWn in FIG. 3, a sense right
`(SENR) or sense left (SENL) signal is applied to logic gate
`301. Logic gate 301 is implemented as a NOR gate in the
`preferred embodiment, although other logic gates or a com
`bination of logic gates may be convenient in other applica
`tions. Logic gate 301 logically combines the SENR and
`SENL signals to form an intermediate sense ampli?er con
`trol signal on node 302.
`In operation, one of the input signals SENR or SENL Will
`go to a logic high When sensing is to begin and then goes to
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`a logic loW during precharge or standby mode. The SENR
`and SENL signals are derived from, for example, the roW
`address strobe (RAS). During standby, When both SENR and
`SENL are loW, the control signal on node 302 is a logic high.
`Soon after either SENR or SENL goes high, the signal on
`node 302 Will transition to a logic loW.
`The signal on node 302 is inverted by inverter 304 and
`applied to the control node of transistor 303. Hence, shortly
`after either SENR or SENL goes high, transistor 303 is
`turned on pulling the LPB signal loW through resister 306.
`Similarly, When the signal on node 302 goes loW, transistor
`313 is turned on pulling the LNB signal high through resistor
`316. Resistor 316 controls the rate of change or dv/dt of
`LNB While resistor 306 controls the dv/dt of LPB.
`After a delay determined by delay element 307, transistor
`308 Will be turned on pulling LPB to ground With a much
`loWer resistance. When transistor 308 is turned on, LPB Will
`fall to the ground voltage With a high dv/dt. Similarly, after
`a delay determined by delay unit 317, transistor 318 Will be
`turned on to pull the LNB signal to VCCI rapidly Without the
`dv/dt limiting effect of resistor 316 described hereinbefore.
`In a typical application, transistor 308 Will be siZed much
`larger than transistor 303 and transistor 318 Will be siZed to
`be much larger than transistor 313. In the particular example,
`the second stage turn on initiated by transistors 308 and 318
`is performed Without any series impedance to limit the rate
`of signal change of LPB and LNB. There Will be parasitic
`impedance in series With transistors 308 and 318, hoWever,
`this parasitic impedance is preferably selected to be much
`less than the impedance provided by resistors 306 and 316.
`Alternatively, resistors 306 and 316 can be eliminated and
`rise time of the ?rst and second stage controlled by relative
`transistor siZes. Also, it should be noted that during the
`second phase turn on With high dv/dt, both the ?rst stage
`transistors 303 and 313 remain on in parallel With transistors
`308 and 318. Hence, even if no resistance Were provided and
`all of transistors 303, 313, 308, and 318 Were similarly siZed,
`the parallel combination of transistors in the second stage
`Will result in higher dv/dt in accordance With the present
`invention. Each of these alternatives is equivalent to the
`speci?c implementation shoWn for purposes of the present
`invention.
`The delayed signal from delay unit 307 is also coupled to
`one of the inputs of logic gate 305. The other input of logic
`gate 305 is coupled to node 302. The output of logic gate 305
`controls transistor 309 to selectively couple VCCI to the
`LPB node. Likewise, node 302 is coupled to one of the
`inputs of logic gate 315, together With the delayed output
`from delay unit 317. The signal on node 302 Will only be a
`logic high When both SENR and SENL are logic loW. Hence,
`during a sense interval logic gate 305 Will be such that its
`output is high maintaining transistor 309 in an off state.
`Logic gate 315 Will be in a state such that its output is a logic
`loW maintaining transistor 319 in an off state. When both
`SENR and SENL go loW, transistors 309 and 319 turn on
`pulling LPB to VCCI and LNB to VSS or ground to
`deactivate sense ampli?er 101 (shoWn in FIG. 1 and FIG. 2).
`FIG. 4 illustrates simulated Wave forms generated by the
`circuit in accordance With the present invention. In FIG. 4,
`the vertical aXis represents signal magnitude in volts While
`the horiZontal aXis represents time. The scale of the hori
`Zontal aXis is in nanoseconds for purposes of understanding,
`hoWever, it should be understood that the Waveforms shoWn
`in FIG. 4 are more important for their relative rise and fall
`times and not for their absolute speed.
`Starting at time 00, the initial standby state or precharge
`state is represented by the Word line signal WLEND being
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`at a logic loW, and the SENL and SENR signals (shown in
`FIG. 3) are loW. As described in reference to FIG. 3, the loW
`SENL and SENR signals pull LPB to VCCI (i.e., logic high)
`and LNB to logic loW. The column select signal YSE is also
`loW isolating LAT and LATB nodes from the data lines D
`and DB. LN and LP are held at an intermediate precharge
`level in the standby state. The sense ampli?er latch nodes
`LAT and LATB are also precharged at a level betWeen logic
`loW and logic high.
`As sensing operation begins at about the time labeled 20
`in FIG. 4, Word line WLEND goes to a logic high to couple
`a selected storage capacitor 201 to a bit line. The isolation
`signals ISOL and ISOR shoWn in FIG. 2 operate in a
`conventional manner and are not illustrated in FIG. 4. As
`shoWn in FIG. 4, Word line WLEND is actually overdriven
`above VCCI to rapidly charge the long Word lines in a
`typical DRAM circuit, although the exact voltage may vary
`from application-to-application.
`Shortly after the Word line is activated, it can be seen that
`at least one of the LAT and LATB nodes begin to differen
`tiate from the precharge level. While both LAT and LATB
`Will eventually separate from the precharge level as they are
`complementary signals, one or the other Will change ?rst
`depending on Which line is coupled to a storage capacitor.
`During this time period, the turn on of sense ampli?er 101
`is critical as overly fast turn on may overdrive the LAT and
`LATB signals producing incorrect results. For example,
`referring to FIG. 1, during overly rapid turn on parasitic
`coupling through the transistors in each sense ampli?er 101b
`may pull both latch nodes 102 and 103 toWard the potential
`of either LN or LP depending on Whether loWer drive
`transistors 106 or upper drive transistors 104 turned on ?rst.
`Such action places the sense ampli?er in an indeterminate or
`metastable state from Which it may not recover the correct
`data value.
`As shoWn in FIG. 4, just before time 25, the LPB signal
`begins to fall at a ?rst dv/dt during a ?rst phase of the sense
`ampli?er turn on. During this initial phase, the LNB signal
`also begins to rise at a ?rst dv/dt. At about time 30, the LAT B
`and LAT signals have suf?ciently separated such that the
`drive transistors (104 and 106 in FIG. 2) can be turned on
`hard. Hence, at this time a second phase of the sense
`ampli?er turn on begins Wherein the dv/dt of the LNB and
`LPB signals is increased to drive the signals rapidly to the
`logic levels.
`As LNB and LPB approach their respective logic levels,
`LN and LP separate from the precharge level thereby turning
`on sense ampli?er 101. As described hereinbefore, LN and
`LP are shared nodes so that each local drive transistor 104
`and 106 actually is coupled to multiple sense ampli?ers. The
`number of drive transistors coupled in parallel by each LN
`and LP node is selected to provide suf?cient combined
`current drive capacity such that the LP and LN nodes do not
`sag or droop outside of their de?ned logic ranges as the
`sense ampli?er latch nodes LAT and LATB are loaded by the
`data lines D and DB during operation. As shoWn in FIG. 4,
`LAT and LATB continue to separate and are driven to the
`appropriate logic levels quickly after LN and LP are acti
`vated.
`Although the invention has been described and illustrated
`With a certain degree of particularity, it is understood that the
`present disclosure has been made only by Way of example,
`and that numerous changes in the combination and arrange
`ment of parts can be resorted to by those skilled in the art
`Without departing from the spirit and scope of the invention,
`as hereinafter claimed. In particular, although the preferred
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`45
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`implementation uses local drive transistors in combination
`With shared LN and LP nodes, it is contemplated that the
`dual-slope clock signal generating component in accordance
`With the present invention can be used With either a shared
`or “lumped” drive transistor or With local drive transistors
`Without shared LN and LP nodes. These and other modi?
`cations in accordance With the present invention are Within
`the scope and spirit of the present invention as hereinafter
`claimed.
`I claim:
`1. A memory device comprising:
`a plurality of sense ampli?ers distributed about an inte
`grated circuit chip, each sense ampli?er having a poWer
`node for receiving current;
`a loW-impedance poWer supply conductor;
`at least one drive transistor having a ?rst current carrying
`electrode coupled to the poWer supply conductor, a
`second current carrying electrode coupled to the poWer
`nodes of a preselected number of the sense ampli?ers,
`and a control electrode;
`a control line coupled to the control electrode;
`a timer unit having an output coupled to the control
`electrode and generating a control signal;
`a ?rst component Within the timer unit causing the control
`signal to change from a ?rst logic level toWards a
`second logic level at a ?rst rate; and
`a second component Within the timer unit causing the
`control signal to change to the second logic level at a
`second rate, Wherein the second rate is greater than the
`?rst rate such that the ?rst component and the second
`component are concurrently activated to cumulatively
`affect the rate of change to the second logic level.
`2. The memory device of claim 1 further comprising a
`conductor coupling the poWer nodes of a number of sense
`ampli?ers.
`3. The memory device of claim 2 Wherein the at least one
`drive transistor is provided for each sense ampli?er.
`4. The memory device of claim 2 Wherein the at least one
`drive transistor comprises a drive transistor that is shared by
`each of the number of sense ampli?ers coupled to the
`conductor.
`5. The memory device of claim 2 Wherein each sense
`ampli?er receives current from more than one drive tran
`sistor.
`6. The memory device of claim 1 further comprising:
`a data line;
`a latch node in the sense ampli?er to hold a signal
`generated by the sense ampli?er; and
`a pass transistor coupled betWeen the latch node and the
`data line.
`7. The memory device of claim 6 Wherein the number of
`poWer nodes coupled together by the conductor is selected
`to provide a combined drive capability suf?cient to drive the
`data line When the pass transistor is turned on