.
`
`United States Patent [191
`Seo
`
`US005140199A
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,140,199
`Aug. 18, 1992
`
`[54] SENSE AMPLIFIER DRIVER FOR MEMORY
`DEVICE HAVING REDUCED POWER
`DISSIPATIQN
`
`0178796 8/1986 Japan ................................. .. 365/205
`0226111 9/ 1988 Japan ..................... ..
`307/603
`0275223 11/1988 Japan ...................... ..
`307/481
`
`[75] Inventor: Seung-mo Seo, Seoul, Rep. of Korea
`[73] Assignee: Samsung Electronics Co., Ltd., Rep.
`of Korea
`1
`[21] Appl. No.: 358,679
`[22] Filed:
`May 30, 1989
`[30]
`Foreign Application Priority Data
`Jul. 11, 1988 [KR] Rep. of Korea .................... .. 88-8607
`
`[51] Int. 01.5 .............................................. .. GllC 7/00
`[52] U.S. Cl. .................................. .. 307/530; 307/263;
`307/592; 307/601; 365/205; 365/233
`[58] Field of Search ............. .. 307/263, 530, 592, 601,
`307/603, 481; 365/194, 205, 233
`
`[56]
`
`References Cited '
`U.S. PATENT DOCUMENTS
`
`3,943,496 3/1976 Padgett et a]. .................... .. 365/233
`4,295,062 10/1981 Mihalich et al. .................. .. 307/290
`4,508,978 4/1985 Reddy ............................... .. 307/482
`4,638,187 l/l987 Boler et al. ....................... .. 307/270
`4,649,295 3/1987
`4,707,626 11/1987
`4,749,882 6/1988
`4,771,195 9/1988
`4,829,199 5/1989
`4,855,623 8/1989
`
`FOREIGN PATENT DOCUMENTS
`
`0156226 9/1983 Japan ................................. .. 307/605
`0070592 4/1985 Japan ................................. .. 365/233
`
`OTHER PUBLICATIONS
`IBM Tech. Disc. Bu1t.; Chakravarti et al.; High Gain
`Sense Ampli?er; Dec. 1977; p. 206.
`Wong et a1.; Memory Techniques-A 45ns Fully Static
`16K MOS ROM; Feb. 19, 1981; p. 150.
`Primary Examiner-Stanley D. Miller
`Assistant Examiner--Terry D. Cunningham
`Attorney, Agent, or Firm—-Morgan & Finnegan
`[57]
`ABSTRACT
`An improved sense ampli?er driver for sensing and
`restoring data in memory cells is disclosed. Pull-up
`means in the form of p-channel MOS transistors are
`respectively provided for forcibly pulling up the gate
`voltage of delayable p-channel MOS transistors within
`the ?rst inverter of the sensing clock driver and the
`second inverter of the restore clock driver in the trailing
`transient periods of the sensing and restoring clock
`signals. The formation of a DC current path between
`the power line and the ground line in any one of the
`delayable p-channel MOS transistors is prevented,
`thereby making it possible to avoid the unnecessary
`power dissipation. Further, delaying resistances are
`installed respectively in the ?rst inverter of the sensing
`clock driver and in the second inverter of the restoring
`clock driver to make the slope of the leading edges of
`the sensing and restoring clocks less steep, thereby mak
`ing it possible to exclude the occurrence of noise.
`
`3 Claims, 5 Drawing Sheets
`
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`Page 1 of 11
`
` SAMSUNG EXHIBIT 1004
`
`

`
`US. Patent
`U.S. Patent
`
`8,1gHA
`2m1...
`Aug. 18, 1992
`
`Sheet 1 of 5
`Sheet 1 of 5
`
`5,140,199
`5,140,199
`
`:2 at“: E:
`
`:2.az.:3:
`
`Page 2 of 11
`
`

`
`U.S. Patent
`
`Aug. 18, 1992
`
`Sheet 2 of 5
`
`FIG.2 (Prior Art)
`
`\
`v5
`
`VL
`
`Vss
`
`Va:
`
`“2:
`
`Vcc
`
`Vcc
`
`Page 3 of 11
`
`

`
`U.S. Patent
`
`Aug. 18, 1992
`
`Sheet 3 of 5
`
`5,140,199
`
`F|G.3 ("Prior Art)
`
`Page 4 of 11
`
`

`
`US. Patent
`..ln.GLlaP3U
`
`Aug'.18, 1992
`
`Sheet 4 of 5
`Sheet 4 of 5
`
`5,140,199
`
`-_-_ _--__\.-_ -
`
`‘l
`
`l
`7
`
`3
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`Page 5 of 11
`
`

`
`US. Patent
`U.S. Patent
`
`Aug. 18, 1992
`Aug. 18, 1992
`
`Sheet 5 of 5
`Sheet 5 of 5
`
`5,140,199
`5,140,199
`
`FIG.6
`
`I 1
`
`WP
`
`Page 6 of 11
`
`

`
`1
`
`SENSE AMPLIFIER DRIVER FOR MEMORY
`DEVICE HAVING REDUCED POWER
`DISSIPATION
`
`FIELD OF THE INVENTION
`The present invention relates to sense ampli?er cir
`cuitry for sensing data from memory cells, and particu
`larly to a sense ampli?er driver for driving a sense am
`pli?er by means of sensing clock signals or restoring
`clock signals having multiple slope characteristics for
`reducing the peak current during the process of sensing
`out of or restoring into the CMOS DRAM. The DC
`current paths within the sensing clock driver and the
`restoring clock driver are removed, when returning to a
`precharge state, thereby reducing the dynamic power
`dissipation due to transient current.
`
`BACKGROUND OF THE INVENTION
`Generally, the sense ampli?er circuitry installed
`within a CMOS DRAM device for sensing data from
`the cell comprises a sensing clock driver, a restoring
`clock driver, a delay means and a sense ampli?er. Sens
`ing clock signals for sensing the data from the cell and
`restoring clock signals for restoring the data into the
`cell cause an increase in the peak current if they have
`steep slope characteristics during transitions from a
`high level to a low level, or vice versa. In such a case,
`noise will be generated, and malfunctions can be in
`duced. According to the conventional solutions for this
`problem, steep slopes generated during transitions of
`sensing clock signals or restoring clock signals are di
`vided into double or multiple steps in order to obtain
`gentle slopes. The conventional sense ampli?er driver
`circuit having multi-slope characteristics and referred
`to in this application is illustrated in FIG. 1.
`However, in the circuits according to conventional
`technologies, despite the above-mentioned advantages,
`the MOS transistors within the sensing clock driver are
`simultaneously turned on during a short period of time
`to form a DC current path, thereby consuming DC
`current. This is so due to the fact that, when the pre
`charge operation for the sense ampli?er is started upon
`termination of the sensing and restoring operation, de
`. layings of the trailing edges of the sensing clock signals
`and restoring clock signals occur based on the multi
`slope characteristics of the sensing clock driver and
`restoring clock driver. The MOS transistors within the
`restoring clock driver will also form a DC current path
`together with a part of the sense ampli?er, thereby
`dissipating ,DC currents also. This will cause a large
`dynamic power loss in the whole high density memory
`device.
`
`40
`
`45
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`5,140,199
`2
`An embodiment of the present invention will be pres
`ented in the form of a sense ampli?er driver constituted
`by the sensing clock driver as follows. Therefore sens
`ing clock driver according to the present invention
`includes: a ?rst inverter for inverting the sensing clock
`input; a second inverter consisting of a p-channel MOS
`transistor having a small current driving capability and
`an n-channel MOS transistor having a large current
`driving capability, for re-inverting the output of the ?rst
`inverter; a delay means for delaying the output of the
`?rst inverter; and an additional p-channel MOS transis
`tor having a gate connected to the output terminal of
`the delay means, a drain connected to the output termi
`nal of the second inverter to form a common output
`node, and a source connected to the power line. The
`additional p-channel MOS transistor holds a current
`driving capability larger than that of the p-channel
`transistor within the second inverter. The sensing en
`able signal derived from the common output node of the
`second inverter is also connected to the gate of the
`sensing transistor coupled with the lower potential node
`of the sense ampli?er which bears a multi-slope charac
`teristics. Further, a means is provided for forcibly pull
`ing up the gate voltage of the additional p-channel MOS
`transistor to the power voltage level immediately when
`the sensing clock is disabled. During the trailing tran
`sient period of the sensing clock signal for disabling the
`sensing operation, the additional p-channel MOS tran
`sistor which has a large current driving capability is
`primarily turned off. This is so because the pull-up
`means for pulling up the gate voltage of the additional
`p-channel MOS transistor is turned on, with the ulti
`mate result that the formation of a DC current path
`between the power line and the ground line is pre
`vented, thereby making it possible to avoid the dynamic
`DC power dissipation.
`Another embodiment of the present invention in the
`form of a sense ampli?er driver including a restoring
`clock driver will be explained hereinafter. The restoring
`clock driver according to the present invention in
`cludes: a ?rst inverter for inverting the restoring clock
`derived from a delay means which generates restoring
`clock by delaying the sensing clocks for a predeter
`mined period of time; and a second inverter consisting
`of a plurality of p-channel MOS transistors which are
`arranged in parallel relative to the output terminal of
`the ?rst inverter. The p-channel MOS transistor are
`turned on successively at different time points in re
`sponse to the outputs of the ?rst inverter, and are pro
`vided with time delaying resistances between their
`gates. The restoring enable signals derived from the
`output node of the second inverter is connected to the
`higher potential node of the sense ampli?er will have
`multislope characteristics. Moreover, a means is pro
`vided for forcibly pulling up to the power voltage level
`the gate voltage of at least a p-channel MOS transistor
`having a delayed operating characteristics within the
`second inverter, as soon as the restoring clock is dis
`abled.
`In the trailing transient period of the restoring clock
`signal the restoring operation is disabled. The pull-up
`means is turned on, and in turn the gate of at least a
`p-channel MOS transistor which has a delayed operat
`ing characteristics within the second inverter is forcibly
`pulled up to simultaneously turn off the respective p
`channel MOS transistors within the second inverter.
`The result is that, during the time when the precharge
`operation of a sense ampli?er is being started by an
`
`60
`
`55
`
`SUMMARY OF THE INVENTION
`Therefore it is a ?rst object of the present invention
`to provide a sense ampli?er driver in which the DC
`current path in the sensing clock driver is removed to
`prevent DC current dissipation for the time when the
`precharge operation for the sense ampli?er is being
`started upon termination of sensing operation.
`It is a second object of the present invention to pro
`vide a sense ampli?er driver in which DC current path
`in restoring clock driver is removed to prevent DC
`65
`current dissipation for the time when the precharge
`operation for the sense ampli?er is being started upon
`termination of restoring operation.
`
`Page 7 of 11
`
`

`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The above objects and other advantages of the pres
`ent invention will become more apparent by describing
`the preferred embodiments of the present invention in
`detail with reference to the attached drawings in which:
`FIG. 1 illustrates the detailed circuitry of the sense
`ampli?er driver according to the conventional technol
`08)’;
`FIG. 2 is a timing chart illustrating the operations of
`inputs and outputs of essential parts of the circuitry of
`FIG. 1;
`FIG. 3 is a circuit showing the details of the delay
`means of the sensing clock of FIG. 1;
`FIG. 4 is a timing chart illustrating the functions of
`the circuit of FIG. 3;
`FIG. 5 is a detailed circuitry of a sense ampli?er
`driver according to the present invention; and
`FIG. 6 is a timing chart illustrating the operations of
`the inputs and outputs of essential parts shown in the
`circuit of FIG. 5.
`
`15
`
`30
`
`40
`
`5,140,199
`4
`3
`sense ampli?er, and the latter being applied on the
`equalization clock signal in order to precharge the sense
`lower potential node of the sense ampli?er.
`ampli?er, the formation of a DC current path between
`Now, the operation of conventional sense ampli?er
`the power line and the ground line in any of the p-chan~
`driver constituted as above will be described by refer
`nel MOS transistors of the second inverter will be pre
`ring to FIG. 2 in which a timing chart thereof is illus
`vented.
`trated. If the equalization control clock signal Qeq is at
`the Vss level and the sensing clock signal Qs is at the
`Vcc level to permit a sensing enable state, then node
`“d” of sensing clock driver 1 goes to low level. Accord
`ingly, the p-channel MOS transistor Te is turned on, but
`the current driving capability of this transistor Te is
`relatively small, with the result that the n-channel MOS
`sense transistor Ts can not be turned on suf?ciently.
`Therefore, the n-channel MOS sense transistor Ts does
`not immediately respond to the relatively steep sloped
`signal of node “d”, but is turned on in a slow manner.
`Subsequently, if the potential of node “e” reaches the
`Vss level after a certain time-delay by means of the
`resistance R3, the additional p-channel MOS transistor
`Td having a current driving capability larger than that
`of the transistor Te is turned on. Accordingly, the po
`tential of the node LAG reaches the Vcc level through
`a gentle slope to completely turn on the n-channel MOS
`sense transistor Ts, and therefore, the sensing signal
`LAB comes down from i Vcc level to Vss level
`through a gentle slope to sense the data.
`Meanwhile, the sensing clock signal Qs passes
`through delay means 3 to produce a restore clock signal
`Qsd which is supplied to restoring clock driver 2.
`Now the process of the formation of the restoring
`clock Qsd by delay means 3 will be described in detail
`referring to FIGS. 3 and 4. The sensing clock Qs is
`supplied to an input terminal Qsm of a NAND gate G1
`after passing through delaying resistance RO, while a
`capacitor C is connected between the input terminal of
`the NAND gate G1 and the ground line Vss. Further, a
`sensing/restoring strobe signal SRS is applied on an
`other input terminal of the NAND gate G1. An inverter
`G2 inverts the output of the NAND gate G1 to produce
`a restoring clock signal Qsd. The sensing/restoring
`strobe signal SRS is kept at a high potential level equiv
`alent to Vcc during the sensing and restoring opera
`tions, accordingly as the sensing clock signal Qs is
`raised from the Vss level to the Vcc level for enabling
`the sense transistor Ts, the potential of the input termi
`nal Qsm of the NAND gate G1 is raised from the Vss
`level to the Vcc level based upon the charging opera
`tion of capacitor C. This occurs after a certain period of
`time due to the delaying resistance RO. At the same
`time, the potential of output terminal of inverter G2 also
`raises from Vss level to the Vcc level, thereby making
`it possible to produce the restoring clock signal Qsd.
`Hence which the restoring enable operation can be
`initiated.
`Meanwhile, disabling of sensing operation is synchro'
`nized with disabling of sensing/restoring strobe signal
`SRS. When the falling edge of the sensing clock signal
`Qs appears, the potential of the input terminal of the
`NAND gate G1, i.e., the potential of the terminal Qsm
`of capacitor C drops from Vcc level to Vss level after a
`certain period of time due to the delaying resistance
`RO.
`However, as described before, the sensing/restoring
`strobe signal SRS, which drops to low level, is applied
`to another input terminal of NAND gate G1, and there
`fore, the output Qsd of inverter G2 is forcibly brought
`down from Vcc level to Vss level in synchronization
`with the falling edge of the sensing/restoring strobe
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`First, in order to give an assistance for understanding
`the device of the present invention, a conventional
`cross-coupled sense ampli?er driver will be described
`referring to FIGS. 1 through 4.
`As shown in FIG. 1, sense ampli?er driver for sensing
`the data stored in a memory cell, in general, consists of
`a sensing clock driver 1, a restoring clock driver 2, a
`delay means 3 and a sense ampli?er 4.
`In the circuit of said sense amplifier driver, a sensing
`clock driver 1 is constituted such that an n-channel
`MOS sense transistor Ts is controlled by means of a
`sensing clock signal Qs, which is delivered through a
`?rst inverter IV] and a second inverter 1V3. The sec~
`ond inverter 1V3 consists of p and n-channel MOS
`transistors Te and Tf. Further the sensing clock driver
`1 is also constituted such that the n-channel MOS sense
`transistor Ts can be controlled by means of the output
`of an additional p-channel MOS transistor Td which is
`driven by means of the sensing clock signal Qs deliv
`ered through the ?rst inverter IVl and a delaying resis
`tance R3.
`The sense ampli?er driver also includes, a restoring
`clock driver 2 which is constituted such that delaying
`resistances R1 and R2 are placed between the gates of
`p-channel MOS transistors Ta-Tc which are arranged
`in parallel for sequentially turning on a plurality of
`transistors Ta-Tc by means of restoring clock signals
`Qsd which is derived from the delay means 3 and deliv
`ered through another inverter 1V2. The p-channel
`MOS transistors Ta-Tc compose a still another inverter
`1V4.
`The sense ampli?er 4 includes mutually cross-cou
`pled p-channel MOS transistors TSPI, TSPZ and n
`channel MOS transistors TSNl, TSNZ data restoring
`and sensing operations are carried out by the output
`signal LA of the restoring clock driver 2 and by the
`output signal LAB of the sensing clock driver 1. The
`former being applied on the higher potential node of the
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`Page 8 of 11
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`SRS. Thus the disable state of the restoring clock signal
`nel MOS transistor Td. The connection terminal “d”
`Qsd is produced almost simultaneously as the disable
`between n-channel MOS transistor Th and the resis
`state of the sensing clock signal Qs. Therefore, as the
`tance R3 within inverter IV10 is connected to the input
`restoring clock signal Qsd is enabled after being delayed
`terminal of inverter IV30. The drain of p-channel MOS
`for a certain period of time from the time of the enabling
`transistor Td and the output terminal of inverter IV30
`of sensing clock signal, the p-channel MOS transistor
`are connected to a common output terminal LAG
`Ta is turned on, while the p-channel MOS transistor Tb
`which is connected to the gate of sense transistor Ts.
`In the embodiment of FIG. 5, upon the disabling of
`is turned on after being delayed by resistance R1.
`the sensing clock signal Qs, the p-channel MOS transis
`Again, the p-channel MOS transistor Tc is turned on
`after being delayed by resistance R2, with the result that
`tor Tg of inverter IV10 is functions as a means for forci
`bly pulling up the gate voltage of the additional p-chan
`the potential of the restoring signal LA of restoring
`clock driver 2, which is applied on higher potential
`nel MOS transistor Td to the level of power source
`node of sense ampli?er 4, is raised from i Vcc level to
`voltage in order to prevent the formation of a DC cur
`rent path.
`Vcc level with a gentle slope to restore the data to sense
`ampli?er 4.
`Also in FIG. 5, restoring clock driver 20 consists of
`an inverter IV20, a plurality of p-channel MOS pull-up
`However, in such a conventional circuitry, during
`the disabling of the sensing clock signal Qs, the p-chan
`transistors Ti, Ti, and an inverter IV40 which consists
`of a plurality of p-channel MOS transistors Ta-Tc and
`nel MOS transistor Tc of the restoring clock driver 2
`resistances R1,R2 installed between the gates of transis
`and the p-channel MOS transistor Td of the sensing
`tors Ta-Tc. A delay means 30 which is constituted in
`clock driver 1 are turned off after being delayed for a
`certain period of time, thereby forming a DC current
`the same way as the delay means 3 of FIG. 3 supplies
`the restoring clock signal Qsd to restoring clock driver
`path between the power line and the ground line. More
`20. Restoring clock signal Qsd thus delivered passes
`speci?cally, in sensing clock driver 1, a DC current
`through inverter IV20 to the gates of the transistors
`path is formed between the power line Vcc and the
`ground line Vss through the p and n-channel MOS
`Ta-Tc. The transistors Ta-Tc successively turn on or
`25
`off by the resistances R1, R2. Further, the restoring
`transistors Td, and Tf. This occurs during the period of
`clock signal Qsd derived from delay means 30 is also
`time starting from time t1 at which the potential of node
`supplied to the gates of the plurality of p-channel MOS
`“d” is raised to threshold voltage Vtn for turning on the
`pull-up transistors Ti,Tj so that, upon feeding of restor
`n-channel MOS transistor Tf, to time t4 at which time
`ing signals of the Vss level, the Vcc level voltage can be
`the potential of node “e” is raised to the threshold volt
`supplied through the respective p-channel MOS transis
`age Vtp for turning off the p-channel MOS transistor
`tors Ti, Tj to the gates of the p-channel MOS transistors
`Td.
`Ta-Tc.
`Meanwhile, in the restoring clock driver 2, a DC
`Upon disabling of the restoring clock signal Qsd, the
`current path is formed either sequentially through p
`p-channel MOS pull-up transistors Ti, Tj functions as
`channel MOS transistor Tc, the p-channel MOS transis
`means for forcibly pulling up the gate voltages of the
`tor TSPl, the equalization transistor Teq, the n-channel
`p-channel MOS transistors Tb, Tc within inverter IV40
`MOS transistor TSN2 and the n-channel MOS sense
`having a delayed operation characteristics, immediately
`transistor Ts, or sequentially through p-channel MOS
`transistor Tc, p-channel MOS transistor TSP2, the
`to the power source voltage level in order to prevent
`equalization transistor Teq, n-channel MOS transistor
`the formation of a DC current path.
`The sensing and restoring output signals LAB and
`TSNl and the n-channel MOS sense transistor Ts. This
`LA delivered from the drain of the n-channel MOS
`occurs during the period of time starting from time t2 at
`which time the equalization control clock begins to
`sense transistor Ts and from the drains of the p-channel
`MOS transistors Ta-Tc are supplied to sense ampli?er
`raise from Vss level to Vcc level, to time t3 at which
`40 of FIG. 5. Speci?cally, these signals LAB, LA are
`time p-channel MOS transistor Tc is turned off.
`respectively supplied to the common source (a lower
`Thus, when the sensing clock signal Qs and the re
`potential node) of two n-channel MOS transistors
`storing clock signal Qsd are disabled, the peak current
`TSNl, TSN2, and to the common source (a higher
`increases for a certain period of time, and an unneces
`potential node) of two p-channel MOS transistors
`sary power loss results.
`TSPl, TSP2, thereby making it possible to carry out the
`FIGS. 5 and 6 respectively illustrate the sense ampli
`sensing and restoring operations for the cell data. Four
`?er driver circuitry for a memory device and the timing
`chart of the operation of the circuitry according to the
`transistors TSNl, TSN2, TSPl, TSP2 are cross-cou
`present invention which is intended to solve the prob
`pled to one another.
`lem experienced by conventional devices.
`Now, the operation and effects of the circuit of the
`present invention will be further described by referring
`Referring to FIG. 5, a sensing clock driver 10 consists
`to the timing chart of FIG. 6. If a sensing enable state is
`of an inverter IV10 having two outputs, an additional
`established by the equalization control clock Qeq being
`p-channel MOS transistor Td having a large current
`at the Vss level and the sensing clock signal Qs being at
`driving capability, and an inverter IV30. The double
`output inverter IV10 comprises a delaying resistance
`the Vcc level, then node “d” of sensing clock driver 10
`to Vss level immediately owing to the function of n
`R3 and p and n-channel MOS transistors Tg and Th.
`channel MOS transistor Th of inverter IV10. There
`The inverter IV30 comprises p and n-channel MOS
`fore, the p-channel MOS transistor Te of the inverter
`transistors Te and Tf. The sensing clock driver 10 thus
`includes, sensing clock signal Qs which is supplied
`IV30 immediately turns on. However, since transistor
`through inverter IV10 both to the additional p-channel
`Te has small current driving capability, the common
`output node LAG is not immediately raised to high
`MOS transistor Td, and to inverter IV30.
`More speci?cally, connection terminal “e” between
`level, i.e., to the Vcc level.
`Subsequently, if the potential of node “e” is lowered
`p-channel MOS transistor Tg and resistance R3 within
`to Vss level after having been delayed for a certain
`the inverter IV10 is connected to the gate of the p-chan
`
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`nel MOS transistor Td can be made by including a
`period of time due to the function of resistance R3 of
`p-channel MOS transistor having a gate connected to
`inverter IVlO, then the additional p-channel MOS tran
`input terminal of ?rst inverter IVl of FIG. 1, a source
`sistor Td having a large current driving capability turns
`connected to power line, and a drain connected to the
`on. Therefore, the potential of node LAG raises to Vcc
`gate of the additional p-channel MOS transistor Td.
`level with a multi-slope characteristics, so that it can
`Even in this embodiment as in the case of FIG. 5, the
`completely turn on the n-channel MOS sense transistor
`additional p-channel MOS transistor Td is preferen
`Ts. The resultant sensing signal LAB of the Vss level
`tially turned off during the trailing transient position of
`obtained through the turning-on operation of the n
`sensing clock signal Qs for disabling the sensing opera
`channel MOS sense transistor Ts carries out the sensing
`tion, as the pull-up means for the gate voltage of the
`operation for the data stored in the memory cell.
`additional p-channel MOS transistor Td is turned on,
`Meanwhile, the restoring clock signal Qsd delivered
`thereby preventing the formation of a DC current path
`through delay means 30 is supplied through inverter
`between the power line and the ground line.
`IVZO to successively turn on a plurality of p-channel
`Thus the circuit of the present invention as described
`MOS transistors Ta-Tc. Accordingly, the sensed data
`above can effectively inhibit the sudden rise of the peak
`as described above is restored by restoring signal LA of
`current during sensing and restoring of data in a mem
`Vcc level. During this process, pull-up p-channel MOS
`ory cell, and can also prevent any unnecessary dynamic
`transistors Ti, T} are not operative, and therefore, they
`power dissipations.
`can not exert any in?uence on the aforementioned re
`storing operation.
`It should also be understood that the foregoing re
`lates to only a preferred embodiment of the invention,
`Now the disabling of sensing clock signal Qs will be
`and that it is intended to cover all changes and modi?ca
`described hereinafter. If sensing clock signal Qs drops
`tions of the example of the invention herein chosen for
`to low level, the drain of p-channel MOS transistor Tg
`the purposes of the disclosure, which do not constitute
`of the inverter IV10, i.e., the node “e” immediately
`departures from the spirit and scope of the invention.
`raises to Vcc level so that p-channel MOS transistor Td
`having a large current driving capability immediately
`What is claimed is:
`25
`1. A sense ampli?er driver including a sensing clock
`turns off. Then, when the potential of node “d” is saised
`driver for delivering a sensing enable signal in response
`to Vcc level, p-channel MOS transistor Te turns off,
`to a sensing clock signal, said sensing enable signal
`and n-channel MOS transistor Tf turns on. Accord
`being delivered to a sensing enable terminal of a data
`ingly, thepotential of node LAG goes to Vss level to
`sensing ampli?er coupled between a pair of bit lines,
`turn off the n-channel MOS sense transistor Ts.
`and a restoring clock driver for delivering a restoring
`As may be understood from the above descriptions,
`enable signal to a restoring enable terminal of said data
`there is almost no time lag between time t1 at which the
`sensing ampli?er in response to a restoring clock signal,
`n-channel MOS transistor Tf is turned on and time t4 at
`a rising edge and a falling edge of said sensing enable
`which the p-channel MOS transistor Td is turned off.
`signal having multi-slope characteristics, said sensing
`Therefore, there is no possibility of the formation of a
`clock driver further comprising:
`DC current path which causes dynamic power losses in
`a ?rst inverter for respectively generating a ?rst out
`the p-channel MOS transistor Td between the power
`put signal and a second output signal in response to
`line and the ground line.
`said sensing clock signal, said ?rst output signal
`Meanwhile the restoring clock signal Qsd of the low
`having a rapid rising transient edge and a slow
`level will turn off the p-channel MOS transistors Ta-Tc
`falling transient edge, said second output signal
`within inverter IV40 after passing through inverter
`having a slow rising transient edge and a rapid
`IV20. The restoring clock signal Qsd of low level will
`falling transient edge:
`turn on pull-up transistors Ti, Tj immediately without
`a second inverter, having a p-channel MOS transistor
`causing any time delay. Accordingly, the gates of p
`and an n-channel MOS transistor, for inverting said
`channel MOS transistors Tb and To are instantly pulled
`second output signal of the first inverter;
`up to Vcc level, and therefore, p-channel MOS transis
`a p-channel MOS transistor having a gate coupled
`tors Tb and To are instantly pulled up to Vcc level, and
`with said ?rst output signal of the ?rst inverter, a
`therefore, the p-channel MOS transistors Tb and Te are
`drain coupled to an output terminal of said second
`all immediately turned off at time t3 without any time
`inverter and a source coupled with a power source
`delay due to resistances R1 and R2. The result is that
`voltage, and having a current driving capability
`the current path from power line will no longer exist by
`larger than that of said p-channel MOS transistor of
`time t2 at which time the equalization clock signal Qeq
`the second inverter, said p-channel MOS transistor
`is enabled. Therefore, the possiblity of a DC current
`being slowly turned on and rapidly turned off in
`path between power line and ground line through p
`response to said ?rst output signal of the ?rst in
`channel MOS transistor Tc, sense ampli?er 40 and n
`channel MOS sense transistor Ts is prevented, and only
`verter; and
`an n-channel MOS transistor having a gate coupled to
`the voltage of restoring node LA is synchronized with
`the rising edge of equalization clock signal Qeq, so that
`said output terminal of the second inverter, a
`source coupled to said sensing enable terminal of
`it would come down through sense ampli?er 40 from
`the data sensing ampli?er and a drain coupled with
`Vcc level to i Vcc level.
`a ground voltage.
`Further, another embodiment of means for pulling up
`2. The sense ampli?er driver as claimed in claim 1,
`gate voltage of additional p-channel MOS transistor Td
`wherein said ?rst inverter comprises a p-channel MOS
`immediately to power source voltage level upon dis
`transistor having a gate coupled with said sensing clock
`abling of sensing clock Qs, although not illustrated in
`signal, a source coupled with said power source voltage
`the drawing, can be realized by adding a p-channel
`and a drain coupled to said gate of the p-channel MOS
`MOS transistor having the following connections in
`transistor responding to said ?rst output signal; an n
`sensing clock driver 1 of FIG. 1. That is, the means for
`channel MOS transistor having a gate coupled with said
`pulling up the voltage of the gate of additional p-chan
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`sensing clock signal, a source coupled with said ground
`age and said restoring enable terminal of the data
`sensing ampli?er, the respective gates thereof con
`voltage and a drain coupled to an input terminal of said
`second inverter; and a delay means, coupled between
`nected to an output terminal of said inverter via a
`said drains of the p-channel and n-channel MOS transis
`respective delay means, and
`tors of the ?rst inverter, for retarding the falling tran- 5
`a second plurality of p-channel MOS transistors, each
`sient of said ?rst output signal and the rising transient of
`having a gate coupled with said restoring clock
`said second output signal.
`signal, a source coupled with said power source
`3. The sense ampli?er driver as cla