IEEE
`Std 802.3, 1998 Edition
`
`22.2.4.4.4 OP (operation code]
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`The operation code for a read transaction is <103>, while the operation code for a write transaction is <01?-.
`
`22.2.4.4.5 PHYAD {PHY Address}
`
`The PHY Address is five bits, allowing 32 unique PHY addresses. The first PHY address bit transmitted and
`received is the MSB of the address. A PHY that is connected to the station management entity via the
`mechanical interface defined in 22.6 shall always respond to transactions addressed to PHY Address zero
`<00000>. A station management entity that is attached to multiple PHYS must have a priori knowledge of
`the appropriate PHY Address for each PHY.
`
`22.2.4.4.6 REGAD (Register Address}
`
`The Register Address is five bits. allowing 32 individual registers to be addressed within each PHY. The first
`Register Address bit transmitted and received is the MSB of the address. The register accessed at Register
`Address zero <00000> shall be the control register defined in 22.2.4.1, and the register accessed at Register
`Address one <00001> shall be the status register defined in 22.2.4.2.
`
`22.2.4.4} TA {turnaround}
`
`The turnaround time is a 2 bit time spacing between the Register‘ Address field and the Data field of a man-
`agement frame to avoid contention during a read transaction. For a read transaction. both the STA and the
`PHY shall remain in a high-impedance state for the first bit time of the turnaround. The PHY shall drive a
`zero bit during the second bit time of the turnaround of a read transaction. During a write transaction, the
`STA shall drive a one bit for the first bit time of the turnaround and a zero bit for the second bit time of the
`
`turnaround. Figure 22-13 shows the behavior of the MDIO signal during the turnaround field of a read trans-
`action.
`
`Figure 22-13—Behavior of MDIO during TA field of a read transaction
`
`22.2.4.4.8 DATA {data}
`
`The data field is 16 bits. The fi.rst data bit transmitted and received shall be bit 15 of the register being
`addressed.
`
`22.3 Signal timing characteristics
`
`All signal timing characteristics shall be measured using the techniques specified in annex 22C. The signal
`
`threshold potentials Vihcmm) and Vmmax} are defined in 22.4.4.1.
`
`This is angfirchive IEEE Standard.
`
`It has been superseded by0g,,{a§ag'@ig§§iQgEqt..t.Q,i§s$;§adard.
`
`Aerohive - Exh
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`Aerohive - Exhibit 1025
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`

`
`CSMNCD
`
`IEEE
`Std 302.3, 1993 Edtlion
`
`The HIGH time of an M11 signal is defined as the length of time that the potential of the signal is greater tha.11
`
`or equal to V’,-Mm:-n)_ The LOW time of an M11 signal is defined as the length of time that the potential of the
`signal is less than or equal to Vmmn}
`
`The setup time of an M11 signal relative to an M11 clock edge is defined as the length of time between when
`the sigial exits and remains out of the switching region and when the clock enters the switching region. The
`hold time of an M1] signal relative to an M11 clock edge is defined as the length of time between when the
`clock exits the switching region and when the signal enters the switching region.
`
`The propagation delay from an M11 clock edge to a valid MJI signal is defined as the length of time between
`when the clock exits the switching region and when the signal exits and remains out of the switching region.
`
`22.3.1 Signals that are synchronous to TX_CLK
`
`Figure 22-14 shows the timing relationship for the sigials associated with the transmit data path at the MH
`connector. The clock to output delay shall be a minimum of 0 ns and a maximum of 25 ns.
`
`T)(_CLK
`
`Txo<3:u>, TX_EN, TX_ER
`
`V 9 V V "9
`';?_o‘.'¢?9‘.'o‘.'¢?
`'lIJ;'IA'A\ K
`
`*0’;
`
`Vlhlminl
`
`Vl'(maJ=)
`
`V‘h(n-Ii")
`
`Figure 22-14—Transmit signal timing relationships at the Mll
`
`22.3.1.1 TX_EN
`
`TX_EN is transitioned by the Reconciliation sublayer synchronously with respect to the TX_CLK rising
`edge with the timing as shown in figure 22-14.
`
`22.3.1.2 TXD<3:0>
`
`TXD<3:0> is transitioned by the Reconciliation sublayer synchronously with respect to the TX_CLK rising
`edge with the timing as depicted i.n figure 22-14.
`
`22.3.1.3 TX_ER
`
`TX_ER is transitioned synchronously with respect to the rising edge of TX_CLK as shown in figure 22-14.
`
`22.3.2 Signals that are synchronous to RX_CLK
`
`Figure 22-15 shows the timing relationship for the sigials associated with the receive data path at the M11
`connector. The timing is referenced to the rising edge of the RX_CLK. The input setup time shall be a mini-
`mum of 10 ns and the input hold time shall be a minimum of 10 ns.
`
`This is arb&5gl3ii.@1$¢fifi§tan§lgrQ5e,l,tKl]as been superseded by a later version of this standard.
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`Aerohive - Exh
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`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`Rx_cLK
`
`7
`RXD<3_C|>, RX_DV, RX_ER
`
`Vih(min)
`vmm)
`
`:;ih(rnin)
`|h(ma_x}
`
`at
`
`1’:-‘_-‘\
`
`Figure 22-15—Receive signal timing relationships at the Mll
`
`22.3.2.1 RX_DV
`
`RX_DV is sampled by the Reconciliation sublayer synchronously with respect to the rising edge of
`RX_CLK with the timing shown i.n figure 22-15.
`
`22.3.2.2 RXD<3:0>
`
`RXD<3:0> is sampled by the Reconciliation sublayer synchronously with respect to the rising edge of
`RX_CLK as shown in figure 22-15. The RXD<3:0> timing requirements must be met at all rising edges of
`RX_CLK.
`
`22.3.2.3 RX_ER
`
`RX_ER is sampled by the Reconciliation sublayer synchronously with respect to the rising edge of
`RX_CLK as shovm in figure 22-15. The RX_ER timing requirements must be met at all rising edges of
`RX CLK.
`
`22.3.3 Signals that have no required clock relationship
`
`22.3.3.1 CRS
`
`CRS is driven by the PHY. Transitions on CRS have no required relationship to either of the clock signals
`provided at the M11.
`
`22.3.3.2 COL
`
`COL is driven by the PHY. Transitions on COL have no required relationship to either of the clock signals
`provided at the M11.
`
`22.3.4 MDIO timing relationship to MDC
`
`MDIO (Management Data Input/Output) is a bidirectional signal that can be sourced by the Station Manage-
`ment Entity (STA) or the PHY. When the STA sources the MDIO signal, the STA shall provide a minimum
`of 10 us of setup time and a minimum of 10 ns of hold time referenced to the rising edge of MDC. as shown
`in figure 22-16, measured at the M1] connector.
`
`When the MDIO signal is sourced by the PHY. it is sampled by the STA synchronously with respect to the
`rising edge of MDC. The clock to output delay from the PHY. as measured at the M11 connector. shall be a
`minimum ofO ns, and a maximum of300 ns, as shown in figure 22-17.
`
`This is anggtrchive lEEE Standard.
`
`It has been superseded by[3‘apifi§fii'4g3l@Ij§iQfigQ{||t.E‘!;i§5$.L§[i}LQ§ird.
`
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`
`IEEE
`Std 802.3, 1998 Edition
`
`MDC
`
`MDIO
`
`
`V'9'9‘9‘9'.'
`Vih(min)
`K\\Y6Y6Y6YIl’7
`Dlofoioiofoii
`
`rl:.v.v.v.v.\ l
`1.;
`Vi|(max)
`
`
`
`
`
`
`MDC
`
`MDIO
`
`Figure 22-17—MDlO sourced by PHY
`
`22.4 Electrical characteristics
`
`The electrical characteristics of the M11 are specified such that the three application environments described
`in 22.1 are accommodated. The electrical specifications are optimized for the integrated circuit to integrated
`circuit application environment, but integrated circuit drivers and receivers that are implemented in compli-
`ance with the specification will also support the mother board to daughter board and short cable application
`environments, provided those environments are constrained to the limits specified in this clause.
`
`NOTE—The specifications for the driver and receiver characteristics can be met with TTL compatible input and output
`buffers implemented in a digital CMOS ASIC process.
`
`22.4.1 Signal levels
`
`The MII uses TTL signal levels, which are compatible with devices operating at a nominal supply voltage of
`either 5.0 or 3.3 V.
`
`NOTE—Care should be taken to ensure that all MII receivers can tolerate dc input potentials from 0.00 V to 5.50 V, refer-
`enced to the COMMON signal, and transient input potentials as high as 7.3 V, or as low as -1.8 V, referenced to the COM-
`MON signal, which can occur when IVHI signals change state. The transient duration will not exceed 15 ns. The dc source
`impedance will be no less than Roh(m]-H). The transient source impedance will be no less than (68 X 0.85 =) 57.8 $2.
`
`This is arbetgfigiii/@1fifiEE§tan§i,grg,e,lt,§]as been superseded by a later version of this standgrd.
`
`bit 1025
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`Aerohive - Exhibit 1025
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`
`IEEE
`Std 802.3, 1998 Edition
`
`22.4.2 Signal paths
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`MII signals can be divided into two groups: signals that go between the STA and the PHY, and signals that
`go between the Reconciliation sublayer and the PHY.
`
`Signals between the STA and the PHY may connect to one or more PHYs. When a signal goes between the
`STA and a single PHY, the signal’s path is a point—to—point transmission path. When a signal goes between
`the STA and multiple PHYS, the signal’s transmission path has drivers and receivers attached in any order
`along the length of the path and is not considered a point-to-point transmission path.
`
`Signals between the Reconciliation sublayer and the PHY may also connect to one or more PHYS. However,
`the transmission path of each of these signals shall be either a point-to-point transmission path or a sequence
`of point-to-point transmission paths connected in series.
`
`All connections to a point—to—point transmission path are at the path ends. The simplest point-to-point trans-
`mission path has a driver at one end and a receiver at the other. Point-to-point transmission paths can also
`have more than one driver and more than one receiver if the drivers and receivers are lumped at the ends of
`the path, and if the maximum propagation delay between the drivers and receivers at a given end of the path
`is a very small fraction of the 10%—90% rise/fall time for signals driven onto the path.
`
`The MII shall use unbalanced signal transmission paths. The characteristic impedance Z0 of transmission
`paths is not specified for electrically short paths where transmission line reflections can be safely ignored.
`
`The characteristic impedance Z0 of electrically long transmission paths or path segments shall be 68 Q :|: 15%.
`
`The output impedance of the driver shall be used to control transmission line reflections on all electrically
`long point-to-point signal paths.
`
`NOTE—In the context of this clause, a transmission path whose round-trip propagation delay is less than half of the
`l0%—90% rise/fall time of signals driven onto the path is considered an electrically short transmission path.
`
`22.4.3 Driver characteristics
`
`The driver characteristics defined in this clause apply to all MII signal drivers. The driver characteristics are
`specified in terms of both their ac and dc characteristics.
`
`NOTE—Rail-to-rail drivers that comply with the driver output V-I diagrams in annex 22B will meet the following ac and
`dc characteristics.
`
`22.4.3.1 DC characteristics
`
`The high (one) logic level output potential Voh shall be no less than 2.40 V at an output current 1011 of -4.0 mA.
`The low (zero) logic level output potential V01 shall not be greater than 0.40V at an output current 101 of
`4.0 mA.
`
`22.4.3.2 AC characteristics
`
`Drivers must also meet certain ac specifications in order to ensure adequate signal quality for electrically
`long point—to—point transmission paths. The ac specifications shall guarantee the following performance
`requirements.
`
`The initial incident potential change arriving at the receiving end of a point-to-point MII signal path plus its
`reflection from the receiving end of the path must switch the receiver input potential monotonically fi'om a
`
`valid high (one) level to Vil S Vmmax) — 200 mV, or from a valid low (zero) level to Vih Z Vimmin) + 200 mV,
`
`This is an54\rchive IEEE Standard.
`
`It has been superseded byogpigggrg/g§§iggEg(..ti;isss;agagard.
`
`bit 1025
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`Std 802.3, 1998 Edition
`
`Subsequent incident potential changes arriving at the receiving end of a point—to—point MII signal path plus
`their reflections from the receiving end of the path must not cause the receiver input potential to reenter the
`
`range Vimiiax) — 200 mV < Vi < Vimmin) + 200 mV except when switching from one valid logic level to the
`other. Such subsequent incident potential changes result from a mismatch between the characteristic imped-
`ance of the signal path and the driver output impedance.
`
`22.4.4 Receiver characteristics
`
`The receiver characteristics are specified in terms of the threshold levels for the logical high (one) and logi-
`cal low (zero) states. In addition, receivers must meet the input current and capacitance limits.
`
`22.4.4.1 Voltage thresholds
`
`An input potential Vi of 2.00 V or greater shall be interpreted by the receiver as a logical high (one). Thus,
`Vih(miii) = 2.00 V. An input potential Vi of 0.80 V or less shall be interpreted by the receiver as a logical low
`(zero). Thus, Vii(ma,i) = 0.80 V. The switching region is defined as signal potentials greater than Vii(max) and
`less than Viii(miii). When the input signal potential is in the switching region, the receiver output is undefined.
`
`22.4.4.2 Input current
`
`The input current requirements shall be measured at the MII connector and shall be referenced to the +5 V
`supply and COMMON pins of the connector. The input current requirements shall be met across the full
`range of supply voltage specified in 22.5.].
`
`The bidirectional signal MDIO has two sets of input current requirements. The MDIO drivers must be dis-
`abled when the input current measurement is made.
`
`The input current characteristics for all MII signals shall fall within the limits specified in table 22-10.
`
`Table 10—lnput current limits
`
`Parameter
`
`Condition
`
`Signal(s)
`
`Input High Current
`
`Input Low Current
`
`All except COL,
`VIDC, MD1o*
`
`coLi
`
`VIDCI
`
`\/IDIO§
`**
`
`\/IDIO
`
`All except COL,
`VIDC, MDIO“
`
`COLb
`
`‘VIDCC
`
`MDIO‘!
`
`MDlOe
`
`This is arbeigfigii/@1EfiEE§tanggrg,e,li.,,has been superseded by a later version of this standard.
`
`Aerohive - Exhibit 1025
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`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`Table 10—lnput current limits (Continued)
`
`
`
`‘Measured at input of Reconciliation sublayer for CRS, RXD<3:0>, RX_CLK, RX_DV, RX_ER, and TX_CLK. Mea-
`sured at inputs of PHY for TXD<3:0>, TX_EN, and TX_ER.
`lMeasured at input of Reconciliation sublayer.
`iMeasured at input of PHY.
`§l*\/leasured at input of STA.
`Measured at input of PHY, which can be attached via the mechanical interface specified in 22.6.
`
`NOTE—These limits for dc input current allow the use of weak resistive pull-ups or pull-downs on the input of each MH
`signal. They allow the use of weak resistive pull-downs on the signals other than COL, MDC, and MDIO. They allow the
`use of a weak resistive pull-up on the signal COL. They allow the use of a resistive pull-down of 2 k9 i 5% on the MDIO
`signal in the STA. They require a resistive pull-up of 1.5 kQ :: 5% on the MDIO signal in a PHY that is attached to the M11
`via the mechanical interface specified in 22.6. The limits on MDC and MDIO allow the signals to be “bused” to several
`PHYS that are contained on the same printed circuit assembly, with a single PHY attached via the M11 connector.
`
`22.4.4.3 Input capacitance
`
`For all signals other than MDIO, the receiver input capacitance Ci shall not exceed 8 pF.
`
`For the MDIO signal, the transceiver input capacitance shall not exceed 10 pF.
`
`22.4.5 Cable characteristics
`
`The MII cable consists of a bundle of individual twisted pairs of conductors with an overall shield covering
`this bundle. Each twisted pair shall be composed of a conductor for an individual signal and a return path
`dedicated to that signal.
`
`NOTE—It is recommended that the signals RX_CLK and TX_CLK be connected to pairs that are located in the center
`of the cable bundle.
`
`22.4.5.1 Conductor size
`
`The specifications for dc resistance in 22.4.5.6 and characteristic impedance in 22.4.5.2 assume a conductor
`size of 0.32 mm (28 AWG).
`
`22.4.5.2 Characteristic impedance
`
`The single-ended characteristic impedance of each twisted pair shall be 68 Q :i: 10%. The characteristic
`impedance measurement shall be performed with the return conductor connected to the cable’s overall shield
`at both ends of the cable.
`
`22.4.5.3 Delay
`
`The propagation delay for each twisted pair, measured from the MII connector to the PHY, shall not exceed
`2.5 ns. The measurement shall be made with the return conductor of the pair connected to the cable’s overall
`shield at both ends of the cable. The propagation delay shall be measured at a frequency of 25 MHz.
`
`This is angetrchive IEEE Standard.
`
`It has been superseded byoapiggerg/g§§iggEg(..ti;i§ss;ag;igard.
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`22.4.5.4 Delay variation
`
`IEEE
`Std 802.3, 1998 Edition
`
`The variation in the propagation delay of the twisted pairs in a given cable bundle, measured from the MII
`connector to the PHY, shall not exceed 0.1 ns. The measurement shall be made with the return conductor of
`the pair connected to the cab1e’s overall shield at both ends of the cable.
`
`22.4.5.5 Shielding
`
`The overall shield must provide sufiicient shielding to meet the requirements of protection against electro-
`magnetic interference.
`
`The overall shield shall be terminated to the connector shell as defined in 22.6.2. A double shield, consisting
`of both braid and foil shielding, is strongly recommended.
`
`This is arbelgfigii/@1EfiEE§;anggrg,e,l1.,.has been superseded by a later version of this standard.
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`bit 1025
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`
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`Std 802.3, 1998 Edition
`
`22.4.5.6 DC resistance
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`The dc resistance of each conductor in the cable, including the contact resistance of the connector, shall not
`exceed 150 m9 measured fiom the M11 connector to the remote PHY.
`
`22.4.6 Hot insertion and removal
`
`The insertion or removal of a PHY from the M11 with power applied (hot insertion or removal) shall not
`damage the devices on either side of the IVIII. In order to prevent contention between multiple output buffers
`driving the PHY output signals, a PHY that is attached to the M11 via the mechanical interface defined in
`22.6 shall ensure that its output buffers present a high impedance to the MH during the insertion process, and
`shall ensure that this condition persists until the output buffers are enabled via the Isolate control bit in the
`management interface basic register.
`
`NOTE—The act of inserting or removing a PHY from an operational system may cause the loss of one or more packets
`or management frames that may be in transit across the M11 or MDI.
`
`22.5 Power supply
`
`When the mechanical interface defined in 22.6 is used to interconnect printed circuit subassemblies, the Rec-
`onciliation sublayer shall provide a regulated power supply for use by the PHY.
`
`The power supply shall use the following MII lines:
`
`+5 V: The plus voltage output to the PHY.
`
`COMMON: The return to the power supply.
`
`22.5.1 Supply voltage
`
`The regulated supply voltage to the PHY shall be 5 Vdc dz 5% at the M11 connector with respect to the COM-
`MON circuit at the MII over the range of load current from 0 to 750 mA. The method of over/under voltage
`protection is not specified; however, under no conditions of operation shall the source apply a voltage to the
`+5 V circuit of less than 0 V or greater than +5.25 Vdc.
`
`Implementations that provide a conversion fi'om the MII to the Attachment Unit Interface (AUI) to support
`connection to 10 Mb/s Medium Attachment Units (MAUs) will require a supplemental power source in
`order to meet the AUI power supply requirements specified in 7.5.2.5.
`
`22.5.2 Load current
`
`The sum of the currents carried on the +5 V lines shall not exceed 750 mA, measured at the M11 connector.
`The surge current drawn by the PHY shall not exceed 5 A peak for a period of 10 ms. The PHY shall be
`capable of powering up from 750 mA current limited sources.
`
`22.5.3 Short-circuit protection
`
`Adequate provisions shall be made to ensure protection of the power supply from overload conditions,
`including a short circuit between the +5 V lines and the COMMON lines.
`
`This is anggtrchive IEEE Standard.
`
`It has been superseded byogplagerg/g§§iggEg(..ti;i§s$;agagard.
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`22.6 Mechanical characteristics
`
`IEEE
`Std 802.3, 1998 Edition
`
`When the M11 is used to interconnect two printed circuit assemblies via a short length of cable, the cable
`shall be connected to the circuit assembly that implements the Reconciliation sublayer by means of the
`mechanical interface defined in this clause.
`
`22.6.1 Definition of mechanical interface
`
`A 40-pole connector having the mechanical mateability dimensions as specified in IEC 1076-3-101: 1995
`shall be used for the MII connector. The circuit assembly that contains the MAC sublayer and Reconciliation
`sublayer shall have a female connector with screw locks, and the mating cable shall have a male connector
`with jack screws.
`
`No requirements are imposed on the mechanical interface used to connect the MII cable to the PHY circuit
`assembly when the MII cable is permanently attached to the PHY circuit assembly, as shown in figure 22-2.
`If the cable is not permanently attached to the PHY circuit assembly, then a male connector with jack screws
`shall be used for the M11 connector at the PHY circuit assembly.
`
`NOTE—All MII conformance tests are performed at the mating surfaces of the MH connector at the Reconciliation sub-
`layer end of the cable. If a PHY circuit assembly does not have a permanently attached cable, the vendor must ensure
`that all of the requirements of this clause are also met when a cable that meets the requirements of 22.4.5 is used to
`attach the PHY circuit assembly to the circuit assembly that contains the Reconciliation sublayer.
`
`22.6.2 Shielding effectiveness and transfer impedance
`
`The shells of these connectors shall be plated with conductive material to ensure the integrity of the current
`path from the cable shield to the chassis. The transfer impedance of this path shall not exceed the values
`listed in table 22-1 1, after a minimum of 500 cycles of mating and unmating. The shield transfer impedance
`values listed in the table are measured in accordance with the procedure defined in annex L of IEEE P1394
`[A1 8] .
`
`Table 11—Transfer impedance performance requirements
`
`
`
`All additions to provide for female shell to male shell conductivity shall be on the shell of the connector with
`male contacts. There should be multiple contact points around the sides of this shell to provide for shield
`continuity.
`
`This is arbelgfigig/@1EfiEE§tanggrg,e,lt,,has been superseded by a later version of this standard.
`
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`
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`Std 802.3, 1993 Edition
`
`22.6.3 Connector pin numbering
`
`LOCAL AND METROPOUTAN AREA NETWORKS:
`
`Figure 22-18 depicts the M11 connector pin numbering, as seen looking into the contacts of a female connec-
`tor fi'om the mating side.
`
`020019018o1?°16o15o14o13o12o1101009 O8 O7 O6 O5 O4 O3 O2 O1
`
`O40 O39 O38 O3T036 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 021
`
`Figure 22-18—MlI connector pin numbering
`
`22.6.4 Clearance dimensions
`
`The circuit assembly that contains the MAC sublayer and Reconciliation sublayer shall provide sufficient
`clearance around the M1] connector to allow the attachment of cables that use die cast metal backshells and
`
`overmold assemblies. This requirement may be met by providing the clearance dimensions shown in
`figure 22-19.
`
`Figure 22-19—M|| connector clearance dimensions
`
`This is anygirchive IEEE Standard.
`
`it has been superseded byogpiagergifggaiggggiuthjiassgagadard.
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`22.6.5 Contact assignments
`
`Table 22-12 shows the assignment of circuits to connector contacts.
`
`IEEE
`Std 802.3, 1998 Edition
`
`Table 12—Mll connector contact assignments
`
`Signal name
`
`Signal name
`
`+5V
`
`COMMO\I
`
`COMMOV
`
`COMMO\I
`
`COMMO\I
`
`COMMO\I
`
`COMMOV
`
`COMMO\I
`
`COMMO\I
`
`COMMOV
`
`COMMO\I
`
`COMMO\I
`
`COMMO\I
`
`COMMOV
`
`COMMOV
`
`COMMO\I
`
`COMMO\I
`
`COMMO\I
`
`COMMOV
`
`+5V
`
`This is arbe,5fi5|ig/@1fifiEE§tanggrg,e,lL@as been superseded by a later version of this standard.
`
`Aerohive - Exhibit 1025
`
`0087
`
`Aerohive - Exhibit 1025
`0087
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`22.7 Protocol Implementation Conformance Statement (PICS) proforma for clause 22,
`Reconciliation Sublayer (RS) and Media Independent Interface (Mll)29
`
`22.7.1 Introduction
`
`The supplier of a protocol implementation that is claimed to conform to IEEE Std 802.3u-1995, Reconcilia-
`tion Sublayer (RS) and Media Independent Interface (MII), shall complete the following Protocol Imple-
`mentation Conformance Statement (PICS) proforma.
`
`A detailed description of the symbols used in the PICS proforma, along with instructions for completing the
`PICS proforma, can be found in clause 21.
`
`22.7.2 Identification
`
`22.7.2.1 Implementation identification
`
`
`
`22.7.2.2 Protocol summary
`
`
`
`29Capyright releasefor PICSpmformas Users of this standard may fi'eely reproduce the PICS proforma in this annex so that it can be
`used for its intended purpose and may further publish the completed PICS.
`
`This is an7¢\rchive IEEE Standard.
`
`It has been superseded byogplgggrg/g§§iggEg(..tI{gsss;agag@rd.
`
`bit 1025
`
`
`
`Aerohive - Exhibit 1025
`0088
`
`

`
`CSMA/CD
`
`IEEE
`Std 802.3, 1998 Edition
`
`22.7.3 PICS proforma tables for reconciliation sublayer and media independent interface
`
`22.7.3.1 Mapping of PLS service primitives
`
` PL1
`
`Must produce FrameCheckEr-
`ror at MAC
`
`Response to RX_ER
`
`22.2.1.5
`
`M
`
`22.7.3.2 Mll signal functional specifications
`
`Subclause
`
`Status
`
`Value/Comment
`
`TX_CLK frequency
`
`TX_CLK duty cycle
`
`RX_CLK min high/low time
`
`RX_CLK synchronous to re-
`covered data
`
`RX_CLK frequency
`
`RX_CLK duty cycle
`
`RX_CLK source due to loss of
`signal
`
`RX_CLK transitions only
`while RX_DV de-asserted
`
`RX_CLK max high/low time
`following de-assertion of
`RX_DV
`
`TX_EN assertion
`
`TX_EN remains asserted
`
`TX_EN transitions
`
`TX_EN negation
`
`TXD<3:0> transitions
`
`TXD<3:0> effect on PHY
`while TX_EN is de-asserted
`
`TX_ER transitions
`
`TX_ER effect on PHY while
`TX_EN is asserted
`
`TX_ER effect on PHY while
`operating at 10 Mb/s, or when
`TX_EN is de-asserted
`
`25% of transmitted data rate
`(25 MHz or 2.5 MHz)
`
`35% to 65%
`
`35% of nominal period
`
`25% of received data rate
`(25 MHz or 2.5 MHz)
`
`35% to 65%
`
`Nominal clock reference
`(e.g., TX_CLK reference)
`
`max 2 times the nominal period
`
`On first nibble of preamble
`
`Stay asserted while all nibbles
`are transmitted over MII
`
`Synchronous with TX_CLK
`
`Before first TX_CLK after final
`nibble of frame
`
`Synchronous with TX_CLK
`
`No effect
`
`Synchronous with TX_CLK
`
`Cause PHY to emit invalid
`symbol
`
`No effect on PHY
`
`This is arbelgfigig/@1EfiEE§tanggrg,e,l1.flhas been superseded by a later version of this standard.
`
`Aerohive - Exhibit 1025
`
`0089
`
`Aerohive - Exhibit 1025
`0089
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`Subclause
`
`Value/Comment
`
`TX_ER implementation
`
`TX_ER pulled down if not ac-
`tively driven
`
`RX_DV transitions
`
`RX_DV assertion
`
`RX_DV negation
`
`RXD<3:0> effect on Reconcil-
`iation sublayer while RX_DV
`is de-asserted
`
`RX_ER assertion
`
`RX_ER transitions
`
`RX_ER effect on Reconcilia-
`tion sublayer while RX_DV is
`de-asserted
`
`CRS assertion
`
`CRS de-assertion
`
`CRS assertion during collision
`
`COL assertion
`
`COL remains asserted while
`collision persists
`
`COL response to SQE
`
`MDC min high/low time
`
`MDC min period
`
`22.2.2.9
`
`22.2.2.9
`
`22.2.2.9
`
`22.2.2.10
`
`22.2.2.10
`
`22.2.2.10
`
`22.2.2.ll
`
`22.2.2.11
`
`MDIO uses three-state drivers
`
`22.2.2.l2
`
`PHY pullup on MDIO
`
`STA pulldown on MDIO
`
`22.2.2.l2
`
`22.2.2.l2
`
`At MII of a PHY
`
`At MII of a repeater or MAC/
`RS only
`
`Synchronous with RX_CLK
`
`From first recovered nibble to
`final nibble of a frame per
`figure 22-6
`
`Before the first RX_CLK fol-
`lows the final nibble per
`figure 22-6
`
`No effect
`
`By PHY to indicate error
`
`Synchronous with RX_CLK
`
`No effect
`
`By PHY when either transmit
`or receive is NON-IDLE
`
`By PHY when both transmit
`and receive are IDLE
`
`Remain asserted throughout
`
`By PHY upon detection of col-
`lision on medium
`
`Assertion by PHY
`
`160 ns
`
`400 ns
`
`kQ :: 5% (L0 +5V)
`
`2 k9 5% (to ov)
`
`This is an74\rchive IEEE Standard.
`
`It has been superseded byogplgggrg/g§§iggEg(..tI{gsss;agag@rd.
`
`Aerohive - Exhibit 1025
`
`0090
`
`Aerohive - Exhibit 1025
`0090
`
`

`
`CSMA/CD
`
`22.7.3.3 Frame structure
`
`IEEE
`Std 802.3, 1998 Edition
`
`Subclause
`
`Value/Comment
`
`Format of transmitted frames
`
`22.2.3
`
`Nibble transmission order
`
`22.2.3
`
`Preamble7octets long
`
`22.2.3.2.l
`
`Preamble and SFD transmis-
`sion
`
`22.2.3.2.1
`
`Per figure 22-10
`
`Per figure 22-11
`
`l0l0l010l010l0lO 10101010
`10101010
`10101010 10101010
`10101010
`
`Per table 22-3
`
`number of octets is received
`
`Preamble and SFD reception
`
`22.2.3.2.2
`
`Per table 22-4, table 22-5
`
`N octets transmitted as 2N
`nibbles
`
`22.2.3.3
`
`Per figure 22-1 1
`
`Indication of excess nibbles
`
`22.2.3.5
`
`Frame contains non-integer
`
`22.7.3.4 Management functions
`
`Subclause
`
`Value/Comment
`
`Incorporate of basic register set
`
`Action on reset
`
`22.2.4.1.1
`
`Return 1 until reset completed
`
`22.2.4.1.1
`
`Reset completes within 0.5 s
`
`22.2.4.1.1
`
`Loopback mode
`
`Receive circuitry isolated from
`network in loopback mode
`
`22.2.4.1.2
`
`22.2.4.1.2
`
`Effect ofassertion ofTX_EN in
`loopback mode
`
`22.2.4.1.2
`
`Propagation of data in loop-
`back mode
`
`22.2.4.1.2
`
`Delay from TX_EN to RX_DV
`in loopback mode
`
`22.2.4.1.2
`
`Behavior of COL in loopback
`mode
`
`22.2.4.1.2
`
`Behavior of COL in loopback
`mode
`
`22.2.4.1.2
`
`Two 16-bit registers as Control
`register (register 0) and Status
`register (register 1)
`
`Reset the entire PHY including
`Control and Status to default
`value and 0.15 S 1
`
`Yes (when reset is done, 0.15 is
`self clearing)
`
`Whenever 0.14 is 1
`
`No transmission
`
`PHY accepts transmit data and
`return it as receive data
`
`Less than 512 BT
`
`De-asserted (for 0.7 = 0)
`
`If 0.7 = 1, see MF33 and MF34
`
`This is arbeigfigii/@1EfiEE§tanggrg,e,l1..has been superseded by a later version of this standard.
`
`Aerohive - Exhibit 1025
`
`009 1
`
`Aerohive - Exhibit 1025
`0091
`
`

`
`IEEE
`Std 802.3, 1998 Edition
`
`LOCAL AND METROPOLITAN AREA NETWORKS:
`
`Value of speed selection bit for
`single speed PHY
`
`Single speed PHY ignores
`writes to speed selection bit
`
`Auto-Negotiation enable
`
`Duplex mode, speed selection
`have no effect when Auto-Ne-
`gotiation is enabled
`
`PHY without Auto-Negotiation
`returns value of zero
`
`PHY without Auto-Negotiation
`ignores writes to enable bit
`
`Response to management
`transactions in power down
`
`Spurious signals in power
`down
`
`TX_CLK and RX_CLK stabi-
`lize within 0.5 s
`
`PHY Response to input signals
`while isolated
`
`High impedance on PHY out-
`put signals while isolated
`
`Response to management
`transactions while isolated
`
`Default value of isolate
`
`PHY without Auto-Negotiation
`returns value of zero
`
`PHY without Auto-Negotiation
`ignores writes to restart bit
`
`Restart Auto-Negotiation
`
`Return 1 until Auto-Negotia-
`tion initiated
`
`Auto-Negotiation not effected
`by clearing bit
`
`Value of duplex mode bit for
`PHYs with one duplex mode
`
`PHY with one duplex mode ig-
`nores writes to duplex bit
`
`Loopback not affected by du-
`plex mode
`
`Assertion of COL in collision
`test mode
`
`Subclause
`
`22.2.4.l.3
`
`22.2.4.1.3
`
`22.2.4.1.4
`
`22.2.4.l.4
`
`22.2.4.l.4
`
`22.2.4.1.4
`
`22.2.4.1.5
`
`22.2.4.1.5
`
`22.2.4.l.5
`
`22.2.4.1.6
`
`22.2.4.l.6
`
`22.2.4.1.6
`
`22.2.4.1.6
`
`22.2.4.l.7
`
`22.2.4.l.7
`
`22.2.4.1.7
`
`22.2.4.l.7
`
`22.2.4.l.7
`
`22.2.4.1.8
`
`22.2.4.1.8
`
`22.2.4.1.8
`
`22.2.4.1.9
`
`Value/Comment
`
`Set to match the correct PHY
`speed
`
`By setting 0.12 = 1
`
`If0.12=1, bits 0.13 and 0.8
`have no effect on link configu-
`ration
`
`Yes (if 1.3=o, then 0.12:0)
`
`Yes (if 1.3=0, 0.12 always = 0
`and cannot be changed)
`
`Remains active
`
`None (not allowed)
`
`Yes (after both bits 0.11 and
`0.10 are cleared to zero)
`
`NONE
`
`Yes (TX_CLK, RX_CLK,
`RX_DV, RX_ER, RXD<3:0>,
`COL, and CRS)
`
`Remains active
`
`0.l0=1
`
`0.9=0if1.3=0or0.12=0
`
`0.9 = 0, cannot be changed if
`1.3 = 0 or0.12 =0
`
`When 0.9= 1 if0.l2 = 1 and
`l.3=l
`
`0.9 is self clearing to 0
`
`Set 0.8 to match the correct
`PHY duplex mode
`
`Yes (0.8 remains unchanged)
`
`Yes (0.8 has no effect on PHY
`when 0.14 = 1)
`
`Within 512 BT after TX_EN is
`asserted
`
`This is anygtrchive IEEE Standard.
`
`It has been superseded byogplgggrg/g§§iggEg(..tI{g§s$;agag@rd.
`
`Aerohive - Exhibit 1025
`
`0092
`
`Aerohive - Exhibit 1025
`0092
`
`

`
`CSMA/CD
`
`De-assertion of COL in colli-
`sion test mode
`
`Subclause
`
`22.2.4.l.9
`
`Reserved bits written as zero
`
`22.2.4.l.l0
`
`Reserved bits ignored when
`read
`
`22.2.4.1.10
`
`PHY returns 0 in reserved bits
`
`22.2.4.l.l0
`
`Effect of write on status register
`
`Reserved bits ignored when
`read
`
`22.2.4.2
`
`22.2.4.2.6
`