Jake‘:Ieoisfiud19"-I91-IIEIs/qw00l/0l-ovsssda
`
`flNational Semiconductor
`
`PRELIMINARY
`November 1995
`
`DP83840
`
`10/100 Mb/s Ethernet Physical Layer
`
`General Description
`The DP83840 is a Physical Layer device for Ethernet
`10BASE-T and 100BASE-X using category 5 Unshielded,
`Type 1 Shielded and Fiber Optic cables.
`This VLSI device is designed for easy implementation of
`10/100 Mb/s Ethernet LANs. It interfaces to the PMD sub-
`layer through National Semiconductor’s DP83223 Twisted
`Pair Transceiver, and to the MAC layer through a Media
`Independent Interface (Mll), ensuring interoperability be-
`tween products from different vendors.
`The DP83840 is designed with National Semiconductor’s
`BiCMOS process. Its system architecture is based on the
`integration of several of National Semiconductor's industry
`proven core technologies as listed below:
`
`— 10BASE-T ENDEC/Transceiver module to provide the
`10 Mb/s IEEE 802.3 functions
`— Clock Recovery/Generator Modules
`Semiconductor’s leading FDDI product
`— FDDI Stream Cipher (Cyclone)
`— 100BASE-X physical coding sub-layer (PCS) and control
`logic that integrate the core modules into a dual speed
`Ethernet physical layer controller
`
`from National
`
`and
`
`Features
`compatib|e—ENDEC
`10BASE-T
`I IEEE
`802.3
`UTP/STP transceivers and filters built-in
`I IEEE 802.3u 100BASE-X compatib|e—support for 2 pair
`Category 5 UTP (100m), Type 1 STP and Fiber Optic
`Transceivers—Connects directly to the DP83223 Twist-
`ed Pair Transceiver
`I ANSI X3T12 TP-PMD compatible
`I IEEE 802.3u Auto-Negotiation for automatic speed
`selection
`I IEEE 802.3u compatible Media Independent Interface
`(Mll) with Serial Management Interface
`I Integrated high performance 100 Mb/s clock recovery
`circuitry requiring no external filters
`I Full Duplex support for 10 and 100 Mb/s
`I MII Serial 10 Mb/s output mode
`I Fully configurable node and repeater modes—a||ows
`operation in either application
`I Programmable loopback modes for easy system
`diagnostics
`I Flexible LED support
`I IEEE 1149.1 Standard Test Access Port and Boundary-
`Scan compatible
`I Small footprint 100-pin PQFP package
`
`System Diagram
`
`IOBASE-T
`
`
`I0 AND/OR 100 Mb/s
`ETHERNET MAC OR
`REPEATER/SWITCH
`PORT
`
`DP33840
`10/100 Mb/s
`ETHERNET PHYSICAL LAYER
`
`
`
`DP83223
`1 OOBASE-TX
`TRANSCEIVER
`
`MAGNETICS
`
`IOBASE-T
`AND
`IOOBASE-TX
`
`TL/F/12388-1
`
`
`
` CLOCKS
`
`STATUS
`LEDS
`
`U.S. Patents Pending
`TRI-STATE” is a registered trademark of National Semiconductor Corporation.
`
`©1996 National Semiconductor Corporation
`TL/F/12388
`RRD-B3OM36/Printed in u. s. A.
`http://www.nationa|.com
`
`Aerohive -
`
`Exhibit 1024
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`Aerohive - Exhibit 1024
`
`

`
`Block Diagram
`
`TEST
`ACCESS
`PORT
`
`LED 1-5
`
`F.hUEDDEENILA
`1SL.R09)EmA.GVNHAM0TDC
`
`CLOCK(S)
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`
`100BASE-X
`TRANSMITINTERFACE
`
`10BASE-T
`INTERFACE
`
`100BASE-X
`RECHVEINTERFACE
`
`TL/F/12388-2
`
`
`

`
`Table of Contents
`
`4.0 Registers
`4.1 Key to Defaults
`4.2 Basic Mode Control Register
`4.3 Basic Mode Status Register
`4.4 PHY Identifier Register #1
`4.5 PHY Identifier Register #2
`4.6 Auto-Negotiation Advertisement Register
`4.7 Auto-Negotiation Link Partner Ability Register
`4.8 Auto-Negotiation Expansion Register
`4.9 Disconnect Counter Register
`4.10 False Carrier Sense Counter Register
`4.11 Receive Error Counter Register
`4.12 Silicon Revision Register
`4.13 PCS Sub-Layer Configuration Register
`4.14 Loopback, Bypass and Receiver Error Mask
`Register
`4.15 PHY Address Register
`4.16 10BASE-T Status Register
`4.17 10BASE-T Configuration Register
`5.0 DP83840 APPLICATION
`
`5.1 Typical Board Level Application
`5.2 Layout Recommendations
`5.3 Plane Partitioning
`5.4 Power and Ground Filtering
`6.0 DC AND Ac SPECIFICATIONS
`
`6.1 Ratings and Operating Conditions
`6.2 DC Specifications
`6.3 AC Specifications
`7.0 PACKAGE DIMENSIONS
`
`GENERAL DESCRIPTION
`
`FEATURES
`
`SYSTEM DIAGRAM
`
`BLOCK DIAGRAM
`
`TABLE OF CONTENTS
`
`1.0 PIN CONNECTION DIAGRAM
`
`2.0 PIN DESCRIPTION
`2.1 Mll Interface
`2.2 100 Mb/s Serial PMD Interface
`2.3 10BASE-T Transceiver Module
`2.4 Clock Interface
`
`2.5 Device Configuration Interface
`2.6 LED Interface
`2.7 IEEE 1149.1 Interface
`2.8 PHY Address Interface
`2.9 Miscellaneous
`2.10 Power and Ground Pins
`
`2.11 Special Connect Pins
`3.0 FUNCTIONAL DESCRIPTION
`3.1 PCS Control
`
`3.2 MII Serial Management Register Access
`3.3 100BASE-X Transmitter
`3.4 100BASE-X Receiver
`3.5 Clock Generation Module
`
`3.6 100 Mb/s Clock Recovery Module
`3.7 10BASE-T Transceiver Module
`3.8 IEEE 1149.1 Controller
`
`3.9 IEEE 802.3u Auto-Negotiation
`3.10 Reset Operation
`3.11 Loopback Operation
`3.12 Alternative 100BASE-X Operation
`
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`
`
`
`

`
`
`
`1.0 Pin Connection Diagram
`
`c:
`D
`_
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`
`80 79 78 77 76 75 74 73 72 7170 69 68 67 66 G5 64 63 62 6160 59 58 57 56 55 54 53 52 51
`
`
`
`81
`CLK25M
`82
`TX_CLK
`83
`NC
`84
`REFVCC
`85
`REFGND
`86
`REFIN
`a7
`cow/cc
`88
`CGMGND
`89
`PHYAD[3]
`am 90
`TDI
`91
`
`TCLK
`“ST
`ms
`AN0
`IOVCC1
`IOGNDI
`1OBTSER
`
`BFALIGN
`BP4B5B
`
`93
`92
`94
`95
`96
`97
`98
`
`99
`
`50
`TDO
`49
`LBEN
`48
`RES_O
`47
`REPEATER
`46
`AN1
`45
`RES_0
`44
`RESET
`43
`RX_EN
`42 E
`41 m
`4-0
`|0GND2
`
`LED3
`38
`'°_V°°2
`5’
`37 E
`36 E
`35
`ocuo
`34
`X2
`33
`X1
`
`32
`31
`
`OVCC
`PLLVCC
`
`TL/F/12388-3
`
`10/100 Mb/s ETHERNET PHYSICAL LAYER
`
`100-PIN JEDEC METRIC PQFP
`
`10111213141516171819 20 2122 23 24 25 26 27 28 29 30
`
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`
`FIGURE 1. DP83840 Pin Connection Diagram
`
`httpz//www.nationa|.com
`
`4
`
`

`
`2.0 Pin Description
`The DP83840 pins are classified into the following interface categories (each interface is described in the sections that follow):
`MII INTERFACE
`LED INTERFACE
`100 Mb/s SERIAL PMD INTERFACE
`IEEE 1149.1 INTERFACE
`
`10 Mb/s INTERFACE
`CLOCK INTERFACE
`DEVICE CONFIGURATION INTERFACE
`
`PHY ADDRESS INTERFACE
`MISCELLANEOUS PINS
`POWER AND GROUND PINS
`
`SPECIAL CONNECT PINS
`
`2.1 Mll INTERFACE
`
`Signal Name
`TX_CLK
`
`Type
`
`Pin #
`
`\I\l\l\I
`
`\I-§
`
`\I03
`
`\IN
`
`O)\I
`
`cns
`(PHYAD[2I)
`
`Description
`TRANSMIT CLOCK: Transmit clock output from the DP83840:
`— 25 MHz nibble transmit clock derived from Clock Generator Module’s (CGM) PLL in
`100BASE-TX mode
`— 2.5 MHz transmit clock in 10BASE-T nibble mode
`— 10 MHz transmit clock in 10BASE-T serial mode
`
`TRANSMIT DATA: Transmit data input pins for nibble data from the Mll in 100 Mb/s or
`10 Mb/s nibble mode (25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s nibble mode).
`In 10 Mb/s serial mode, the TXD[0] pin is used as the serial data input pin. TXD[3:1] are
`ignored.
`
`TRANSMIT ENABLE: Active high input indicates the presence of valid nibble data on TXD[3:0]
`for both 100 Mb/s or 10 Mb/s nibble mode.
`
`In 10 Mb/s serial mode, active high indicates the presence of valid 10 Mb/s data on TXD[0].
`TRANSMIT ERROR: In 100 Mb/s mode, when this signal is high and TX_EN is active the
`HALT symbol is substituted for the actual data nibble.
`In 10 Mb/s mode, this input is ignored.
`In encoder bypass mode (BP_4B5B or BP_ALlGN) TX_ER becomes the TXD [4] pin, the
`fifth TXD data bit.
`
`MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/
`output serial interface which may be asynchronous to transmit and receive clocks. The
`maximum clock rate is 2.5 MHz.
`
`MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be
`sourced by the station management entity or the PHY. This pin requires a 4.7 kn pullup
`resistor.
`
`CARRIER SENSE: This pin is asserted high to indicate the presence of carrier due to receive
`or transmit activities in 10BASE-T or 100BASE-X Half Duplex modes.
`In Repeater, Full Duplex, or Loopback mode a logic 1 indicates presence of carrier due only to
`receive activity.
`This is also the PHY address sensing (PHYAD[2]) pin for multiple PHY applications—see
`Section 2.8 for more details.
`
`COLLISION DETECT: Asserted high to indicate detection of collision conditions in 10 Mb/s
`and 100 Mb/s Half Duplex modes. In 10BASE-T Half Duplex mode with Heartbeat asserted (bit
`4, register 1Ch), it is also asserted for a duration of approximately 1 ps at the end of
`transmission to indicate CD heartbeat.
`
`In Full Duplex mode this signal is always logic 0. There is no heartbeat function in this mode.
`RECEIVE CLOCK: Provides the recovered receive clock for different modes of operation:
`— 25 MHz nibble clock in 100 Mb/s mode
`— 2.5 MHz nibble clock in 10 Mb/s nibble mode
`— 10 MHz receive clock in 10 Mb/s serial mode
`I = '|'|'L/CMOS input 0 = 1'|'L/CMOS output 2 = TRI-STATE" output
`J = IEEE 1149.1 pin
`
`5
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`

`
`Description
`
`RECEIVE ERROR: Asserted high to indicate that an invalid symbol has been detected inside a
`received packet in 100 Mb/s mode.
`In a 5B/4B decoder bypass mode (BP_4B5B or BP_ALIGN modes), RX_ER becomes
`FtXD[4]. the fifth FtXD data bit of the 5B symbol.
`This is also the PHY address sensing (PHYAD[4]) pin for multiple PHY app|ications—see
`Section 2.8 for more details.
`
`RECEIVE DATA VALID: Asserted high to indicate that valid data is present on RXD[3:O].
`RECEIVE DATA: Nibble wide receive data (synchronous to RX_CLK—25 MHz for 100BASE-X
`mode, 2.5 MHz for 10BASE-T nibble mode). Data is driven on the falling edge of RX_CLK.
`In 10 Mb/s serial mode, the RXD[0] pin is used as the data output pin. RXD[3:1] are don't care.
`
`-#010101(.0ONO!
`
`2.0 Pin Description (Continued)
`2.1 Mll INTERFACE (Continued)
`
`Signal Name
`RX_ER
`(PHYAD[4])
`
`Type
`0, Z, J
`
`|,J
`
`RECEIVE ENABLE: Active high enable for receive signals FtXD[3:0], RX_CLK, RX_DV and
`RX_EFt. A low on this input tri-states these output pins. For normal operation in a node
`application this pin should be pulled high.
`I = '|'|'L/CMOS input 0 = 1'I'L/CMOS output Z = TRI-STATE output
`J = IEEE 1149.1 pin
`2.2 100 Mb/S SERIAL PMD INTERFACE
`
`Signal Name
`SPEED_10
`
`ENCSEL
`(PHYAD[1])
`
`Type
`O. J
`
`I/O, J
`
`LBEN
`(PHYAD[0])
`
`Description
`
`SPEED 10 Mb/s: Indicates 10 Mb/s operation when high. Indicates 100 Mb/s operation when
`low. This pin can be used to drive a low current LED to indicate 100 Mb/s speed if required.
`ENCODE SELECT: Used to select binary or MLT-3 coding scheme in the PMD transceiver (at
`the DP83223, logic high selects binary coding scheme and logic low selects MLT-3 coding
`scheme).
`This is also the PHY address sensing (PHYAD[1]) pin for multiple PHY appIications—see
`Section 2.8 for more details.
`
`LOOPBACK ENABLE: This pin should be connected to the Loopback Enable pin of a
`DP83223 100 Mb/s Transceiver:
`
`1 = Loopback enabled
`0 = Loopback disabled
`In 10 Mb/s modes, this output has no meaning.
`This is also the PHY address sensing (PHYAD[0]) pin for multiple PHY app|ications—see
`Section 2.8 for more details.
`
`TD-
`TD+
`SD-
`SD+
`RD-
`RD+
`
`16
`.5
`7
`
`o (ECL)
`
`I (ECL)
`
`I (ECL)
`
`TRANSMIT DATA: Differential ECL 125 Mb/s serialized transmit data outputs to the DP83223
`Twister.
`
`SIGNAL DETECT: Differential ECL signal detect inputs. Indicates that a signal is present at the
`DP83223 receive inputs as specified by the TP-PMD ANSI standard.
`
`RECEIVE DATA: Differential ECL 125 Mb/s receive data inputs.
`
`I = '|'|'L/GMOS input 0 = '|'|'L/CMOS output Z = TRI-STATE output
`
`J = IEEE 1149.1 pin
`
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`
`

`
`2.0 Pin Description (Continued)
`2.3 10 MbIS INTERFACE
`
`Signal NameE
`
`Description
`
`REG
`
`TXU —
`TXU "
`TXS —
`TXS ——
`FIXI —
`FIXI +
`
`EQUALIZATION RESISTOR: A resistor connected between this pin and GND or Vcc adjusts the
`equalization step amplitude on the 1OBASE-T Manchester encoded transmit data (TXU + / — or
`TXS + / —). Typically no resistor is required for operation with cable lengths less than 100m. Great
`care must be taken to ensure system timing integrity when using cable lengths greater than 100m.
`Refer to the IEEE 802.3u standard, Clause 29 for more details on system topology issues.
`The equations to calculate this resistor value are still under investigation. Currently, this value
`must be determined empirically.
`EXTENDED CABLE RESISTOR: A resistor connected between this pin and GND or Vcc adjusts
`the amplitude of the differential transmit outputs (TXU + / — or TXS+ / —). Typically no resistor is
`required for operation with cable lengths less than 100m. Great care must be taken to ensure
`system timing integrity when using cable lengths greater than 100m. Refer to the IEEE 802.3u
`standard, Clause 29 for more details on system topology issues.
`The equations to calculate this resistor value are still under investigation. Currently, this value
`must be determined empirically.
`UNSHIELDED TWISTED PAIR OUTPUT: This differential output pair is the filtered 1OBASE-T
`transmit data for UTP cable.
`
`SHIELDED TWISTED PAIR OUTPUT: This differential output pair is the filtered 1OBASE-T
`transmit data for STP cable.
`
`20
`21
`
`TWISTED PAIR RECEIVE INPUT: These are the differential 1OBASE-T receive data inputs for
`either STP or UTP.
`
`I = '|'|'L/CMOS input 0 = 1'l'L/CMOS output Z = TRI-STATE output
`2.4 CLOCK INTERFACE
`
`J = IEEE 1149.1 pin
`
`Signal NameE
`FIEFIN
`
`CLK25M
`
`OSCI N
`
`X2
`
`X1
`
`I = '|'|'L/CMOS input 0 = 1'l'L/CMOS output Z = TRI-STATE output
`
`Description
`REFERENCE INPUT: 25 MHz TTL reference clock input. Can be supplied from an external
`oscillator module or from the CLK25M output.
`25 MHz CLOCK OUTPUT: Derived from the 50 MHz OSCIN input.
`OSCILLATOR INPUT: 50 MHz : 50 ppm external 'l'l'L oscillator input. If not used, pull down to
`GND with a 4.7 K!) resistor.
`
`CRYSTAL OSCILLATOR OUTPUT: External 20 MHz i 0.005% crystal connection. Used for
`1OBASE-T timing. When using an external 20 MHz oscillator connected to X1, leave this pin
`unconnected.
`
`CRYSTAL OSCILLATOR INPUT: External 20 MHz 1 0.005% crystal connection. Used for
`1OBASE-T timing and Auto-Negotiation. If not used, this pin should be tied to Vcc either directly or
`via a pull-up resistor—typica|Iy 4.7 kn. The DP83840 detects this condition, enables the internal
`+ 2.5 divider and switches the 10 Mb/s and Auto-Negotiation circuitry to the internally derived
`20 MHz clock.
`
`J = IEEE 1149.1 pin
`
`7
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`
`
`

`
`2.0 Pin Description (Continued)
`2.5 DEVICE CONFIGURATION INTERFACE
`
`ESignal Name
`ANO
`
`Description
`ANO: This is a three level input pin (i.e., 1, M, 0) that works in conjunction with the AN1 pin to
`control the forced or advertised operating mode of the DP8384O according to the following table.
`The value on this pin is set by either connecting the input to GND or Vcc (0 or 1) or leaving it
`unconnected (M). The unconnected state, M, refers to the mid level (Vcc + 2) set by internal
`resistors (~ 3 kn). This value is latched into the DP83840 at power-up/reset. See Section 3.9 for
`more details.
`AN1
`AND
`0
`M
`
`Forced Mode
`
`1OBASE-T, Half-Duplex without Auto-Negotiation
`1OBASE-T, Full Duplex without Auto-Negotiation
`100BASE-TX, Half-Duplex without Auto-Negotiation
`100BASE-TX, Full Duplex without Auto-Negotiation
`Advertised Mode
`
`M 0 1
`
`1 M M
`
`AN1
`M
`
`ANO
`M
`
`0
`1
`0
`1
`
`All capable (i.e. Full Duplex for 1OBASE-T and 100BASE-TX) advertised via Auto-
`Negotiation
`1OBASE-T, Half-Duplex advertised via Auto-Negotiation
`O
`1OBASE-T, Full Duplex advertised via Auto-Negotiation
`0
`100BASE-TX, Half-Duplex advertised via Auto-Negotiation
`1
`100BASE-TX, Full Duplex advertised via Auto-Negotiation
`1
`AN1: This is a three level input pin (i.e., 1, M, O) that works in conjunction with the AND pin to
`control the forced or advertised operating mode of the DP83840 according to the table given in
`the ANO pin description above. The value on this pin is set by either connecting the input to GND
`or Vcc (0 or 1) or leaving it unconnected (M). This value is latched into the DP8384O at power-up/
`reset. See Section 3.9 for more details.
`
`REPEATER
`
`REPEATER/NODE MODE: Selects REPEATER mode when set high and NODE mode when set
`low. In REPEATER mode or NODE mode with Full Duplex configured, the Carrier Sense (CRS)
`output from the DP8384O is asserted due to receive activity only. In NODE mode, and not
`configured for Full Duplex operation, CRS is asserted due to either receive and transmit activity.
`At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kn) is
`latched to bit 12 of the PCS Configuration Register, address 17h.
`SERIALINIBBLE SELECT:
`
`1031-SER
`
`10 Mb/s Serial Operation:
`When set high, this input selects serial data transfer mode. Manchester encoded transmit and
`receive data is exchanged serially with a 10 MHz clock rate on the least significant bits of the
`nibble-wide Mll data buses, pins TXD[0] and RXD[0] respectively. This mode is intended for use
`with the DP83840 connected to a device (MAC or Repeater) that has a 10 Mb/s serial interface.
`Serial operation is not supported in 100 Mb/s mode, so for 100 Mb/s this input is ignored.
`10 and 100 Mb/s Nibble Operation:
`When set low, this input selects the Mll compliant nibble data transfer mode. Transmit and receive
`data is exchanged in nibbles on the TXD[3:0] and RXD[3:0] pins respectively.
`At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kn) is
`latched to bit 9 of the 1OBASE-T Status Register, address 1Bh.
`BYPASS ALIGNMENT: Allows 100 Mb/s transmit and receive data streams to bypass all of the
`transmit and receive operations when set high. Refer to Figures 4 and 5.
`At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kn) is
`latched into bit 12 of the Loopback, Bypass and Receiver Error Mask Register, address 18h.
`I = '|'|'L/CMOS input 0 = '|'|'L/CMOS output Z = TRI-STATE output
`J = IEEE 1149.1 pin
`
`BPALIGN
`
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`

`
`2.0 Pin Description (Continued)
`2.5 DEVICE CONFIGURATION INTERFACE (Continued)
`
`Signal NameE
`BP4B5B
`I, J
`
`Description
`BYPASS 4B5B ENCODERIDECODER: Allows 100 Mb/s transmit and receive data streams to
`bypass the 4B to 5B encoder and 5B to 4B decoder circuits when set high.
`At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kn) is
`latched into bit 14 of the Loopback, Bypass and Receiver Error Mask Register, address 18h.
`BYPASS SCRAMBLERIDESCRAMBLER: Allows 100 Mb/s transmit and receive data streams to
`bypass the scrambler and descrambler circuits when set high.
`At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4.7 kn) is
`latched into bit 13 of the Loopback, Bypass and Receiver Error Mask Register, address 18h.
`I = 'I'I'L/GMOS input 0 = 1'I'L/CMOS output 2 = TRI-STATE output
`J = IEEE 1149.1 pin
`2.6 LED INTERFACE
`
`I, J
`
`These outputs can be used to drive LEDs directly, or can be used to provide status information to a network management
`device. Refer to Figure 12 for the LED connection diagram. An LED indication of 100 Mb/s operation can be obtained by
`connecting a low current LED (and its associated resistor) to the SPEED_10 pin (54). See Section 2.2.
`
`Signal NameE
`D1
`LE
`0, J
`42
`
`Description
`TRANSMIT LED: Indicates the presence of transmit activity for 10 Mb/s and 100 Mb/s operation.
`Active low.
`
`If bit 2 (LED1_MODE) of the PCS Configuration Register (address 17h) is set high, then the LED1
`pin function is changed to indicate the status of the Disconnect Function as defined by the state
`of bit 5 (CON_STATUS) in the PHY address register (address 19h).
`The DP8384O incorporates a “monostable” function on the LED1 output. This ensures that even
`minimum size packets generate adequate LED ON time to be visible.
`RECEIVE LED: Indicates the presence of any receive activity (CRS active) for 10 Mb/s and
`100 Mb/s operation. Active low.
`The DP83840 incorporates a “monostable" function on the LED2 output. This ensures that even
`minimum size packets generate adequate LED ON time to be visible.
`
`0, J
`
`41
`
`LED3 E LINK LED: Indicates Good Link status for 10 Mb/s and 100 Mb/s operation. Active low.
`LED4
`O, J
`37
`POLARITY/FULL DUPLEX LED: Indicates Good Polarity status for 10 Mb/s operation. Indicates
`Full Duplex mode status for 100 Mb/s operation. Active low.
`If bit 1 (LED4_MODE) in the PCS Configuration Register (address 17h) is set high, the LED4 pin
`function is changed to indicate Full Duplex mode status for 10 Mb/s and 100 Mb/s operation.
`COLLISION LED: Indicates the presence of collision activity for 10 Mb/s and 100 Mb/s
`operation. This LED has no meaning for 10 Mb/s or 100 Mb/s Full Duplex operation. Active low.
`I = '|'|'L/GMDS input 0 = 'I'I'L/CMOS output Z = TRI-STATE output
`J = IEEE 1149.1 pin
`2.7 IEEE 1149.1 INTERFACE
`
`LED5
`
`O, J
`
`The IEEE 1149.1 Standard Test Access Port and Boundary Scan (sometimes referred to as JTAG) interface signals allow
`system level boundary scan to be performed.
`
`Signal NameE
`Descrlptlon
`TDO
`0, 2
`TEST DATA OUTPUT: Serial instruction/test output data for the IEEE 1149.1 scan chain.
`1“ IfBoundary-Scan is not implementedthis pin should be left unconnected (NC).
`TDI Z TEST DATA INPUT: Serial instruction/test input data for the IEEE 1149.1 scan chain.
`S
`TEST RESET: An asynchronous low going pulse will reset and initialize the IEEE 1149.1 test
`circuitry.
`If Boundary-Scan is not implemented, this pin should be left unconnected (NC) since it has an
`internal pull-up resistor (10 kn).
`I = 'I'I'L/GMOS input 0 = 1'I'L/CMOS output 2 = TRI-STATE output
`J = IEEE1149.1 pin
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`2.0 Pin Description (Continued)
`2.7 IEEE 1149.1 INTERFACE (Continued)
`
`Signal NameE
`
`Description
`TEST CLOCK: Test clock for the IEEE 1149.1 circuitry.
`This pin should be pulled to GND with an appropriate resistor (10 kn).
`TEST MODE SELECT: Control input to the IEEE 1149.1 test circuitry.
`If Boundary-Scan is not implemented, this pin should be left unconnected (NC) since it has an
`internal pull-up resistor (1 0 kn).
`I = '|'|'L/GMOS input 0 = '|'|'L/CMOS output Z = TRI-STATE output
`J = IEEE 1149.1 pin
`2.8 PHY ADDRESS INTERFACE
`
`It should be noted that while PHYAD[4:0] provides up to 32 unique PHY address options, an address selection of all zeros
`(00000) will result in a PHY isolation condition. See the Isolate bit description in the BMGR, address 00h, Section 4.2.
`
`Signal Name
`
`LBEN
`(pl-|YAD[o])
`
`Type
`
`I/O, J
`
`ENCSEL
`(pi-|YAD[1])
`
`I/O, J
`
`CRS
`(P|-|YAD[2])
`
`PHYAD[3]
`
`Description
`
`PHY ADDRESS [O]: PHY address sensing pin (bit 0) for multiple PHY applications. PHY
`address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kn.) to this
`pin as required.
`The pull-up/pull-down status of this pin is latched into the PHYAD address register (address
`19h) during power up/reset.
`This pin is also the Loopback Enable output pin (LBEN) for the 100 Mb/s Serial PMD Interface.
`See Section 2.2 for more details.
`
`PHY ADDRESS [1]: PHY address sensing pin (bit 1) for multiple PHY applications. PHY
`address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kn.) to this
`pin as required.
`The pull-up/pull-down status of this pin is latched into the PHYAD address register (address
`19h) during power up/reset.
`This pin is also the Encode Select output pin (ENCSEL) for the 100 Mb/s Serial PMD Interface.
`See Section 2.2 for more details.
`
`PHY ADDRESS [2]: PHY address sensing pin (bit 2) for multiple PHY applications. PHY
`address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kn) to this
`pin as required.
`The pull-up/pull-down status of this pin is latched into the PHYAD address register (address
`19h) during power up/reset.
`This pin is also the Carrier Sense output pin (CRS) for the Mll Interface. See Section 2.1 for
`more details.
`
`PHY ADDRESS [3]: PHY address sensing pin (bit 3) for multiple PHY applications. PHY
`address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kn.) to this
`pin as required.
`The pull-up/pull-down status of this pin is latched into the PHYAD address register (address
`19h) during power up/reset.
`Since this input does not have a dual function, it is a good choice for providing a non-zero PHY
`address to the DP83840.
`
`RX_ER
`(PHYAD[4])
`
`I/O, Z. J
`
`PHY ADDRESS [4]: PHY address sensing pin (bit 4) for multiple PHY applications. PHY
`address sensing is achieved by strapping a pull-up/pull-down resistor (typically 10 kn.) to this
`pin as required.
`The pull-up/pull-down status of this pin is latched into the PHYAD address register (address
`19h) during power up/reset.
`This pin is also the Receive Error output pin (RX_ER) for the Mll Interface. See Section 2.1 for
`more details.
`I = '|'|'L/CMDS input 0 = '|'|'L/CMOS output Z = TRI-STATE output
`
`J = IEEE 1149.1 pin
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`2.0 Pin Description (Continued)
`2.9 MISCELLANEOUS
`
`Signal NameE
`
`Description
`RESET: Active high input that initializes the DP83840.
`I = '|'|'L/CMOS input 0 = 1'|'L/CMOS output 2 = TRI-STATE output
`J = IEEE 1149.1 pin
`2.10 POWER AND GROUND PINS
`The power (Vcc) and ground (GND) pins of the DP83840 are grouped in pairs into four categories—TTL/CMOS Input pairs,
`TTL/CMOS Output and I/O pairs, 10 Mb/s pairs and 100 Mb/s pairs. Great care must be taken with the layout of the power and
`ground supplies to this device. Each of the four categories of pairs should have its own isolated supplies. More details of the
`power and ground layout requirements are given in Sections 5.2, 5.3 and 5.4.
`
`Pln Names Descrlptlon
`GROUP A—1TLlCMOS INPUT SUPPLY PAIRS
`
`IOVCC1, IOG ND1
`
`lOVcc2, lOGND2
`IOVCC3, IOGNDS
`PCSVCC, PCSGND
`GROUP B—1TL/CMOS OUTPUT AND IIO SUPPLY PAIRS
`
`|OVcc4, IOGND4
`RCLKGND
`IOVCC5, |OGND5
`IOVCC5, |OGND6
`REFVCC, REFGND
`GROUP C-10 Mb/s SUPPLY PAIRS
`
`RXVCC, RXGND
`TDVCC, TDGND
`PLLVcc, PLLGND
`ovcc, OGND
`GROUP D—100 Mb/s SUPPLY PAIRS
`
`TTL lnputlOutput Supply #1
`
`TTL Input/Output Supply #2
`TTL Input/Output Supply #3
`Physical Coding Sublayer Supply
`
`TTL Input/Output Supply #4
`Receive Clock Ground, No Paired Vcc
`TTL Input/Output Supply #5
`TTL lnputlOutput Supply #6
`25 MHz Clock Supply
`
`Receive Section Supply
`Transmit Section Supply
`Phase Locked Loop Supply
`Internal Oscillator Supply
`
`OSCGND
`9, 10
`ANAVcc, ANAGND
`12, 11
`CRMVCC, CRMGND
`15
`ECLVCC
`87, 88
`CGMVCC, CGMGND
`I = '|'|'L/CMOS input 0 = 1'|'L/CMOS output 2 = TRI-STATE output
`2.11 SPECIAL CONNECT PINS
`
`External Oscillator Input Ground—No Paired Vcc
`Analog Section Supply
`Clock Recovery Module Supply
`ECL Outputs Supply
`Clock Generator Module Supply
`J = IEEE 1149.1 pin
`
`Signal NameE
`NC
`13
`14
`83
`
`Description
`NO CONNECT: These pins are reserved for future use. Leave them unconnected (floating).
`
`RES_O
`
`4
`45
`
`RESERVED_0: These pins are reserved for future use. Connect them to the nearest ground
`plane. For future upgradability, connect these pins to GND via 00. resistors.
`
`J
`
`RES_O
`
`RESERVED_0: These pins are reserved for future use. Connect them to the nearest ground
`48
`plane. For future upgradability, connect these pins to GND via 0.0. resistors.
`90
`I = ‘|‘|'L/CMOS input 0 = ‘ITL/CMOS output 2 = TRI-STATE output
`J = IEEE 1149.1 pin
`
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`3.0 Functional Description
`The DP83840 10/100 Mb/s Ethernet Physical Layer inte-
`grates a 100BASE-T Physical Coding Sub-layer (PCS) and a
`complete 10BASE-T module in a single chip. It provides a
`standard Media Independent Interface (MII) to communicate
`between the Physical Signaling and the Medium Access
`Control (MAC) layers for both 100BASE-X and 10BASE-T
`operations.
`It interfaces to a 100 Mbls Physical Medium
`Dependent (PMD) transceiver, such as the DP83223.
`The 100BASE-X section of the device consists of the follow-
`ing functional blocks:
`0 Transmitter
`0 Receiver
`0 Clock Generation Module (CGM)
`0 Clock Recovery Module (CRM)
`the
`The 10BASE-T section of
`the device consists of
`10 Mb/s transceiver module with filters and an ENDEC
`module.
`The 100BASE-X and 10BASE-T sections share the follow-
`ing functional blocks:
`0 PCS Control
`0 Mll Registers
`0 IEEE 1149.1 Controller
`0 IEEE 802.3u Auto-Negotiation
`Each of these functional blocks is described below.
`
`3.1 PCS CONTROL
`The IEEE 802.3u 100BASE-X Standard defines the Physical
`Coding Sublayer (PCS) as the transmit, receive and carrier
`sense functions. These functions within the DP83840 are
`controlled via external pins and internal registers via the Mll
`serial management interface.
`
`3.1.1 100BASE-X Bypass Options
`The DP83840 incorporates a highly flexible transmit and re-
`ceive channel architecture. Each of the major 100BASE-X
`transmit and receive functional blocks of the DP83840 are
`selectively bypassable to provide increased flexibility for
`various applications.
`3.1.1.1 Bypass 4B5B and 5B4B
`The 100BASE-X 4B5B symbol encoder in the transmit
`channel and the 100BASE-X 5B4B symbol decoder in the
`receive channel may be bypassed by setting the BP_4B5B
`bit in the LBREMR (bit 14, register address 18h). The de-
`fault value for this bit is set by the BP4B5B pin 100 at pow-
`er-up/reset.
`
`3.1.1.2 Bypass Scrambler and Descrambler
`The 100BASE-X scrambler in the transmit channel and the
`100BASE-X descrambler in the receive channel may be by-
`passed by setting the BP_SCR bit in the LBREMR (bit 13,
`register address 18h). The default value for this bit is set by
`the BPSCR signal (pin 1) at power-up/reset.
`3.1.1.3 Bypass NRZI Encoder and Decoder
`The 100BASE-X NRZI encoder in the transmit channel and
`the 100BASE-X NRZI decoder in the receive channel may
`be bypassed by setting the NRZl_EN bit in the PCR (bit 15.
`register address 17h). The default for this bit is a 1, which
`enables the NRZI encoder and decoder.
`
`3.1.1.4 Bypass Align
`The 100BASE-X transmit channel operations (4B5B symbol
`encoder, scrambler and NRZ to NRZI) and the 100BASE-X
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`receive channel operations (NRZI to NRZ, descrambler and
`4B5B symbol decoding) may all be bypassed by setting the
`BP_ALIGN bit
`in the LBREMR (bit 12, register address
`18h). The default value for
`this bit
`is set by the
`BP_ALlGN signal (pin 99) at power-up/reset.
`The bypass align function is intended for those repeater ap-
`plications where none of the transmit and receive channel
`operations are required.
`3.1.2 Repeater Mode
`The DP83840 Carrier Sense (CRS) operation depends on
`the value of the REPEATER bit in the PCR (bit 12, register
`address 17h). When set high, the CRS output (pin 66) is
`asserted for receive activity only. When set low, the CRS
`output is asserted for either receive or transmit activity.
`The default value for this bit is set by the REPEATER pin 66
`at power-up/reset.
`3.1.3 Mll control
`
`The DP83640 has 3 basic MII operating modes:
`3.1.3.1 100 Mbls Operation
`For 100 Mb/s operation, the MII operates in nibble mode
`with a clock rate of 25 MHz. This clock rate is independent
`of bypass conditions.
`In normal
`(non-bypassed) operation the MII data at
`RXD[3:0] and TXD[3:0]
`is nibble wide.
`In bypass mode
`(BP_4B5B or BP_AL|GN set) the MII data takes the form
`of 5-bit symbols. The lowest significant 4 bits appear on
`TXD[3:0] and RXD[3:0] as normal, and the most significant
`bits (TXD[4] and RXD[4]) appear on the TX_ER and
`RX_ER pins respectively.
`3.1.3.2 10 Mbls Nibble Mode Operation
`For 10 Mb/s nibble mode operation, the MII clock rate is
`2.5 MHz. The 100BASE-X bypass functions do not apply to
`10 Mb/s operation. This is the default 10 Mb/s mode of
`operation.
`
`3.1.3.3 10 Mb/s Serial Mode Operation
`For applications that have external ENDECs for 10 Mb/s
`operation, the DP83840 accepts Manchester encoded seri-
`al data on the TXD[0] input and provides Manchester en-
`coded serial data output on RXD[0] with a clock rate of
`10 MHz.
`
`This mode is selected by setting the 10BT_SER bit in the
`10BTSR (bit 9, register address 1Bh). The default value for
`this bit is set by the 10BTSER pin 98 at power-up/reset.
`3.2 MII SERIAL MANAGEMENT REGISTER ACCESS
`
`The MII specification defines a set of thirty-two 16-bit status
`and control registers that are accessible through the serial
`management data interface pins MDC and MDIO. The
`DP83840 implements all the required Mll registers and a
`subset of optional registers. The registers are fully de-
`scribed in Section 4. The serial management access proto-
`col is described below.
`
`3.2.1 Serial Management Access Protocol
`The serial control interface consists of two pins, Manage-
`ment Data Clock (MDC) and Management Data lnput/Out-
`put (MDIO). MDC has a maximum clock rate of 2.5 MHz.
`The MDIO line is bi-directional and may be shared by up to
`32 devices. The MDIO frame fonnat is shown in Table I.
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`
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`
`3.0 Functional Description (Continued)
`The MDIO pin requires a pull-up resistor (4.7 kn) which,
`during IDLE condition, will pull MDIO high. Prior to initia