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`FIG. 13
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`‘I310
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`RECORD PROGRAM MODE
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`CHOOSE DAY
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`CHOOSE TIME
`
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`
`CHOOSE CHANNEL
`
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`
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`(19) Q '
`
`Européiisches Paientarnt
`
`European Patent Oifice
`
`llllilillllllllllllllllllillilllfllllllilillllflilllllillllllllilllll
`
`Office européen des brevets
`
`(11)
`
`EP 0 594 241 B1
`
`(12)
`
`EUROPEAN PATENT SPECIFICATION
`
`(45) Dale of publication and mention
`of the grant of the patent:
`06.05.1999 Bulletin I999.f18
`
`(21) Application number: 932028715
`
`(22) Date oi filing: 12.10.1993
`
`(51) IntCI.5: GDEF 3106, GOSF 5J'O6,
`
`GOBF 7/00, HO-4N 5/44,
`H04N 5/45
`
`(54) Arrangement for storing an information signal in a memory and retrieving the information
`signal trorn said memory
`
`Ge-rat zur Speicherung eines Datensignals in einem Speicher und zurwiedergabe des Datensignals
`aus diesern Speicher
`
`Appareii de mémorisalion d'un signal rfinformation dans une rnémoire et de recouvrement du signal
`d'iniormation de la mémoire en question
`
`(B4) Designated Contracting States:
`AT DE FR GB
`
`(30) Priority: 19.10.1992 EP 92203191
`
`(43) Date oi publication of application:
`2104.1 994 Bulletin 1994117
`
`(73) Proprietor Koninklijke Philips Electronics N.V.
`5621 BA Eindhoven (NL)
`
`(72) Inventors:
`- Thornason. Graham (5.,
`do INT. OCTROOIBUHEAU E.V.
`
`NL-5655 Eindhoven (NL)
`
`' Van Loon, Paul M.,
`GIDINT. OCTFIOOIBUFIEAU B.V.
`
`NL-5656 Eindhoven (NL)-
`
`Representative.
`van der Kruk, Willem Leonardus el al
`INTEHNATIDNAAL OE.‘-TFIOOIBUFIEAU B.V.,
`Prot. Holstlaan 6
`
`5655 .AA Eindhoven {NL)
`
`References cited:
`
`W0-A-9D!OB999
`
`W0-A-91!13695
`
`COMPUTER DESIGN, Vol.25, no.6, March 1986,
`LITTL ETON, MASSACHUSETTS US pages 87- B2
`WINTERSTEIN ‘CACHE DESIGN BOOSTS SMD
`DISK DRIVE PERFORMANCE‘
`
`EP0'594241B1
`
`Note: Within nine months lrorn the publication ot the mention ol the grant ol the European patent, any person may give
`notice to the European Patent Office 01 opposition to the European patent granted. Notice oi opposition shall be filed in
`a written reasoned statement. It shall not be deemed to have been tiled until the opposition lee has been paid. (Art.
`99(1) European Patent Convention).
`
`TIVO 454228
`
`306
`
`

`

`EP 0 594 241 B1
`
`2
`
`Description
`
`[0001] The invention relates to an arrangement for
`storing an inlormation signal in a memory and retrieving
`the information signal lrom said memory. the arrange-
`ment including the memory, an input terminal tor receiv-
`ing the inlormation signal, an output terminal for supply-
`ing a delayed version ol the inlormatton signal, an input
`butler memory, having an input coupled to the input ter-
`minal and an output coupled to an input of said memory,
`and an output butler memory having an input coupled
`to the output or said memory and an output coupled to
`said output terminal.
`{c002} Published international patent application no.
`WO91I13695 discloses th temporary storage ol a vid-
`eo signal in a memory. Using this known arrangement,
`an information signal can be stored in the memory and
`an irtlorrnation signal previously stored in said memory
`can be retrieved simultaneously trom said memory. The
`memory can be in the lorrn ol an optical disk or a mag-
`netic disk, such as a hard disk or a disk-array. The ar-
`rangement can be used in a television apparatus or a
`videorecorder so as to store a video signal in the mem-
`ory.
`[0003] One application of the arrangement is where
`live television signal transmissions are continuously re-
`corded and a history is maintained as iar back as the
`extent ol the memory will permiL For some applications,
`the memory capacity ot the memory can be such that it
`permits the storage of a video signal having a length of
`a few minutes. For otherapplications a memory capacity
`corresponding to a length of about 15 minutes is con-
`sidered a minimum practical amount.
`[0004] The arrangement otters a number ol interest-
`ing leatures to a user.
`[0005]
`individual choice or the time at which a pro-
`gram is watched. For example, suppose at ten past eight
`the viewer wants to start watching the eight o'clock news
`(trom the beginning. ot course). Using the arrangement,
`provided the right channel has been monitored. the
`viewer lumps back ten minutes in time, as it were. and
`watches the news trom the start. Unlike the case where
`
`the programme is recorded on a conventional video re-
`corder, the viewer does not have to wait until the pro-
`gram has finished belore watching it.
`[0006] Continuity alter an interruption. it the viewer is
`interrupted while watching a programme, tor example
`by a telephone call or a call at the door, he can resume
`watching the program trom the point at which he was
`interrupted. This lunctionality is not possible with a con-
`venlional video-recorder.
`
`[0007] A practical solution to program overlap. Sup-
`pose a programme on one channel doesn't finish until
`ten minutes alter the start ol a programme on another
`channel. The prior art permits one to watch both pro-
`grammes without the use ol a video recorder. During the
`lirst programme, the viewer ensures that the channel ol
`the second programme is being monitored. Alter the first
`
`programme has ended, the viewer switches to the other
`channel and jumps back to the start oi the programme.
`An important advantage over using a video recorder is
`that one does not have to wait until the recording has
`linished belore the programme can be watched.
`[0003]
`individual replays, including slow motion. The
`viewer can see a replay ol an event just seen, (or just
`missed, or not
`fully understood) and then continue
`watching the programme trom the point where the re-
`play was started. Moreover. the replays can be watched
`in slow motion.
`
`[0009] Belated decision to record on video recorder
`possible. A viewer may decide after watching a pro-
`gramme lor ten minutes that the programme is worth
`recording onto video. With the arrangement. he can ret-
`rospectively start video-recording. whilst continuing to
`watch the programme live.
`[0010] Additional lealures oi the arrangement are:
`[0011] A means ol accelerating the viewing ol a his-
`torical programme. ll the viewer is not watching live, a.
`9. due to a later programme start or an interruption, he
`can catch up with the live broadcast by accelerating the
`playback. An acceleration lactor or a few per cent is
`practically unnoticed by the viewer. The circuitry (disk
`read-out. demullipleiring, data decompression. dfa con-
`version etc.) must be capable ol processing the data at
`the accelerated rate. The sound can be specially proc-
`essed so that the speed is accelerated without an undue
`increase in tone.
`
`[0012] A means oi last-accelerating over a historical
`programme. In this case not all television picture data is
`necessarily processed - some may be skipped and not
`be passed on tor demutliplexirig and decompression.
`[0013] A test reverse lunction.
`[0014] A picture-in-picture (PI P) processing unit to
`enable combinations ol live and historical programmes
`to be displayed using picture~in-picture lormals.
`[0015]
`in order to enable an uninterrupted storage of
`a live television programme in the main memory. and
`enable an uninterrupted and simultaneous retrieval of
`the historical programme from the rrrain memory. an in-
`put butler memory and an output butler memory are
`present. Data arriving tor storage in the main memory,
`whilst the main memory is temporarily busy tor another
`operation. will be stored in the input butler memory. and
`will be stored at a later moment in the main memory by
`retrieving the data trom the input butter memory. Data
`will also be requested regularly trom the main memory
`to be displayed on a TV screen as a historical pro-
`gramme. Again, the main memory may be temporarily
`busy for another operation, so data must be readily
`available in the output butler memory, so as to provide
`continuity oi viewing lor the user.
`[0016] The invention as claimed in claim 1 provides
`for an imp rovemenl in relation to the memories included
`in the arrangement_ For that purpose, the input butter
`memory and the output butler memory are combined in-
`to one single butter memory.
`
`TIVO 454229
`
`307
`
`

`

`EP 0 594 241 B1
`
`[0017] The invention is based on the lollowing recog-
`nition. In an ideal operation ol the input butter memory.
`the control oi the data transler through the input butter
`memory should be such that. in order to absorb a max-
`imum amount ol data without a lransler ol data trom the
`input buttermernory lo the main memory, the input butler
`memory should be empty. Further, in an ideal operation
`of‘ the output butler memory.
`the control ol the data
`transter through the output butler memory should be
`such that. in order to provide a maximum amount oi data
`to be displayed on the screen without a transler ol data
`trom the main memory to the output bufler memory, the
`output butler memory should be lull. These require-
`ments olter the possibility to combine the input butler
`memory and the oulp Lrl butler memory into one shared
`memory, to be used as efficiently as possible under the
`administration realized by a microprocessor.
`[0018] The invention is specillcaliy usalul in the situ-
`ation where the main memory is a hard-disk arrange-
`ment. and where the hard-disk arrangement has a sin-
`gle magnetic head for storing the information signal on
`and retrieving the information signal lrom the hard disk
`included in the hard—disk arrangement. It should howev-
`er be noted that also in disk arrangements having more
`than one head. situations can occur where an uninter-
`rupted storage on or retrieval from the disk is not possi-
`ble. such as in the case where a head has to jump to
`another storage location and inlorrnalion llow interrup-
`tion can not be corrected by another head. Further, it
`should be noted that. where the description discloses
`the storage o! a single information signal in and retrieval
`ol said inlorrnation signal lrom the main memory.
`it is
`equally well possible to apply the inventive concept to
`the storage and retrieval oi a number of two or more
`inlorrnation signals inrlrom the main memory. eg. de-
`rived trom dillerent program channels.
`[0019] The invention will be lunher described in the
`following figure description. in which
`
`ligure 1 discloses an embodiment ol the arrange-
`rnenl.
`ligure 2 discloses a more simplified embodiment.
`ligure 3 discloses a butter memory in the lon'n oi a
`FIFO, and
`ligure 4 discloses a butter memory in the term ot a
`reversible FIFO.
`
`Figure 1 discloses an embodiment ot the ar-
`[0020]
`rangement. One or more television signals lirsl pass
`through a channel selector 1 . which selects which trans-
`missions, according to their channel. are to be stored.
`and which transmissions. accordingto their channel. are
`required tor live display. The transmissions which are
`selected to be stored are digitized by means oi aid (an-
`alogue lo digital} conveners 2 The digital data is then
`compressed in real time by a data compressor 3. The
`output oi each channel atler being compressed by the
`data compressor 3 is placed in a butler It. ol which there
`
`is at least one per selected channel. The butters 4 also
`act as a multiplexer because they can be read out in
`such a way as to convert several parallel data streams
`into one data stream (although the dillerenl streams are
`separately administered). The inlorrnalion contained in
`the butters 4 will be translerred to the butter memory 35
`undersupervision ot a microprocessor 24 by a DMA [di-
`rect memory aocess) controller 31, and is identifiable as
`input destined tor a main memory 35. which is in the
`lorm ol a band disk arrangement. The microprocessor
`24 initiates the data lransler lrorn the butler 4 to the bull-
`
`er memory 35. and performs memory allocation in the
`butter memory. The microprocessor 24 runs HOM-
`(read-only memory} 22 based sollware and makes use
`(it a working HAM (random access memory) 23 tor lem-
`porary variables. the administration oi the butter mem-
`ory 35, storage oi user commands and the user status
`etc. Input data in the butter memory 35 is translerred to
`the main memory 35 as soon as it is convenient under
`supervision ol the microprocessor 24 by another DMA
`controller 32.
`
`[0021] The stored data in main memory 36 is in due
`course transferred to the butter memory 35 under su-
`pervision ol the microprocessor 24 by DMA controller
`32. DMA controller 32 cannot at the same time be re-
`
`quired or used tor transferring data in the opposite di-
`rection. As television data is actually required to be dis-
`played on the television screen. it is lranslerrecl under
`supervision of the microprocessor 24 by DMA controller
`33 to a butler M. The process ol transler ol data lrorn
`main memory 36 to the butter memory 35. and lrorn the
`butler memory 35 lo the boilers 14 takes place sepa-
`rately lor channels which the viewer has selected as his-
`torical channels to be viewed or recorded or used for
`
`any other purpose. An adequate supply ot data per
`channel must always be present in the butter memory
`35 to be able to keep up with the demand. Data is taken
`lrorn the butters 14 and is decompressed by a data de-
`compressor 13. and is converted to an analogue signal
`by a die (digital to analogue] converter 12. The output
`oi the we converter 12 can be sent to a video recorder
`or television. An acceleration controller 41 has various
`tasks - it controls the acceleration rate at which data is
`
`required. including providing for slow motion and trozen
`irarnes and lrarne stepping. It also provides lor last lor-
`ward and last reverse lunctions. The DMA controller 33.
`
`butters 14. data decompressor 13 and die (digital to an-
`alogue) conveners 12 should all be capable ot working
`slightly taster {say 15%} than real time. so that an ac-
`celerated playback can be provided without loss ol data
`until the acceleration controller 41 generates an accel-
`erated display at a standard frame-rate. Live transmis-
`sions and historical transmissions can be simultaneous-
`ly displayed using PIP : {picture-in-picture) techniques
`by a Pit‘-llpostprocessor 42.
`[0022]
`It may be advantageous to combine the butter
`memory 35 and working FIAM (random access memory)
`23 into one memory.
`
`TlV0 454230
`
`308
`
`

`

`5
`
`EP 0 594 241 B1
`
`6
`
`[0023] The bulier memory 35 enables a single head
`hard disk to cope with the dual task ot writing the TV
`signal being monitored and simultaneously reading out
`the signal to be displayed.
`[0024]
`Flelerring now to figure 2. conceptually, when
`the arrangement is in operation. there is a llow ol data
`as lollows.
`
`[0025] Data arrives at the input terminal 50 Ior storage
`on the main memory 36, but as the disk in the main
`memory 36 may be temporarily busy tor another oper-
`ation. the data arriving will be buttered in input butter
`35s. by applying the data to the input 59a ol said input
`butler 35a. As soon as the disk is capable of receiving
`the data. the data stored in the input butler 35a is sup-
`plied to the output 51a oi the butter 35a and applied to
`the input 54 ol the main memory 36. for storage on the
`disk.
`
`[0026] Data will also be regularly requested from the
`main memory disk 36 to be displayed on the TV screen.
`Again the disk may be temporarily busy for another op-
`aration. Data stored in the output butter 35b is now sup-
`plied to the output 51b and thus applied to the output
`terminal 53 so as to enable continuity oi viewing for the
`user. As soon as the disk is capable of supplying data.
`the data stored on the disk is supplied to the output 56
`oi the main memory 35 and applied to the input 59b of
`the output butler memory 35b. for storage in the output
`butler 35b.
`
`in particular. the input butler 35a is needed to
`[0027]
`butter the incoming data while the disk is being read.
`and the output butler 35b is needed to provide a contin-
`uous output oi data while the disk is being written to.
`The input butler 35a and the output butter 35b are com-
`bined into one shared memory 35.
`[0028]
`It will be shown that the input butler part and
`the output butler part in the butler memory 35 can be
`realized using a FIFO or alternatively a reversible queue
`mechanism. These structures are now discussed.
`
`[D029] Figure 3 shows a butler memory. such as the
`input buffer memory 35a in the form at e FIFO. The out-
`put buiier memory has the same construction. Figure 3
`shows basic FIFO queue control using a two—entry FIFO
`queue control block 60. including two pointer locations.
`the pointers stored in the locations pointing to the be-
`ginning and the end of the queue. The pointers in the
`control block 60 are set to some suitable constant such
`
`as zero to indicate an empty queue. see ligure 3a. Mem-
`ory blocks 51a. 52a.
`58a and 59a are chained in one
`direction. All memory blocks include a memory space
`70 for storing the data and a pointer location 71, as in-
`dicated in the memory block 52a. The pointer P1 in the
`control block 60 points to the address where the memory
`block 593 is stored. As this memory block is the block
`lastly stored. its pointer has a constant value. such as
`zero. The pointer P2 in the control block 60 points to the
`address where the memory block 51a is stored. This
`memory block is the block containing the oldest infor-
`mation stored in the butter memory. its pointer points to
`
`the address where the next memory block 52a is stored.
`The pointer it of the memory block 523 points to the
`address where the next memory block is stored. In this
`way. the pointer oi block 583 points to the address where
`the block 59a is stored.
`
`[0030] Memory blocks. such as the memory block 72.
`are added to the queue at the end ol the chain, This is
`realized by selling P1 in control block 60 to the address
`where the memory block 72 is stored. Further. the point-
`er in memory block 72 becomes zero. and the pointer
`in memory block 593 will be set to the address where
`the memory block 72 is stored. Memory blocks. such as
`the memory block Sta. are taken lrorn the queue at the
`start oi the chain. This is realized by setting P2 in the
`control block 60 to the address where the memory block
`52a is stored. in this way memory blocks can be added
`to and taken from the queue without the need to follow
`the whole chain oi memory blocks. The pointer admin-
`istration can be maintained in a short. fixed period at
`time.
`
`A basic administration ol the butter memory 35
`[0031]
`is possible using 3 FlFO queues. namely one FIFO
`queue {FIFO number ‘it lor the tree memory blocks in
`the common butler memory 35. one FIFO (FIFO number
`2] tor the input bu ller memory part in the common butler
`memory 35 and one FIFO [FiFO number 3) for the out-
`put buiier memory part ol the common butler memory
`35.
`
`A memory block is allocated for input by taking
`[0032]
`it lrom FlFO number 1 and adding it to FIFO number 2.
`A memory block is deallocated lrom input alter its con-
`tents have been written to main memory 36 by taking it
`lrom FiFO number 2 and adding it to FIFO number 1. A
`memory block is allocated tor output by taking it from
`FlFO number 1 and adding it to FIFO number 3. A mem-
`ory bloclr is deallocated lrorn output alter its data has
`been transferred to the output terminal 53 by taking it
`irom FlFO number 3 and adding it to FIFO number 1.
`For this scheme to work property, there must be ade-
`quate memory available in the butter memory 35. It is
`important not to allow too much output memory to be
`allocated, as the amount ol tree memory tor input will
`then be tnsutlicient. The amount of memory needed.
`and the maximum amount of memory to ever be allocat-
`ed to output data are mainly dependent on the seek time
`and data transier lime oi the main memory 36.
`[0033] The FIFO queue control blocks. such as the
`control block 60, can be located in tixed locations ol
`working RAM 23 or the butter memory 35.
`[0034] Separate channels can be separately admin-
`istered by delining one FIFO tor tree memory blocks and
`two F|FOs per channel [one lor the input butler part and
`one [or the output butler pan. for each channel}.
`[0035]
`it may be possible to economics on memory
`by allowing the situation to occur exceptionally where
`there are no tree memory blocks to allocate lor input. In
`this case the most recently tilled output butler memory
`block is taken lrorn FIFO number 3 and added to FIFO
`
`TWO 454231
`
`309
`
`

`

`7
`
`EP 0 594 241 B1
`
`8
`
`number 1. An indication is set that in due course this
`data must be re—read lrorn main memory 36. This proc-
`ess can be repeated it more input butler memory blocks
`are needed. A snag is that in order to deallocate the
`most recent butter in a FIFO queue as administered in
`Figure 3. the entire chain at memory blocks must be lol-
`lowed in order to lind the most-recent-but-one memory
`block. which is to become the most recent memory
`block. This problem can be solved by using a reversible
`FIFO queue for the output butler part. as illustrated in
`Figure 4. Reversible queues are an extension to the
`FIFO ol figure 3. in that the memory blocks are linked in
`both directions. This enables a consistent queue admin-
`istration to be maintained tor use as FIFO (First-tn First-
`Outl or LIFO (Last—tri First~0ul) without needing to tollow
`the whole chain at pointers. For that purpose, the mem-
`ory blocks include two pointer locations 71 and 73. tor
`pointing towards a subsequent and a previous memory
`block respectively. The memory block 61 can again be
`the block including the oldest information. and the block
`69 then comprises the most information most recently
`stored.
`It the reierence numerals in Figure 3 that carry
`[0036]
`an index 'a' are amended so as to carry an index 'b‘. the
`butter memory ol Figure 3 thus obtained describes the
`output butler memory 35b.
`
`Claims
`
`An arrangement tor intermediate storage ot a video
`signal, said arrangement comprising: input means
`(50) [or receiving sequential video signal elements
`at a tirst average speed; frrst—in—iirst-out input bridg-
`ing butter memory means 135a) having an input
`(59a) ted by said input means. having random ac-
`cess tunctionatity tor receiving said video signal el-
`ements and having an output intertace (51 at; mass
`memory disc means (36) having cross-track ran-
`dom access. lunctionality tor ellecting said interme-
`diate storage. and having write head means ted by
`said output interface {Stat and furthermore read
`head means: lirst-in-lirst«out output bridging butler
`memory means (35b) having random access lunc-
`tionality and having an input intertace (5%) led by
`said read head means; output means (53) having
`an input led by said lirst-in-tirst—out output bridging
`butter memory means t35b} tor outputting said so-
`quential video signal elements at a second average
`speed; and wherein said input bridging butler mem-
`ory means and output bridging butter memory
`means are exchangeably mapped on a single bridg-
`ing bulter, for through said random access lunction-
`alily and said cross-track random access lunction-
`aiity etlecling an arbitrarily selectable intermediate
`storage time.
`
`2- An arrangement as claimed in Claim 1. incorporat-
`
`ed in a television receiver apparatus that has a vid-
`eo output tor connection to a video recorder appa-
`ratus.
`
`An arrangement as claimed in Claim I, wherein said
`write head means and read head means are located
`
`in a single head.
`
`An arrangement as claimed in Claim 1, where in said
`mass memory disc means are magnetic andlor op-
`tical storage hard disc means.
`
`An arrangement as claimed in Claim 1 wherein said
`input means are arranged [or operating at a lirst av-
`erage spaed and said output means are arranged
`tor then operating at at second avrage speed that
`is higher than said first ave rage speed.
`
`An arrangement as claimed in Claim 1 wherein said
`input means are arranged for operating at a lirst av-
`erage speed and said output means are arranged
`for selectably operating at a second average speed
`that is eilhercontroltably higher or controilabty lower
`than said first average speed.
`
`An arrangement as claimed in Claims 5 or 6. where-
`in said second average speed corresponds to an
`appropriate human user viewing speed.
`
`An arrangement as ctaimed in Claim 1 . wherein said
`storage disc means allow current storage ol at least
`a five minutes long stream oi video signal elements.
`
`An arrangement as claimed in Claim 1 . wherein said
`input means. said output means and said mass
`memory disc means are arranged lor accepting at
`least two independent streams oi video signal ele-
`ments in parallel.
`
`. An arrangement as claimed in Claim 1. wherein said
`input means and said massrnernory disc means are
`arranged lor accepting at least two independent
`streams of video signal elements in parallel.
`
`. An arrangement as claimed in Claim 1. combined
`with a supplementary video recording apparatus.
`wherein said output means are arranged tor belat-
`edly aclivating saidvideo recording apparatus alter
`said intermediate storage having commenced at an
`earlier instant.
`
`. An arrangement as claimed in Claim 1, combined
`with a video receiver apparatus and a video display
`apparatus. and being arranged for broadcaster-im
`dependent replay andtor slow-motion replay.
`
`. An arrangement as claimed in Claim 1 combined
`with a multi-channel video-receiver apparatus and
`
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`a supplementary single-channel video-recording
`apparatus. wherein said input means and said mass
`memory disc means are arranged tor accepting at
`least two Independent streams ol video signal ele-
`ments in parallel and said output means are ar-
`ranged for belatedly activating said supplementary
`video recording apparatus with respect to a second
`channel after said intermediate storage having
`commenced at an earlier instant during overlap oi
`said second channel with a first channel during the
`latter's being stored on said supplementary video
`recorder.
`
`. An arrangement as claimed in Claim 1 combined
`with a video-receiver apparatus and a video display
`apparatus. wherein said input means and said mass
`memory disc means are arranged for accepting a
`tirst stream oi video signal elements in parallel to
`receiving at least a second independent stream of
`video signal elements next to said First stream of vid-
`eo signal elements by said video receiver appara-
`tus, and said Output means are arranged tor belat-
`edly activating said video display apparatus with re-
`spect to said first stream alter said intermediate
`storage having commenced at an earlier instant
`during overlap at said lirst and second streams and
`said second stream's being displayed on said video
`display apparatus.
`
`. An arrangement as claimed in Claim 1 combined
`with a video-receiver apparatus and a video display
`apparatus, and tor receiving a stream 0! video sig-
`nal elements, and comprising inputting means tor
`receiving an intermission control signal at a first par-
`ticular time instant. and second inputting means for
`subsequently receiving a continue control signal at
`a second particular time instant. and said output
`means are arranged tor belatedly activating said
`video display apparatus as trom said second par-
`ticular time instant on for displaying said stream oi
`video signal elements as having been stored since
`said first particular time instant.
`
`Patentenspriiche
`
`1. Anordnung zur unmittetbaren Speicherung eines
`tfdeosignals, wobei die genannle Anordnung um-
`iai3t: Eingangsmittei (50) zum Emptangen sequen-
`tielter Wdeosignaielemente bei einer ersten milita-
`ren Geschwindiglreit;
`FlFO-Eingangst'tbeibrClk—
`kungspulferspeicherrnitteI (35a), mil einern von den
`genannten Eingangsmitteln gespeisten Eingang
`{S93}. mit der Funktionalitat des wahiireien Zugrifis
`zum Emptangen der genannten \fideosignale|e—
`rnente und mit einer Ausgangsschnittstelle (51 at.
`Massenspeicherplanenrnitteln (36}mi1 der Funl<tio-
`nalitat des wahilreien Ouerspurzugrills zurn Bewir—
`
`l<en der genannten Zwischenspeicherung und mit
`von der genannten Ausgangsschnittstelle {S18} ge-
`speisten Sctireibiroptmittein und weiterhin Lase-
`kopimitteln. FlF0—Ausgangsfiberbrflckungspufler-
`speicherrnitteln (35b) mit der Fun ktionalitiit des
`wahllreien Zugritls und mit einer \i0l'I den genannten
`Lesekoptmitteln gespeisten Eingangsschnittstelte
`(59b}‘. Ausgangsmitteln (53) mit einem von den ge-
`nannten
`FlF0-AusgangsEIberbrIickungspLtt'ler-
`speicherrnitteln {35b) gespeislen Eingang zurn
`Ausgeben der genannlen sequentiellen \ftdeosi-
`gnalelemente be-i einer zweiten mittlereri Ge-
`schwindigkeit; und wobei die genannten Eingangs-
`uberbrfickungspulterspeichermittet und Ausg.angs—
`tiberbnilclcungsputterspeichermittel
`austauschbar
`aui einen einzelnen Clberbruckungspuiier abgebi|-
`det werden, um fiber die genannte Funktionalitat
`des wahllreien Zugritls und die genannte Funl<tio-
`nalitét des wahitreien Querspurzugritis eine willIrflr-
`lich wahlbare Zwischenspeicherdauer 2U bewirl-ten.
`
`Anordnung nach Anspruch 1, aulgenornmen in el-
`nem Fernsehgerat, das einen Videoausgang zum
`Anschlufl an ein Videorecordergerat hat.
`
`Anordnung nach Anspruch 1. wobei die genannten
`Schreibkopimittel und Lesekoptmitlet in einem ein-
`Iigen Kopl liegen.
`
`Anordnung nach Anspruch 1. wobei die genannlen
`Massenspeicherplattenrnittel Feslplaltenrnittel zur
`magnetischen undloder optischen Speicherung
`sind.
`
`Anordrtung nach Anspruch 1. wobel die genanntert
`Eingangsrnittel |Elr einen Betrieb bei einer ersten
`mittleren Geschwindigkeit ausgebildet sinct und die
`genannten Ausgangsmittel ausgebildet sind, um
`dann bet einer zweiten rnittleren Geschwindigkeit
`zu arbeiten, die hoher ist als die genannte erste
`mittlere GeschwindigkeiL
`
`Anordnung nach Anspruch 1. wobei die genannten
`Eingangsmittel lfir einn Eletrieb bei einer ersten
`rnittleren Geschwindigkeit ausgebildet sind und die
`genannten Ausgangsrnittel lllr einen setelrtiven Be-
`trieb bei einer zweiten rnittleren Geschwindigkeit
`ausgehildet sind. die entweder regelbar héiheroder
`regelbar niedriger ist ais die genannie erste ntitilere
`Ge-schwindigkeit.
`
`Anordnung nach Anspruch 5 oder 6. wobei die gs»
`nannte zweite mittlere Geschwindigkeil einer ge-
`eigneten
`Etetrachtungsgeschwindigkeit
`eines
`menschlichen Benutzers entspricht.
`
`Anordnung nach Anspruch 1, wobei die genannten
`Speicherplattenmitleldie laulendespeicherung ZU-
`
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`mindesl eines fitnl Minulen langen Slrorns aus Vl-
`deosignalelementen zulassen.
`
`Anordnung nach Anspruch 1. wobei die genannlen
`Eingangsmittel. die genannlen Ausgangsmittet und
`die genannlen Massenspeicherplallenmitlel aus-
`gebildet sind. um zurnindesl zwei Unahhéingige
`Slrérne Von Videosignalelementen parallel zu ak-
`zeplieren.
`
`. Anordnung nach Anspruch 1, wohei die genannlen
`Eingangsmillel und die genannlen Massenspei-
`cherplarlenmittl ausgebildel sind, um zumindesl
`zwei unabhéngige Slréme van Wdeosignalelemerr
`ten parallel zu akzepliererr
`
`_ Anordnung nach Anspruch 1, kombiniert mit einem
`zusélziichen Vrdeoaufnahmegerél. wobei die ge-
`nannlen Ausgangsmillel ausgebildel sind. um die-
`ses lfideorecordergerial spél zu aklivieren. nach-
`dem die genannle Zwischertspeicherung zu einem
`lrflheren Zeitpunkl begonnen hat.
`
`. Anordnung nach Anspruch 1, kombirtierl mil einern
`Videoempfangsgerél und einem Videowiedergabe-
`geret und ausgehildel zurn rundllinkanbietterun.-arb-
`héngigen Abspielen undfoder zurn Abspielen in
`Zaillupe.
`
`. Anordnung nach Anspruch 1. kombinierl mil einerrl
`Mehrkanalvideoemplangsgeréit und einern zu5§tlz-
`lichen Einkanalvideoaulnahmegerét, wobei die ge-
`nannlen Eingangsmitlel und die genannlen Mas-
`senspeicherplallenrnittel ausgebildel sind, um zu-
`rnindesl zwei unabhfingige Stréme von Videosi-
`gnalelemenlen parallel zu akzeplieren und die ge-
`nannlen Ausgangsmiltel ausgebildet sind, um die-
`ses Zusétzliche lfideoaulnahmegerét in bezug aul
`einen zweilen l-(anal spét zu aktivteren. nachdem
`die genannte Zwischenspeicherung zu elriem Ini-
`heren Zeitpunkt wéihrend des Uberlappens dieses
`zweiten Kanals