..
`
`"
`
`inteJ.
`
`PC SD RAM Serial Presence Detect (SPD) Specification
`
`PC SDRAM Serial Presence Detect (SPD)
`Specification
`
`REVISION 1.2B .
`November, 1999
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`Nov,1999
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`1of30
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`

`....
`
`PC SDRAM Serial Presence Detect (SPDJ Specification
`
`IS" WITH NO WARRANTIES
`"AS
`IS PROVIDED
`THIS SPECIFICATION
`INCLUDING ANY WARRANTY OF MERCHANTABILITY,
`WHATSOEVER,
`NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY
`WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR
`SAMPLE. Intel disclaims au liability, including liability for infringement of any proprietary
`rights, relating to use of information in this specification. No license, express or implied,
`by estoppal or otherwise, to any intellectual property rights is granted herein.
`
`• *Third-party brands and names are the property of their respective bwners.
`
`Copyright Intel Corporation, 1997, 1999
`
`Nov, 1999
`
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`

`"'
`
`PC SDRAM Serial Presence Detect (SPD) SpeclHcation
`
`Changes:
`
`Revision 1.28:
`Updated Table 5, Serial Present Detect Data format, for consistency:
`- Definitions of bytes 32-35 were added to this summary table since they were already
`defined in the specs
`Added Section 5.0, SPO data format example.
`
`Revision 1.2A:
`Modified specification name
`Corrects the typos in Rev1 .2 revision history
`Byte 127 bit 3 definition reserved for thermal information, values are TBD
`
`Revision 1.2 adds:
`Bytes 126, 127: Additional Information for "backward compatibility"
`Bytes 93-94: Manufacturing Date Code
`Bytes 32-35:
`Additional Timing Information
`Byte 5:
`Changed the nomenclature from Bank to Row on the DIMM to remove
`confusion of Rows vs. Banks on a DIMM
`
`Revision 1.1 adds comments to clarlfy several Bytes:
`Bytes 3-4:
`Note added to clarify address row/column 1/16 rollup usage.
`Bytes 5, 17: . Note added to clarify Module, SDRAM Device bank usage.
`Bytes 23-26: Note added to clarify timing1/16ns rollup usage.
`
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`

`infel.
`TABLE OF CONTENTS
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`CHANGE HISTORY
`
`LIST OF TABLES
`
`LIST OF FIGURES
`
`1.0 INTRODUCTION
`
`2.0 SDRAM MODULE PERFORMANCE GRADES
`
`3.0 EEPROM COMPONENT SPECIFICATIONS
`
`4.0 SERIAL PRESENCE DETECT EEPROM DATA
`
`5.0 SPD DATA FORMAT EXAMPLE
`
`LIST OF TABLES
`TABLE I: EEPROM COMPONENT ABSOLUTE MAXIMUM RA TINGS
`TABLE 2: EEPROM COMPONENT OPERA TING CONDITIONS
`TABLE 3: EEPROM COMPONENT A.C. AND O.C. CHARACTERISTICS
`TABLE 4: EEPROM COMPONENT A.C. TIMING PARAMETERS
`TABLE 5: SERIAL PRESENCE DETECT DAT A FORMAT
`TABLE 6: SPD DATA FORMAT EXAMPLE
`
`LIST OF FIGURES
`FIGURE I: EEPROM COMPONENT A.C. TIMING PARAMETERS
`FIGURE 2: EEPROM DATA VALIDITY
`FIGURE 3: EEPROM START AND STOP CONDITIONS
`FIGURE 4: EEPROM ACKNOWLEDGE
`FIGURE 5: EEPROM BYTE WRITE OPERATION
`FIGURE 6: EEPROM PAGE WRITE OPERATION
`FIGURE 7: EEPROM CURRENT ADDRESS READ OPERATION
`FIGURE 8: EEPROM RANDOM READ OPERATION
`FIGURE 9: EEPROM SEQUENTIAL READ OPERATION
`
`3
`
`4
`
`4
`
`5
`
`5
`
`6
`
`11
`
`29
`
`6
`6
`6
`7
`11
`29
`
`7
`8
`8
`8
`9
`9
`9
`9
`10
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`

`infel.
`1.0 Introduction
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`.
`This specification defines the Serial Presence Detect (SPD) electrical and Data Structure
`requirements for Synchronous DRAM Dual In-Line Memory Modules ($DRAM DIMMs) and Small(cid:173)
`outline Memory Modules (SO-DI MM). These SDRAM DIMMs are intended for use as main
`memory installed on personal computer, work-station, and/or server motherboards.
`
`~~~·~:~~
`:!?.!:kl$~'._,
`mm CICI
`
`168-D!MM reference
`
`This specification largely follows the JEDEC defined 168-pin and S0-144 SDRAM DIMM SPD
`specs as of July 1996. Changes in process are currently shown in italics.
`
`2.0 SD RAM Module Performance· Grades
`Three perfonnance grades are defined in the SPD matrix:
`
`CAS Latency x
`CAS Latency x-1
`CAS Latency x-2
`
`highest latency, lowest performance
`·
`2nd highest latency
`3rd highest latency, highest performance (may restrict freq)
`
`This is a relative series of three latencies, CL x being the most commonly available at this speed
`grade.
`·
`The performance grade of the module is determined by the read data access time (Tac), and RAS
`cycle time (Trc) supported by the SDRAM components.
`
`Latency numbers in the sequence will depend on the speeds which are supported by the module.
`
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`intel.
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`3.0 EEPROM Component Specifications
`
`The Serial Presence Detect fl.inction is implemented using a 2048 bit EEPROM component. This
`nonvolatile storage device contains data programmed by the DIMM manufacturer that identifies.
`the module type and various SDRAM organization and timing parameters. System read/write
`operations to the EEPROM device occur. using the OIMM's SCL (clock) and SDA (data) signals,
`together with SA(2;0) which provide the EEPROM Device Address. If the EEPROM device has a
`Write Protect input pin, it must be tied in the non-write protect state on the DIMM PCS. The
`EEPROM device selected by the DIMM manufacturer must use the SA(2:0) device address
`signals. The EEPROM must operate with a Vee of 3.0 Vdc to 3.6 Vdc.
`
`Table 1: EEPROM Component Absolute Maximum Ratings
`
`Parameter
`All Input or Output Voltages with
`Respect to Ground
`Ambient Sto~e Te~rature
`
`Range
`+4.6V to -0.3V
`
`-40 •c to +100 °c
`
`Table 2: EEPROM Component Operating Conditions
`
`Parameter
`Ambient ~ratil!& Temp~rature
`Positive Power Sl!!lll!L
`
`Ral!fill
`0°c10+1o•c
`3.0Vto3.6V
`
`Table 3: EEPROM Component A.C. and D.C. Characteri$tlcs
`
`Sy_mbol
`IecA
`Isa
`Iu
`ho
`V1L
`V1H
`VoL
`
`Parameter
`Active Power Supply_ Current
`Standby Current
`Input Leakage Current
`O~ut Leaki!.g_e Current
`11!2.ut Low Vol~e
`Input Hjg_h Volt~e
`Output Low Volt!E:_e
`
`Test Conditions
`fseL = I 00 kHz
`VIN= GND.or Vee
`V1N=GNDorVcc
`VoUT "'GND to Vee
`
`IoL"' 3.0 mA
`
`Min
`
`-0.3
`Yee X 0.7
`
`Max
`5.0
`100
`10
`10
`VecX0.3
`
`0.4
`
`Units
`mA
`uA
`uA
`uA
`v
`v
`v
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`intet.
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`Table 4: EEPROM Component A.C. Timing Parameters
`
`~mbol
`fuL
`Ti
`
`tAA
`tauF
`
`t1m:STA
`!Low
`
`lH!OH
`lsu:STA
`
`tHO:OAT
`tsu:OAT
`tR
`tp
`
`Min
`
`0.3
`6.7
`
`4.5
`6.7
`4.5
`6.7
`
`0
`500
`
`6.7
`300
`
`Parameter
`SCL Clock Fr~ueni:x_
`Noise Suppression Time Constant at
`SCL, SDA i~uts
`SCL Low to SDA Data Out Valid
`Time the Bus Must Be Free before a
`New Transmission Can Start
`Start Condition Hold Time
`Clock Low Time
`Clock Hig!l Time
`Start Condition Setup Time
`J.for a R~eated Start Condition)
`us
`Data In Hold Time
`ns
`Data In Setu.J!. Time
`us
`SDA and SCL Rise Time
`ns
`SDA and SCL Fall Time
`us
`St~ Condition Setui Time
`!fil_i:!ITO
`ns
`Data Out Hold Time
`!mi.
`ms
`15
`Write ~le Time
`lwa
`Note: The write cycle time (twR) is the time from a valid stop condition of a write sequence to the end of the
`EEPROM Internal erase/program cycle. During the write cycle, the EEPROM bus Interface circuits are
`disabled, SOA remains high due to pull-up resistor, and the EEPROM does not respond to its slave
`address.
`
`Units
`kHz
`ns
`
`us
`us
`
`us
`us
`us
`us
`
`Max
`80
`100
`
`7.0
`
`I
`l
`300
`
`SCL
`
`SDA
`IN
`
`SDA
`OUT
`
`tsu:STO
`
`Figure 1: EEPROM Component A.C. Timing Parameters
`
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`

`

`PC SDRAM Serial Presence Detect (SPD) Specification
`
`infel.
`
`SDA
`
`SCL
`
`I
`I
`
`11
`
`I
`I
`I
`
`Data
`stable
`
`Data
`change
`
`Figure 2: EEPROM Data Va.lidity
`
`SDA
`
`SCL
`
`I
`I
`I
`I
`I
`START
`
`STOP
`
`START = High to low transition ol SOA llhlile SCL is high
`STOP = Low to high transition of SDA while SCL is high
`
`Figure 3: EEPROM Start and Stop conditions
`
`SDA
`
`receiver
`
`START
`
`I
`
`v
`
`I
`
`!
`
`ACKNOWLEDGE
`
`ACKNOWLEDGE:
`Transmitter releases SDA after transmitting eight bits.
`During ninth clock cycle receiver pulls SDA low to acknowledge receit of the eight bits.
`
`Figure 4: EEPROM Acknowledge
`
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`

`intel.
`
`SYSTEM
`MASTER:
`
`SDA
`
`EEPROM:
`
`PC SD RAM Serlal Presence Detect (SPD) Specification
`
`s
`~
`T slave address
`data
`worti address
`:
`(write]
`0
`T~ ,---A--..~ p
`
`mf] 0~ 0• I : : : : : : : 11: : : : : : : I u
`• c
`c •
`
`A
`
`A
`c
`K
`
`K
`
`Figure 5: EEPROM Byte Write Operation
`
`.--
`
`~
`(write)
`data n-.1
`data n
`word eddres$ (n)
`R
`data n,. 15 0
`T ,---J'----, ,---J'----, ,---J'----, ~ ~ p
`, ! : : : : : : : 11::::::: I l::::::: I ~;:=i 0
`[flfl 0ffTI] 0
`
`A
`c
`K
`
`A
`c
`Iii,
`
`A
`c
`K
`
`A
`c
`K
`
`A
`c
`K
`
`SYSTEM
`MASTER:
`
`SDA
`
`EEPROM:
`
`Figure 6: EEPROM Page Write Operation
`
`slave address
`"
`(Reed)
`R
`t,..--A---,
`
`s
`T
`0 •
`
`SYSTEM
`MASTER:
`
`SOA
`
`EE PROM:
`
`Figure 7: EEPROM Current Address Read Operation
`
`SYSTEM
`MASTER:
`
`SDA
`
`EEPROM:
`
`s
`T
`
`c
`K
`
`c
`K
`
`data n
`
`Figure 8: EEPROM Random Read Operation
`
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`

`

`PC SDRAM Serial Presence Detect (SPD) Specification
`
`SYSTEM
`MASTER:
`
`SDA
`
`EE PROM:
`
`A·
`c
`K
`
`A
`
`c •
`
`A
`c
`I(
`
`A~ '---v--"
`c
`data n+1
`data n
`K
`
`data n+x
`
`Figure 9: EEPROM Sequential Read Operation
`
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`

`intel.
`
`PC SOR.AM Serial Presence Detect (SPD) Specification
`
`4.0 Serial Presence Detect EEPROM Data
`
`Table 5: Serial Presence Detect Data Format
`
`Byte Number
`
`Function
`
`Back Random Column Address
`
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24.
`
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36-61
`62
`63
`
`73-90
`91-92
`93-94
`95-98
`99-125
`126
`127
`
`Notes: Required/Optional' (bold") are SDRAM only bytes
`
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`

`

`ifltel.
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`Byte 0 ·Number of Bytes used by Module Manufacturer (General)
`This field describes the total number of bytes used by the module manufacturer for the SPD data
`and any (optional) specific supplier information. The byte count includes the fields for all required
`and optional data.
`
`Number of ~es
`Undefined
`1
`2
`3
`
`128
`
`254
`255
`
`Hex Value
`00
`01
`02
`03
`
`80
`
`FE
`FF
`
`Byte 1 • Total SPD Memory Size (General)
`This field describes the total size of the serial memoiy used to hold the Serial Presence Detect
`data.
`
`S!ze
`
`Hex Value
`00
`01
`02
`03
`04
`05
`06
`07
`08
`09
`OA
`OB
`oc
`OD
`
`Byte 2 • Memory Type (General)
`This field describes the fundamental memory type implemented on the module.
`
`Memory Type
`EDO
`SDRAM
`
`Hex Value
`02
`04·
`
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`

`

`"
`
`intel.
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`Note for Bytes 3-4: Bytes 3-4 show a roll-up value for Hex 1, 2, 3 (i.e .. 1row/16rows). For
`SDRAM devices over duration of REV 1 in Byte 62 {SPD Jedec Rev level), values of 1-3rows/cols
`are not expected, and Hex equivalent is 16-18rows/columns. Jedec Byte 62 would change rev
`· level if values of 1-3 row/col become available.
`
`Byte 3 - Number of Row Address Bits (SD RAM specific)
`This field describes the number of row address bits in the SDRAM array. Note: the number of row
`address bits does not include the bank selects (BAO, BA1 ). If the module has only one bank OR if
`the module has two banks of the same size and organization, then bits 3:0 describe the number of
`row address bits, and bits 7:4 are 0. If the module has two banks with different size/organization,
`then bits 3:0 describe the row addressing for bank 1 and bits 7:4 describe the row addressing for
`bank 2.
`
`Number of Row Addr bits
`Undefined
`1116
`2117
`
`Bits 3:0 Hex Value
`0
`·1
`2
`
`7
`8
`9
`to
`11
`
`14
`15
`
`7
`B
`9
`A
`B
`e
`F
`
`Number of Row Addr bits
`Undefined
`1/16
`2117
`
`Bits 7:4 Hex Value
`0
`1
`2
`
`7
`8
`9
`10
`11
`
`14
`15
`
`7
`8
`9
`A
`B
`
`E
`F
`
`Nov, 1999
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`

`

`PC SDRAM Serial Presence Detect (SPD) Specification
`
`BYTE 4 - Number of Column Address Bits (SD RAM specific)
`This field describes the number. of column address bits in the SDRAM array. Note: the number of
`column address bits does not include the bank selects (BAO, BA 1 ), or the AutoPrecharge bit. If
`the module has only one bank OR if the module has two banks of the same size and organization,
`then bits 3:0 describe the number of column address bits. and bits 7:4 are 0. If the module has
`two banks with different size/organization, then bits 3:0 describe the column addressing for bank 1
`and bits 7:4 describe the column addressing for bank 2.
`
`Number of Col Addr bits
`Undefined
`1116
`2117
`
`Bits 3:0 Hex Value
`0
`1
`2
`
`7
`a
`9
`10
`11
`12
`13
`14
`15
`
`1
`8
`9
`A
`B
`c
`D
`E
`F
`
`Number of Col Addr bits
`Undefined
`1116
`2117
`
`Bits 7:4 Hex Value
`0
`1
`2
`
`7
`8
`9
`10
`11
`12
`13
`14
`15
`
`7
`8
`9
`A
`B
`c
`D
`E
`F
`
`.
`BYTE 5 - Number of Module Rows
`This field describes the number' of rows of SD RAM components on the module. Byte 17 applies to
`SDRAM device banks (a module with 2 rows could have devices with 2-16 internal banks).
`
`Number of Banks
`Undefined
`1
`2
`3
`
`254
`255
`
`Hex Value
`00
`01
`02
`03
`
`FE
`FF
`
`Nov, 1999
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`

`intet.
`
`PC SD RAM Serial Presence Detect (SPD) SpecilicaHon
`
`BYTES 6 & 7 ·Module Data Width
`This field describes the data width on the SCRAM module. Bit 0 of byte 6 is the LSB and Bit 7 of
`byte 7 is the MSB.
`
`Module Data Width
`Undefined
`1
`2
`3
`
`eyte f{HeX)
`00
`00
`00
`00
`
`eyte 6(Hei)
`00
`01
`02
`03
`
`32
`
`36
`
`64
`
`12
`
`BO
`
`12B
`
`144
`
`160
`
`256
`
`00
`
`00
`
`00
`
`00
`
`00
`
`00
`
`00
`
`00
`
`01
`
`, ___
`
`20
`
`24
`
`40
`
`48
`
`50
`
`80
`
`90
`
`AO
`
`00.
`
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`

`

`PC SDRAM Serial Presence Detect (SPD) Specification
`
`BYTE 8 - Module Interface Signal Levels
`This field describes the SDRAM module signal voltage interface.
`
`Voltage Interface
`5.0 Voll/TTL
`LVTTL
`HSTL 1.5 ·
`SSTL3.3
`SSTL2.5
`TBD
`TBO
`
`New Table
`
`Hex Value
`00
`01
`02
`03
`04
`05
`06
`
`FF
`
`BYTE 9 - SDRAM Cycle time (highest CAS latency)
`This field defines the total minimum cycle time (clock period) for the SDRAM. For example if the
`SDRAMs support CAS latency of 3, 2 and 1 (as indicated in byte 18), this byte defines Tclk for
`CAS latency 3. The byte is broken into two nibbles: the high order nibble {bits 4 through 7)
`designate the cycle time to a granularity of 1 ns; the value presented by the low order nibble has a
`granularity of 1f10 ns and is added to the value of the higher nibble.
`
`BYTE 10 • SDRAM Access time from Clock (highest CAS latency)
`This field defines the maximum clock to data out for the SDRAM (Tac). For example if the
`SDRAMs support CAS latency of 3, 2 and 1 (as indicated in byte 18), this byte defines Tac for
`CAS latency 3. The byte is broken into two nibbles: the high order nibble (bits 4 through 7)
`designate the cycle time to a granularity of 1 ns; the value presented by the low order nibble has a
`granularity of 1/1 O ns and is added to the value of th~ higher nibble.
`
`BYTE 11 • Module Configuration Type
`This field defines the module's error detection and correction scheme.
`
`Error Detect/Correct
`Nona
`Paii!Y
`ECC
`TBD
`TBD
`TBO
`TSD
`
`TSO
`
`Hex Value
`00
`01
`02
`03
`04
`05
`06
`
`FF
`
`Nov, 1999
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`
`

`

`..
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`BYTE 12 • Refresh Rate/Type
`This field defines the module's refresh rate and type.
`
`Refresh Period
`
`Bit 7, Self Refresh
`Fla
`0
`0
`0
`0
`Q
`0
`0
`Q
`0
`0
`
`Self Refresh
`
`TBD
`
`Bits 6-0 (hex)
`
`00
`01
`02
`03
`04
`05
`06
`07
`08
`09
`
`00
`01
`02
`03
`04
`05
`06
`
`7F
`
`BYTE 13 - SDRAM Width (Primary SDRAM)
`Bits 6:0 of this byte define the data width of the primary SDRAM components used on the module.
`The primary SDRAM is that which is used for data. Examples of primary (data) SDRAM widths are
`x4, x6, x16, and x32. Bit 7 of this byte is a flag which Indicates that a 2nd bank on the module has
`a primary SDRAM width of 2X that of the first bank. If the module has two banks with the same
`Primary SDRAM width, then bit 7 remains as "O".
`
`Primary SORAM
`Co11.!.25'nent Data Width
`Undefined
`1
`2
`3
`4
`a
`
`16
`
`32
`
`127
`
`Bits 6:0 Hex Value
`
`00
`01
`02
`03
`04
`
`08
`
`10
`
`20
`
`7F
`
`Bank Con~uratlon
`No Bank 2 ·OR·
`Bank 2 uses same width
`Prim!l_ry SDRAM as Bank 1
`Bank 2 Primary SORAM ls
`2X the width of Bank 1
`
`Bits 7 Value
`
`0
`
`1
`
`Nov, 1999
`
`17 of 30
`
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`
`

`

`..
`
`intel.
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`BYTE 14 - Error Checking SDRAM Width
`If the module incorporates error checking and if the primary data SDRAM does not include these
`bits; i.e. there are separate error checking SDRAMs, then the error checking SORAM's width is
`expressed in this byte. Examples of error checking SCRAM widths include x4, x8, and x16.
`
`Bits 6:0 of this byte. define the data width of the Error Checking SDRAM components used on the
`module. Bit 7 is a flag which indicates that a 2nd bank on the module has Error Checking
`SDRAM width of 2X that of the first bank. If the module has two banks with the same Error
`Checking SDRAM width, then bit 7 remains as "O".
`
`Error Checking SORAM
`Component Data Width
`Undefined
`1
`2
`3
`4
`5
`6
`7
`8
`
`16
`..
`32
`
`127
`
`Bits 6:0 Hex Value
`
`00
`01
`02
`03
`04
`05
`06
`07
`08
`
`10
`
`20
`
`7F
`
`Bank Configuration
`No Bank 2 ·OR-
`Bank 2 uses same width
`EC SDRAM as Bank 1
`Bank 2 EC SORAM is 2X
`Ille width of Bank 1
`
`Bits 1 Value
`
`0
`
`1
`
`BYTE 15 - SDRAM Device Attributes, Min Clock Delay for Back to Back Random Column
`Addresses
`
`Number of Clocks
`Undefined
`1
`2
`3
`4
`5
`6
`
`255
`
`Hex Value
`00
`01
`02
`03
`04
`05
`06
`
`FF
`
`Nov, 1999
`
`18of 30
`
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`
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`Page 2004-18
`
`

`

`PC SD RAM Serial Pre5ence Detect (SPD) Specification
`
`BYTE 16 - SDRAM Device Attributes, Burst Lengths Supported
`This byte defines variou.s burst lengths supported. If the burst length is supported, then the
`corresponding bit is T
`
`Blt7
`Burst
`Length=
`P1!9_e
`1 or o
`
`Blt6
`TBO
`
`Blt5
`TBD
`
`0
`
`0
`
`8114
`TBO
`
`0
`
`Blt3
`Burst
`Length= 8
`
`Bit 2
`Burst
`Length= 4
`
`Bit 1
`Burst
`Length 2
`
`!!It 0
`Burst
`Length= 1
`
`1 orO
`
`1 oro
`
`1 oro
`
`1 orO
`
`BYTE 17 - SDRAM Device Attributes, Number of Banks on SD RAM Device
`This byte defines the number of banks internal to the SDRAM devices for each row of the DlMMs.
`
`Number of Device Banks
`Resvd.
`1
`2
`3
`4
`5
`
`.....
`256
`
`Hex Value
`00
`01
`02
`03
`04
`05
`...
`FF
`
`BYTE 18 - SDRAM Device Attributes, CAS Latency
`This byte defines which CAS latencies are supported. If the bit is "1" then that CAS Latency is
`supported.
`
`Blt7
`TBD
`
`1 orO
`
`Blt3
`Blt4
`Bit S
`Blt6
`CAS
`CAS
`CAS
`CAS
`Latel}fY_= 7 Late~6 Late~=5 Laten<;)/_=4
`1 or O
`1 orO
`1 orO
`1 orO
`
`BltO
`Bit 1
`Blt2
`CAS
`CAS
`CAS
`laten~=3 Late~=2 Laten~= 1
`1 orO
`1 orO
`1 orO
`
`BYTE 19- SDRAM Device Attributes, CS Latency
`This byte defines which CS latencies are acceptable for the Module. If the bit is "1" then that CS
`Latency is supported.
`
`Blt7
`TBO
`
`1 orO
`
`Blt6
`CS Latency
`=6
`1 orO
`
`Bit 5
`CS Latency
`=5
`1or0
`
`Bit4
`CS latency
`=4
`1 orO
`
`Blt2
`Bit 3
`cs latency cs Latency
`=3.
`=2
`1 orO
`1 orO
`
`Bit 1
`CS Latency
`= 1
`1 orO
`
`Bit 0
`CS Latency
`=O
`1 or o
`
`BYTE 20 - SDRAM Device Attributes, WE Latency
`This byte defines which CS latencies are acceptable for the Module. If the bit is "1" then that WE
`Latency is supported.
`
`Blt7
`TBD
`
`1 orO
`
`Bit 0
`Blt4
`Bit 1
`Blt2
`Blt5
`Blt6
`Blt3
`WE Latency WE Latency WE Latency WE Latency WE Latency WE Latency WE Latency
`=4
`=6
`=3
`=2
`=O
`"5
`" 1
`1 orO
`1 or 0
`1 or.0
`1 orO
`1 orO
`1 orO
`1 oro
`
`Nov, 1999
`
`19 of 30
`
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`
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`Page 2004-19
`
`

`

`infel.
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`BYTE 21 - SDRAM Module Attributes
`This byte defines yarious aspects of the module. If the aspect is TRUE, then the corresponding bit
`is ·1·.
`
`6117
`TSO
`
`Bltli
`Redundant
`RowAddr
`
`Blt5
`Differential
`Clock Input
`
`Blt4
`Registered
`OOMB
`Inputs
`
`Sit3
`Buffered
`OQMB
`Inputs
`
`Sit2
`On·Card
`PLL (Clock)
`
`Bit 1
`Registered
`Address/
`Control
`l~ts·
`1 orO
`
`BltO
`Suffered
`Address/
`Control
`l!)J!_IJIS •
`1 orO
`
`1 or O
`1 oro
`0
`•Address, RAS, CAS, WE, CKE, S
`•• Redundant addressing implies the use of SORAM~ having the same address depth (e.g. 4Mx4 mixed with 4Mx16) in
`the same 8-byte quad word, but having different RASICAS addressing and/or different numbers of device banks. Actual
`implementation is not yet delermined.
`
`1 orO
`
`1 orO
`
`1 orO
`
`BYTE 22 - SDRAM Device Attributes, General
`
`This byte defines various aspects of the SDRAMs on the module. If the aspect is TRUE, then the
`corresponding bit is "1 ",
`
`Blt7
`TBO
`
`Blt6
`TBO
`
`0
`
`0
`
`Bit 5
`Upper Vee
`tolerance:
`0 = 10%
`1=5%
`1 orO
`
`Blt4
`LowerVci;
`tolerance:
`Q; 10%
`1 =5%
`1 orO
`
`Bit3
`Supports
`Write1/Rea
`d Burst
`
`Blt2
`Supports
`Precharge
`All
`
`Bit 1
`Supports
`Auto-
`Pre charge
`
`BltO
`Supports
`Early RAS#
`?recharge
`
`1or0
`
`1 or O
`
`1 orO
`
`1 orO
`
`Vee Tolerance ref era to the voltage range under which the SDRAMs operate to the timings
`specified in the SPO bytes 9, 10, 23-30.
`
`Note for Bytes 23·24: Bytes 23-24 show a roll-up value for Hex 1, 2, 3 (i.e., 1ns/16ns). For
`SDRAM devices over duration of REV 1 in Byte 62 (SPD Jedec Rev level), values of 1-3ns are not
`expected, and Hex equivalent is 16-18ns. Jedec Byte 62 will change rev level when values of 1-3
`ns become available.
`
`BYTE 23 - SDRAM Cycle time (2nd highest CAS latency)
`This field defines the minimum cycle time (clock period) for the SDRAM when operating at its 2nd
`highest CAS latency. For example if the SDRAMs support CAS latency of 3, 2 and 1 (as ·indicated
`in byte 18}, this byte defines Tclk for CAS latency 2. The byte is broken into two nibbles: the high
`order nibble (bits 4 through 7) designate the cycle time to a granularity of 1 ns; the value
`presented by the low order nibble has a granularity of 1/10 ns and is added to the value of the
`higher nibble.
`
`Nanoseconds
`Undefined
`1ns f 16ns
`2ns/ 17ns
`3nsf18ns
`4
`
`Bits 7-4 Hex Value
`0
`1
`2
`3
`4
`
`1110 nanoseconds
`0
`1
`2
`3
`4
`
`Bits 3-0 Hex Value
`0
`1
`2
`3
`4
`
`15
`
`F
`
`9
`
`9
`
`Nov, 1999
`
`20 of 30
`
`Revision 1.28
`
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`Page 2004-20
`
`

`

`.. ·
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`BYTE 24 - SDRAM Access from Clock (2nd highest CAS latency)
`This field defines the maximum clock to data out for the SDRAM (Tac) when operating at its 2nd
`highest CAS latency. For example if the SDRAMs support CAS latency of 3, 2 and 1 (as indicated
`in byte 18), this byte defines Tac for CAS latency 2. The byte Is broken into two nibbles: the high
`order nibble (bits 4 through 7) designate the cycle time to a granularity of 1 ns; the value
`presented by the low order nibble ti as a granularity of 1/10 ns and is added to the value of the
`higher nibble.
`
`Nanoseconds
`Undefined
`1ns / 16ns
`2ns / 17ns
`3ns 118 ns
`4
`
`Bits 7-4 Hex Value
`0
`1
`2
`3
`4
`
`1110 nanoseconds
`0
`1
`2
`3
`4
`
`Bits 3·0 Hex Value
`0
`1
`2
`3
`4
`
`~5
`
`F
`
`9
`
`9
`
`BYTE 25 • SDRAM Cycle time (3rd highest CAS latency)
`This field defines the minimum cycle time (clock period} for the SDRAM when operating at its 3rd
`highest CAS latency. For example if the SDRAMs support CAS latency of 3, 2 and 1 (as indicated
`in byte 18), this byte defines Tclk for CAS latency 1. The byte is broken into two sections: the 6
`high order bits (bits 7:2) designate the cycle lime to a granularity of 1 ns; the value presented by
`bits 1:0 has a granularity of 1/4 ns and Is added to the value of the higher nibble.
`
`Nano$8conds
`
`1/4 nanoseconds
`
`Undefined
`1ns
`2ns
`ons
`4
`
`63
`
`111111
`
`0
`1
`2
`3
`
`Bits 1·0
`blnl!ll'. value
`00
`01
`10
`11
`
`BYTE 26 - SDRAM Access from Clock (3rd highest CAS latency)
`This field defines the maximum clock to data out for the SD RAMs (Tac} when operated at its 3rd
`highest GAS latency. For example if the SDRAMs support CAS latency of 3, 2 and 1 (as indicated
`in byte 18), this byte defines Tac for CAS latency 1. The byte is broken into two sections: the 6
`high order bits (bits 7:2} designate the access time to a granularity of 1 ns; the value presented by
`bits 1 :0 has a granularity of 1/4 ns and is added to the value of the higher nibble.
`
`Nanoseconds
`
`Undefined
`1ns
`2ns
`3ns
`4
`
`Bits 7·2
`Binary Value
`000000
`000001
`000010
`000011
`000100
`
`63
`
`111111
`
`114 nanoseconds
`
`0
`1
`2
`3
`
`Bits 1·0
`Blnary Value
`00
`01
`10
`11
`
`Nov, 1999
`
`21of30
`
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`
`Polaris Innovations LTD Exhibit 2004
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`Page 2004-21
`
`

`

`•
`
`PC SDRAM Serial Presence Detect {SPD) Specification
`
`BYTE 27 ~Minimum Row Precharge Time
`This byte defines the precharge to activate minimum (Trp} using 1 ns granularity.
`
`Precharge Minimum
`
`undefined
`1 ns
`2 ns
`
`30 ns
`
`45 ns
`
`255 ns
`
`Bits 7-0
`Hex Value
`00
`01
`02
`
`1E
`
`20
`
`FF
`
`BYTE 28 ·Row Active to Row Active Min
`This byte defines the minimum row activate to row activate. delay (Trrd} using 1 ns granularity.
`
`Act to Act Minimum
`
`undefined
`1 ns
`2 ns
`
`30 ns
`
`45 ns
`
`255 ns
`
`Bits 7-0
`Hex Value
`o.
`1
`2
`
`1E
`
`20
`
`FF
`
`BYTE 29 • RAS to CAS Delay Min
`This byte defines the minimum RAS to CAS delay (Trcd) using 1ns granularity.
`
`RAS to CAS Delay
`Minimum
`undefined
`1 ns
`2 ns
`
`30 ns
`
`45 ns
`
`255 ns
`
`Bits 7·0
`Hex Value
`0
`1
`2
`
`1E
`
`20
`
`FF
`
`Nov, 1999
`
`22 of 30
`
`Revision 1.28
`
`Polaris Innovations LTD Exhibit 2004
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`Page 2004-22
`
`

`

`•
`..
`
`inteJ.
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`BYTE 30 - Minimum RAS Pulse Width
`
`This byte defines the minimum activate to precharge time (Tras) using 1 ns granularity.
`
`Ac:tlvate to Prec:harge
`Minimum
`undefined
`1 ns
`2 ns
`
`· Bits 7,11
`Hex Value
`0
`1
`2
`
`60 ns
`
`75 ns
`
`90 ns
`
`255 ns
`
`3C·
`
`48
`
`SA
`
`FF
`
`BYTE 31 - Density of Each Row on Module
`
`This byte describes the memory capacity of each physical row on the DIMM module. This byte wm
`have at least one bit set to a "1" to represent at least one row's size. If there is more than one row
`on the module (as represented in Byte 5) and they have the same size, tnen only one bit in this
`field is set. If the module has more than one row of different sizes then more than one bit will be
`set. For example:
`
`#Banks
`I
`2
`2
`
`Size of Row 1
`32MByte
`32MByte
`. 32MByte
`
`Size of Row2
`NIA
`32MByte
`16MByte
`
`Byte 31 contents
`0000 lOOO
`0000 1000
`0000 1100
`
`Size
`
`NN
`
`Bit7
`512MByte
`
`0
`
`-
`
`Blt6
`256MByt
`e
`o·
`
`8115
`12BMByte
`
`1 oro
`
`8114
`64M6yte
`
`Blt3
`32~Byte
`
`1 or O
`
`~,
`
`1 orO
`
`Bit2
`16MByte
`
`1 orO
`
`Bit 1
`BM Byte
`
`1 oro
`
`BltO
`4MByte
`
`1 orO
`
`BYTE 32-35 - Input setup and Hold time (Under JEDEC Committee Ballot no. JC42.5-97-
`119)
`
`Definition of these bytes is in JEDEC Ballot process. The proposed data structure is as defined:
`
`Bit7
`Positive/
`i'l_egative
`1 orO
`
`8115 J
`Time
`
`Blt4
`Inns
`
`Blt6 I
`Setup
`I
`1 orO I
`1 or 0
`1 orO
`1 orO
`Bit 7 = 0 defines a positive setup time w.r.t. the clock
`Bit 7 = 1 defines a negative setup time w.r.t the clock
`Bit 6-4 = Defines the setup time in ns.
`Bit 3-0= Defines the setup time in tenth of a ns.
`
`Blt3
`Setup
`
`I
`
`I
`
`Blt2 J
`Time
`
`1or0
`
`I
`
`Bit 1
`in tenth
`1 or o
`
`I
`
`I
`
`B!tO
`of a os
`
`1 or O
`
`Nov, 1999
`
`23 of 30
`
`Revision 1.28
`
`Polaris Innovations LTD Exhibit 2004
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`Page 2004-23
`
`

`

`•
`
`•
`
`PC SDRAM Serial Presence Detect (SPD) Specification
`
`Some encoded values in the table·
`Blt5
`Blt6
`Blt7
`0
`0
`0
`0
`0
`0
`0
`0
`0
`
`0
`0
`0
`
`0
`0
`
`0
`
`0
`1
`1
`
`1
`1
`1
`
`0
`0
`0
`
`0
`0
`
`1
`
`1
`0
`0
`
`0
`0
`0
`
`0
`0
`
`0
`0
`0
`
`0
`1
`
`1
`
`1
`0
`0
`
`0
`0
`0
`
`Slt4
`0
`0
`0
`
`0
`1
`1 .
`
`1
`0
`
`1
`
`1
`0
`0
`
`0
`1
`1
`
`Blt3
`0
`0
`0
`
`Blt2
`0
`0
`0
`
`Bit 1
`0
`0
`1
`
`Bite
`0
`1
`0
`
`Comment
`Ons
`0.1 ns
`0.2ns
`
`1
`0
`0
`
`1
`0
`
`0
`
`1
`0
`0
`
`1
`0
`0
`
`0
`0
`0
`
`0
`0
`
`0
`
`0
`0
`0
`
`0
`0
`0
`
`0
`0
`
`0
`0
`0
`
`0
`0
`
`0
`
`0
`0
`1
`
`0
`0
`0
`
`1
`0
`1
`
`1
`0
`
`0
`
`1
`1
`0
`
`1
`a
`1
`
`0.9ns
`1.0 ns
`1.1 ns
`
`1.9 ns
`2.0 ns
`
`7.0 ns
`
`7.9 ns
`-0.1 ns
`-0.2 ns
`
`-0.9 ns
`-1.0 ns
`-1.1 ns
`
`-1.9 ns
`-2.0 ns
`
`1
`1
`
`1
`
`1
`x
`
`x
`
`1
`
`1
`x
`
`x
`
`0
`1
`
`1
`
`1
`x
`
`x
`
`1
`0
`
`1
`
`1
`x
`
`x
`
`1
`0
`
`0
`
`1
`1
`
`1
`
`0
`
`0
`0
`
`1
`
`0
`0
`
`0
`
`0
`1
`
`1
`
`1
`0
`
`0
`
`1
`0
`
`1
`
`-7.0 ns
`
`-7.9 ns
`RFU
`RFU
`RFU
`
`BYTE 31- Command and Address signal input setup time:
`
`This byte describes the input setup time w.r.t the rising edge of the clock input. Both positive and
`negative setup times are supported.
`
`Bit 7
`Positve/
`N~ative
`1 orO
`
`Bit G J
`Se11.Jp
`
`Blt5
`Time
`
`1or0 _[
`
`1 orO
`
`J
`
`J_
`
`.Blt4
`inns
`
`1 orO
`
`Bit3
`Setup
`
`1 orO
`
`J
`
`J
`
`Blt2 J
`Time
`
`1 orO
`
`l
`
`Bit 1 J
`in tenth
`1 orO J
`
`BitO
`of a ns
`
`1 er 0
`
`Bit 7 = 0 defines a positive setup time w.r.t. the clock
`Bit 7 "' 1 defines a negative setup time w.r.t the clock
`Bit 6-4 = Defines the setup time in ns.
`Bit 3-0= Defines the setup time in tenth of a ns.
`
`Example:
`For an address input setup time of:
`+2.5ns the byte value will be (0 010 0101)
`Similarly:
`For an address input setup time of:
`-0.5ns the byte value will be (1 000 0101)
`
`Nov,1999
`
`24 of 30
`
`Revision 1.28
`
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`Page 2004-24
`
`

`

`intet.
`
`PC SD RAM Serial Presence Detect (SPD) Specification
`
`BYTE 33 - Command and Address signal input bold time:
`
`This byte describes the input hold time w.r.t the rising edge of the clock input. Both positive and
`~egative hold times are supported.
`
`Blt7
`Positive/
`~ative
`1 orO
`
`·8116 I
`Hold
`
`Blt5
`T1111e
`
`I
`
`Blt4
`Inns
`
`Blt3
`Hold
`
`l
`
`Blt2
`Time
`
`1 orO J_
`
`1 orO
`
`J_
`
`1 or O
`
`1 orO
`
`J_
`
`1 orO
`
`j_
`
`I
`
`Bit 1
`in tenth
`
`1 orO
`
`l
`
`I
`
`Bit 0
`ofa ns
`
`1 orO
`
`Bit 7 = O defines a positive hold time w.r.t. the clock
`Bit 7 = 1 defines a negative hold time w.r.t the clock
`Bit 6-4 = Defines the hold time in ns.
`Bit 3-0= Defines the hold time in tenth of a ns.
`
`Example:
`For a command input hold time of:
`•2.5ns the byte value will be (0 010 0101}
`Similarly:
`For a command input hold time of:
`-0.5ns the byte value will be (1 000 0101}
`
`BYTE 34 - Data signal input setup time:
`
`This byte describes the Input setup time w.r.t the rising edge of the clock input. Both positive and
`negative setup times are supported.
`
`8117
`Positive/
`N~ative
`1 orO
`
`l
`
`Bit5
`Time
`
`1 oro
`
`l
`
`81!4
`Inns
`
`Blt3
`Setup
`
`1or0
`
`I
`
`Blt2
`Time
`
`I
`
`Bit 1
`In tenth
`
`l
`
`BltO
`of ns
`
`.l 1 orO
`
`.l 1 or O
`
`.l
`
`1 orO
`
`8116
`Setup
`I
`1 orO I
`1 oro
`Bit 7 = 0 defines a positive setup time w.r.t. the clock
`Bit 7 = 1 defines a negative setup time w.r.t the clock
`Bit 6-4 = Defines the setup time in ns.
`Bit 3-0= Defines the setup time in tenth of a ns.
`
`Example:
`For a data input setup time of:
`+2.5ns the byte value will be (0 010 0101)
`Similarly,
`For a data input setup time of:
`-0.5ns the byte value will be (1 000 0101}
`
`Nov, 1999
`
`25 of 30
`
`Revision 1.28
`
`Polaris Innovations LTD Exhibit 2004
`Kingston v. Polaris, IPR2016-01622
`Page 2004-25
`
`

`

`..
`
`infel.
`
`PC SDRAM S