infel.
`
`133 MHz PC SCRAM Unbuffered SO-DIMM Specification
`
`133 MHz PC SDRAM 64-Bit Non-ECC/Parity 144 Pin
`UNBUFFERED SO-DIMM SPECIFICATION
`
`REVISION 1.0C
`
`August2000
`
`Revision 1.0C
`
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`
`

`
`\
`
`133 MHz PC SDRAM Unbuffered SO·DIMM Specification
`
`THIS DOCUMENT IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
`INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY
`PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY
`PROPOSAL, SPECIFICATION, OR SAMPLE.
`No license, express or implied, by estoppel or otherwise, to any intellectual property
`rights is granted herein.
`Intel disclaims all liability, including liability for infringem~nt of any proprietary rights,
`relating to implementation of infonnation in this specification. Intel does not warrant or
`represent that such implementation(s) will not infringe such rights.
`
`• Other brands and names are the property of their respective owners.
`
`Copyright Intel Corporation, 2000
`
`August 2000
`
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`
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`
`

`
`133 MHz PC SCRAM Unbuffered SO-DIMM Specification
`
`Changes:
`Revision 1.0c Aug. 23, 2000
`First external copy.
`Added "Y" field in label to help specify if SO-DIMM is buffered or un-buffered (Optional)
`Removed wiring table from page 16.
`Revision 1.0b June 23, 2000
`Review copy.
`Added Gerber release note stating that PC133 Unbuffered SO-DI MM Gerber is
`backward compatible with the PC100 Unbuffered SO-DI MM.
`Removal of the pull-up/pull:.down on WP.
`Require SPD EEPROM to be strapped to allow for write (WP to be shorted to GND).
`Revision 1.0a May 23, 2000
`Updated SO-DIMM naming convention (Added extra characters for the "d" and "e" field.)
`Removed mixed-mode configuration table.
`Revision 1.0 April 28, 2000
`Added support for 512Mb
`Removed A 12/256Mb serial resistor.
`Removed support for 50 pin TSOP package.
`Removed support for 1MX16 devices.
`Removed support for PC100/66 SDRAM for better clarity.
`Copied from PC100/66 SO-DIMM Spec. Rev 1.1
`Revision 1.1 January 25, 2000
`Added pull-up/pull-down option on SPD wlite protect pin.
`Revision 1.0 October, 1998
`Added 256Mbit support, and changed decoupling. ·
`Revision 0.7 August 14, 1998
`Added clock trace length data, and PB marking information.
`Revision 0.51 July 15, 1998
`Added figures 14 and 15
`Revision 0.5 July 14, 1998
`Add support for 66MHz
`Revision 0.3 June 12, 1998
`Removed support of XS components
`Revision 0.22 Aprll 15, 1998
`First external copy.
`
`August 2000
`
`3
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`
`

`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`TABLE OF CONTENTS
`
`LIST OF TABLES .
`
`LIST OF FIGURES
`
`1.0 Introduction
`
`2.0 Environment Requirements
`
`3.0 Mechanical Design
`
`4.0 Module Pinout
`
`5.0 SCRAM SO-DIMM Block Diagrams
`
`6.0 SO-DIMM PCB Layout and Signal Routing
`
`7.0 SO-DIMM PCB and Final Assembly Labeling Requirements
`
`8.0 SCRAM Component Specifications
`
`9.0 EEPROM Component Specifications
`
`10.0 Compatibility
`
`5
`
`6
`
`7
`
`10
`
`11
`
`15
`
`16
`
`18
`
`29
`
`29
`
`29
`
`30
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`

`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`LIST OF TABLES
`TABLE l: RELATED DOCUMENTS
`TABLE 2: SDRAM NON MIXED-MODE MODULE CONFIGURATIONS
`TABLE 3: SO-DIMM REFERENCE DESIGNS
`TABLE 4: SO-DIMM ENVIRONMENT AL REQUIREMENTS
`TABLE 5: SO-DIMM DIMENSIONS AND TOLERANCES
`TABLE 6: SDRAM SO-DIMM PINOUT
`TABLE7:PCBCALCULATEDPARAMETERS
`TABLE 8: SIGNAL TOPOLOGY CATEGORIES
`TABLE 9: TRACE LENGTH TABLE FOR CLOCK TOPOLOGIES
`TABLE 10: TRACE LENGTH TABLE FOR CLOCKS TO ROWS WITH OPTIONAL STUFFING
`TABLE 11: TRACE LENGTH TABLE FOR DATA TOPOLOGIES
`TABLE 12: TRACE LENGTH TABLE FOR DATA MASK TOPOLOGIES (1/2 LOADS)
`TABLE 13: TRACE LENGTH TABLE FOR CHIP SELECT TOPOLOGIES
`TABLE 14: TRACE LENGTH TABLES FOR CLOCK ENABLE TOPOLOGIES
`TABLE 15: TRACE LENGTH TABLE FOR DOUBLE CYCLE SIGNAL TOPOLOGIES
`
`8
`9
`9
`10
`11
`IS
`18
`20
`22
`23
`24
`25
`26
`27
`28
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`
`

`
`133 MHz PC SCRAM Unbuffered SO-DIMM Specification
`
`LIST OF FIGURES
`FIGURE 1: SO-DIMM WITH FOUR 54-PIN SDRAM PER SIDE
`FIGURE 2: SO-DIMM WITH TWO 54-PIN SDRAM PER SIDE
`FIGURE 3: SO-DIMM MECHANICAL DRAWING (l OF 5)
`FIGURE 4: SO-DIMM MECHANICAL DRAWING (2 OF 5)
`FIGURE 5: SO-DIMM MECHANICAL DRAWING (3 OF 5)
`FIGURE 6: SO-DIMM MECHANICAL DRAWING (4 OF 5)
`FIGURE 7: SO-DIMM MECHANICAL DRAWING (5 OF 5)
`FIGURE 8: 64-BIT NON-ECC SO-DIMM BLOCK DIAGRAM (1 ROW, Xl6 SD RAMS)
`FIGURE 9: 64-BlT NON-ECC SO-DIMM BLOCK DIAGRAM (2 ROWS, Xl6 SDRAMS)
`FIGURE 10: EXAMPLE 6-LA YER PCB ST ACKUP
`FIGURE 11: SIGNAL ROUTING TOPOLOGIES FOR CLOCKS
`FIGURE 12: SIGNAL ROUTING TOPOLOGIES FOR CLOCKS TO ROWS WITH OPTIONAL
`· STUFFING
`FI.GURE 13: SIGNAL ROUTING TOPOLOGIES FOR DAT A
`FIGURE 14: SIGNAL ROUTING TOPOLOGIES FOR DATA MASK (1/2 LOADS)
`FIGURE 15: SIGNAL ROUTING TOPOLOGIES FOR CHIP SELECT
`FIGURE 16: SIGNAL ROUTING TOPOLOGIES FOR CLOCK ENABLE
`FIGURE 17: SIGNAL ROUTING TOPOLOOIES FOR DOUBLE CYCLE SIGNALS
`
`1
`7
`12
`I~
`13
`14
`14
`16
`17
`18
`22
`
`23
`24
`25
`26
`27
`28
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`
`

`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`1.0 Introduction
`
`This specification defines the electrical, mechanical, and trace routing requirements for 144-pin, 3 .3 volt,
`133 MHz, 64-bit wide (non-ECC!Parity), 2 clock, unbuffered Synchronous DRAM Small Outline Dual In(cid:173)
`Line Memory Modules (SDRAM SO-DIMMs). These SDRAM SO-DIMMs are intended for use as main·
`memory installed in personal notebook computer motherboards.
`
`-:;Ji~Ot :~
`.·.'fsof.i19·.
`" " '
`~
`
`..
`
`'. TsoP(IQ.
`.
`
`0 Cl Cl
`
`l
`
`Figure 1: SO·CIMM with four 54-pin SCRAM per side
`
`Figure 2: SO-CIMM with two 54-pin SCRAM per side
`
`Related Documents
`
`The related documents contain infonnation that is critical to this specification. The revisions listed are the
`latest releases at the time of this writing. However, it is important to use the most current revisions of each
`of these documents when generating or modifying SO-DIMM designs.
`
`August 2000
`
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`
`

`
`infel.
`
`133 MHz PC SDRAM Unbuffered SO·DIMM Specification
`
`Table 1: Related Documents
`Tm.e
`Intel PC 100 SDRAM Sjl_ecification
`Intel PC 133 SDRAM S_Q_ecification
`Intel SDRAM SPD Data Structure Specification
`
`REV
`DATE
`1.63 Oct. 1998
`1.7 Nov. 1999
`1.28 Nov.1999
`
`August2000
`
`8
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`
`

`
`infel.
`
`133 MHz PC SCRAM Unbuffered SO·DIMM Specification
`
`SO-DIMM Configurations
`SD RAM SO-DIMM configurations are defined in the following tables:
`
`Table 2: SDRAM Non Mixed-Mode Module Configurations
`
`Co11tig
`#
`I
`2
`3
`4
`5
`6
`7
`8
`
`SO-DIMM
`C'!i!!'c..!!l.
`32MB
`64MB
`64MS
`!28MB
`128MB
`256MB
`256MB
`512MB
`
`SO.DIMM
`0..!&.anlzntion
`4MX64
`8MX64
`8MX64
`16MX64
`16MX64
`32MX64
`32MX64
`64MX64
`
`SD RAM
`dens!tt_
`64Mbit
`64Mbit
`128 Mbit
`128Mbit
`256Mbit
`256Mbit
`.512Mbit
`512Mbit
`
`#or
`SD RAM
`<!!:!!ln!zatfon SDRAMs
`4
`4MXl6
`4MX16
`8
`4
`8MXl6
`8
`8MXl6
`16MX16
`4
`16MXl6
`8
`4
`32MX16
`32MXl6
`8
`
`# Row$Of
`SDRAM
`l
`2
`1
`2
`I
`2
`1
`2
`
`# Ba11kll In
`SD RAM
`4
`4
`4
`4
`4
`4
`4
`4
`
`# Address bib
`row/baaklcol
`121218
`121218
`1212/9
`!Y2/9
`131219
`13/2/9
`13/2/10
`13/2110
`
`The following PC133 SO-DIMMs will be designed at Intel and offered as reference designs.
`Table 3: SO-OIMM Reference Designs
`
`Coofig#
`
`1131511
`
`2/4/6/8
`
`SO-DIMM
`Caiac.!!I_
`32MB/64MB/
`128MB1256 MB
`64MB/ 128 MB/
`256 MB/ 512 MB
`
`SD RAM
`dens!tt_
`64, 128, 256,
`512Mbit
`64, 128, 256,
`512Mbit
`
`SD RAM
`Q!g_anlzatlon
`4MXl6/8MXl6/
`16MX16 I 32MX16
`4MX16/8MX16/
`16MX16 / 32MX16
`
`#Rowsor_
`SD RAM
`I
`
`#Banks In
`SD RAM
`4
`
`Size or
`SO-DJMM
`1.00
`
`Corresponding
`F,!2.re
`Figure 2
`
`2
`
`4
`
`1.25
`
`Figure I
`
`Distinction between "banks" and "rows"
`
`This docwnent only uses "banks" when referring to banks of memory internal to the SDRAM component
`(two or four). "Rows" is used to define the number of sets of SD RAMs on the SO-DIMM that collectively
`make up 64 bits of data.
`·
`
`August 2000
`
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`
`

`
`133 MHz PC SCRAM Unbuffered SO-DIMM Specification
`
`2.0 Environmental Requirements
`
`The SDRAM SO-DIM:M shall be designed to operate within a notebook personal computer in a variety of
`environments. The temperature and humidity limits are as follows.
`
`Table 4: SO-DIMM Environmental Requirements
`
`, noncondensin
`
`5% to 95% without condensation
`to 50,000 ft. at 50 °C
`1.682 PSI
`
`Safety - UL Rating
`
`Printed circuit board to have a flammability rating of 94V-O Markings to include UL tractability
`requirements per UL Recognized Component Directory.
`
`August2000
`
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`
`

`
`infel.
`
`133 MHz PC SORAM Unbuffered SO-DIMM Specification
`
`3.0 Mechanical-Design
`The following table and drawings give the specific dimensions and tolerances for a 144-pin SO-DIMM.
`Table 5: 50-DIMM Dimensions and Tolerances
`SYMBOL
`A
`
`DEFIN1110N
`Overall module height measured
`from Datum -B-.
`The distance from Datum -B- to the
`centerline of the PWB alignment
`holes
`
`MIN
`25.25mm
`31.60mm
`
`NOM
`25.40mm
`31.75 mm
`6.00 mm BASIC
`
`MAX
`25.55mm
`31.90mm
`
`NOTES
`Two sizes available: "! inch"
`and "J.2S inch';.
`These holes are not used by the
`next level of assembly. The
`dimensions are supplied for
`information only. If the holes are
`used in manufacturing they
`should be tightly tolemnced. The
`recommended positional
`tolerance is 0.10 nun.
`
`Al
`
`A1
`
`A.3
`
`A4
`
`D
`DI
`
`D2
`
`03
`
`04
`
`. DS
`
`E
`
`el
`
`e2
`
`The distance from Datum -B- to the
`lower edge of the Component Area
`on the front side of the PWB.
`The distance from Datum -B- to the
`lower edge of the Component Area
`on the back side of the PWB.
`
`The distance from Datum -B- to the
`centerline of the latch boles
`The overall lenilih of the PWB
`The distance between the centerline
`of the contact at the immediate left
`of the key zone and the inner edge
`of the left latch hole.
`The distance between the inner edge
`of the latch holes
`The distance between Datum -A·
`and the center of the contact at the
`immediate left of the key zone on
`the front side of the PWB.
`The distance between Datum -A-
`and the center of the contact at the
`immediate left of the key zone on
`the backside of the PWB.
`The distance between the centerline
`ofD Datum -A-.
`The overall thickness of the PWB
`with the components mounted. The
`overall thickness is measured from
`the highest component on the front
`side to the highest component on
`the backside
`The distance between the centerline
`of the contact to the immediate left
`of the key zone and the center of the
`left most contact.
`The distance between the centerline
`of the contact to the immediate right
`of the key zone and the center of the
`r:!g_ht most contact,
`
`3.2mm
`
`4.0mm
`
`20.00 mm BASIC
`
`67.45 mm
`
`67.60nun
`24.SO mm BASIC
`
`67.75mm
`
`Dimensions applicable when
`components mounted on both
`sides. Application note: border
`of component area.
`
`The position oflhe notch
`indicates that the operating
`voltage is 3.3 Volts. The
`centerlines of contacts on the
`front side of the PWB are not
`coincident with.the centerlines of
`contacts on the backside of the
`PWB
`
`3.80 mm
`
`Dimensions applicable when
`components mounted on both
`sides.
`
`63.60 mm BASIC
`
`2.50 mm BASIC
`
`2.10 mm BASIC
`
`4.80 mm BASIC
`
`23.20mmBASIC
`
`32.80 mm BASIC
`
`August2000
`
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`
`

`
`133 MHz PC SCRAM Unbuffered SO·DIMM Specification
`
`~OFD
`I D - - - - i
`l~!o. 1~lclelAI
`!
`---102
`'
`
`~ l--mJ
`
`I ~(DATUM Al
`Vi A~
`
`1.80
`2K
`OPT lONAl HQL[S
`l~ l¢o. to~ !clslAI
`
`Pl N 144
`
`· '
`
`,~
`
`,
`
`l.;
`
`,
`
`,
`
`,
`
`/
`,,·'
`
`/ / ! / /
`,·'
`,,·'
`.. I"
`,·'
`
`/
`,·'
`
`4.00±0.10
`
`,
`
`·''.
`
`,
`
`·''.
`
`/
`,·'
`
`fULL R
`
`2xR3.00 MIN.
`
`,,·' ·~· ·"·
`,/ ... // .-19Aacf'" , .• / ,./ _[I~ 1¢ o. 1 o§l !c I a I A I
`n
`f
`.-+
`,·'
`I
`r
`Figure 3: SO-DIMM Mechanical Drawing (1 of 5)
`
`<DATUM AJ /
`
`2.00 MIN.
`2X
`
`August 2000
`
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`
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`
`

`
`ifltel.
`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`A2
`
`j_
`
`VIH/' A-A
`
`Figure 4: SO-DIMM Mechanical Drawing (2 of 5)
`
`&4.00
`
`CDATUM Al
`
`4. 00±0.10
`t
`
`DETAIL Z(cid:173)
`SCALE 511
`
`Figure 5: SO-DIMM Mechanical Drawing (3 of 5)
`
`f
`0.25 MAX.
`
`DETAIL Y
`SCALE 5/ I
`
`August2000
`
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`
`

`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`Figure 6: SO-DIMM Mechanical Drawing (4 of 5)
`
`NOTES
`
`1 DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M-1994.
`
`2 TOLERANCES ON ALL DIMENSIONS+/- 0.15 UNLESS OTHERWISE
`SPECIFIED.
`
`3 ALL DIMENSIONS ARE IN MILIMETERS.
`
`& APPLICATION NOTE:
`
`VARYING THE POSITION OF THE NOTCH IDENTIFIES THE OPERATIONAL
`VOLTAGE. THE SO-DIMMS GENERATED FROM THIS SPECIFICATION
`OPERATE USING A VDDQ VOLTAGE OF 3.3 VOL TS.
`& DIMENSION APPLICABLE WHEN COMPONENTS MOUNTED ON BOTH
`
`SIDES
`
`_&CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING
`AND/OR METALIZATION.
`.
`
`fb. APPLICATION NOTE:
`RECOMMENDED PLATING FOR CONTACT PADS SHALL BE
`ELECTROLYTIC GOLD PLATING 0. 76 MICROMETER MIN.
`OVER NICKEL PLATING 2 MICROMETER MIN .
`
`.ffiAPPLICATION NOTE:
`. BORDER OF COMPONENf AREA.
`
`Figure 7: SO-DIMM Mechanical Drawing (5 of 5)
`
`Explanation ofSO-DIMM Keying
`
`All SO-DIMMs generated from this spec should have a notch cut into the edge connection that conveys
`information on the voltage of the SO-DIMM. The notch should be positioned between SO-DIMM pins 59
`and 61 and should be centered between the two pins. This signifies that the SO-DIMM operates using a
`Vddq voltage of3.3 Volts. Please see the mechanical drawings above for ex.act dimensions and placement
`of the notch.
`
`August2000
`
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`

`
`133 MHz PC SCRAM Unbuffered SO·DIMM Specification
`
`4.0 Module Pinout
`The following table provides the 144-pin, 64-bit unbuffered SO-DIMM module connector pinout. Note that
`all odd-numbered pads reside on the primary (front) side of the SO-DIMM card, and all even-numbered
`pins reside on the secondary (back) side of the card.
`
`Table 6: SORAM SO·DIMM pinout
`
`SigoalName
`
`Signal Name
`
`Signal Name
`
`Pin
`
`V..ss_
`_l_
`QQQ_
`3
`·s
`QQJ
`D..Q..2
`.7
`003
`9
`Vdd
`II
`D..Q..4
`13
`D_ID
`15
`DQ6
`17
`n_m
`19
`Vss
`21
`QQ.MBO
`23
`QQ_MBI
`25
`'27
`Vdd
`AO
`29
`' 31
`Al
`' 33
`A2
`Vss
`35"
`~ 37
`009
`39
`0010
`41
`43
`_OQll
`Vdd
`4S
`47'
`l)Ql2
`QQ_l3
`49
`0014
`51
`D..Q..15
`53
`SS
`Vss
`Reserved
`51
`Reserved
`59
`
`Pin
`-2
`4
`6
`8
`10
`'12
`14
`16.
`18
`20
`22
`' 24
`'26 '
`28
`'30
`32
`34
`36
`. 38
`40
`42
`44
`46
`48
`so'
`52·
`54
`56
`58
`60
`
`Vrt<
`0032
`@;!3
`@;!4
`D_Q35
`Vdd
`D_.Q'.36
`DQ37
`D_ID8
`D...039
`Vss
`oQ_MB4
`QQ_MBS
`Vdd
`A3
`A4
`AS
`Vss
`D040
`QQ!J
`0012
`D043
`Vdd
`D044
`DQ45
`0046
`0017
`Vss
`.R.escrved
`Reserved
`
`CLKO
`62
`61
`Vdd
`63
`64
`RAS#
`66
`65
`WE#
`' 67
`68
`SO#
`69
`70
`Note: Reserved = Do not connect
`
`: :., '' '
`CKEO
`Vdd
`CAS#
`CKE!
`Al2
`
`_SllL
`Reserved
`Vss
`Reserved
`Reserved
`Vdd
`QQ.!6
`QQ.!7
`QQ.!8
`QQ.!9
`Vss
`0020
`0021
`D..Q..22
`.0023
`Vdd
`A6
`A8
`Vss
`A9
`AlO
`Vdd
`D_Q_MB2
`QQ_MB3
`Vss
`0024
`0025
`0026
`0027
`Vdd
`0028
`D_Q29
`o_mo
`D_fill
`Vss
`SDA
`Vdd
`
`Pin
`
`-1.L
`73
`75
`77
`'79
`81
`83
`'85
`' 87
`'89
`91
`93
`95
`'97
`99
`'101
`103
`105
`107
`109
`· 111
`113
`ll5
`117
`119
`121
`123
`125
`127
`129
`131
`la3
`135
`137
`139
`141
`143
`
`Pia
`
`Signal Name
`
`_I},_
`74
`76
`78
`80
`82
`' &4
`86
`88
`90
`92
`94
`96
`98
`100
`102
`104
`106
`' 108'
`110
`112
`114
`116
`118
`120
`l22
`124 '
`126
`128
`130
`132
`134
`136 '
`138
`140
`142
`144
`
`..All
`CLKI
`Vss
`Reserved
`Reserved
`Vdd
`D_.00
`0~9
`D~O
`0.051
`Vss
`D_QS2
`D~3
`QQ?4
`D_Q55
`Vdd
`A7
`BAO
`Vss
`BAI
`All
`Vdd
`QQ.MB6
`QQ_MB7
`Vss
`D_QS6
`D_ID7
`D...058
`D.Q,59
`Vdd
`Q.Q§O
`D.061
`D..Q..62
`D-2§3
`Vss
`set
`Vdd
`
`August 2000
`
`15
`
`Revision 1.oc
`
`Polaris Innovations LTD Exhibit 2003
`Kingston v. Polaris, IPR2016-01622
`Page 2003-15
`
`

`
`133 MHz PC SDRAM Unbuffered SO·DIMM Specification
`
`5.0 SCRAM SO-DIMM Block Diagrams
`
`DOM4
`D0(39:32)
`
`DOM5
`00(47:40)
`
`DQM6
`D0(55:48)
`
`DOM7
`D0(63:56}
`
`10
`
`10
`
`10
`
`10
`
`02
`
`03
`
`CKEOO
`
`!RASO
`/CASO
`IWEQ
`A(12:0) 0
`BS(1:0} 0
`
`> CKE: SDRAM DO - D3
`
`> {RAS: SDRAM DO - D3
`> ICAS: SDRAM DO - D3
`> !WE: SDRAM DO - D3
`> A(12:0): SDRAM DO • 03
`> BS(1 :0): SDRAM 00 • 03
`
`ISO
`
`DQMO
`D0(7:0)
`
`DOM1
`00(15:8)
`
`DO
`
`10
`
`10
`
`OQM2 Lr-----1
`00(23:16} { }---.JV\,.,,._--1
`10
`
`01
`
`DQM3 < > - - - - - -1
`D0(31 :24) 0---.Ml'l'----l
`10
`
`-----
`
`'-"
`
`SCL
`WP
`SA2
`SA1
`SAO
`
`""
`
`SERIAL PD
`
`,...
`'-J SDA
`
`Note: SPD EEPROM should
`be strapped to allow for writes.
`
`CKO Oc-----'l)SDRAM DO - D3
`
`CK1 Q--.1.iN--,
`-
`"1ii
`
`..1..10pF r
`
`VDDO
`
`> SDRAM DO - D3
`J_ Recommended bypass;
`T Three0.1~FX7R0603
`per SDRAM device
`VSS 0---'-~) SDRAM DO - 03
`
`Note: To obtain most advantageous board layout, byte lanes may be swapped. Bits within a byte may also be
`swapped, however, bits between bytes may not be swapped.
`
`Figure 8: 64-bit non-ECC SO-DIMM Block Diagram (1 Row, x16 SDRAMs}
`
`August2000
`
`16
`
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`
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`Kingston v. Polaris, IPR2016-01622
`Page 2003-16
`
`

`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`DO
`
`04
`
`10
`
`D1
`
`05
`
`10
`
`SERIAL PD
`
`OQM4
`00(39:32)
`
`OQM5
`D0(47:40)
`
`DOM6
`00(55:48)
`
`DOM7
`D0(63:56)
`
`10
`
`10
`
`10
`
`10
`
`02
`
`06
`
`03
`
`07
`
`...,
`
`SDA
`
`CKE1 0-----> CKE: SDRAM 04 - D7
`> CKE: SCRAM DO • 03
`CKEO 0
`
`IRAS 0
`/CAS 0
`!WE 0
`A(12:0) 0
`BS(1 :0) 0
`
`> /RAS: SDRAM DO - 07
`> /CAS: SDRAM DO • 07
`> !WE: SDRAM DO· D7
`> A(12:0): SDRAM DO· 07
`> BS(1 :0): SCRAM DO·
`
`infel.
`
`/SO
`
`DQMO
`DQ(7:0)
`
`DQM1
`D0(15:8)
`
`DQM2
`D0(23:16)
`
`DOM3
`00(31:24)
`
`SCL
`WP
`SA2
`SA1
`SAO
`
`...,
`
`+
`
`Note: SPD EEPROM should
`be strapped to allow for writes.
`
`CKO 01----7> 4 LOADS
`CK1 0
`) 4 LOADS
`
`VDD O-........,...-.,.,,)SDRAM DO· 07
`Recommended bypass:
`Three 0.1uF X7R 0603
`per SDRAM dev!ce
`_
`VSS O>--........ -i>SDRAM DO • 07
`
`I
`I
`
`Note: To obtain most advantageous board layout, byte lanes may be swapped. Bits Within a byte may also be
`swapped, however, bits between bytes may not be swapped.
`
`Figure 9: 64·bit non-ECC SO-DIMM Block Diagram (2 Rows, x16 SDRAMs)
`
`August2000
`
`17
`
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`
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`Page 2003-17
`
`

`
`133 MHz PC SDRAM Unbuffered SQ..DIMM Specification
`
`6.0 SO·DIMM PCB Layout and Signal Routing
`
`Printed Circuit Board
`The SQ..DIMM printed circuit board shall be at lea.st a six layer stack-up using glass epoxy material. The
`PCB must have both a full ground plane layer and a full power plane layer. The required signal trace
`impedance is 55Q±l5%. Components shall be of surface mount type, and may be mounted on one or both
`sides of the PCB.
`
`Table 7: PCB Calculated Parameters
`
`Parameter
`Propagation delay: So {ps/in] (oiJter layers)
`
`Propagation delay: 80 [ps/in] (inner layers)
`Trace impedance: Z., [O] (all layers)
`
`Min
`
`Max
`
`141
`
`167
`
`47
`
`153
`
`180
`
`63
`
`--r-----------
`
`Signal Layer
`
`Layer 1
`
`Ground Layer
`
`Layer 2
`
`1.0mm +l-0.1mm
`
`Signal Layer
`
`Layer3
`
`Signal Layer
`
`Layer 4
`
`Power Layer
`
`Signal Layer
`
`Layer6
`
`Layer 5
`
`Figure 1 O: Example 6-layer PCB Stackup
`
`August2000
`
`18
`
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`
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`Kingston v. Polaris, IPR2016-01622
`Page 2003-18
`
`

`
`infel.
`
`Edge Connection
`
`133 MHz PC SDRAM Unbuffered SO·DIMM Specification
`
`The PCB edge connector contacts shall be gold plated per Figure 7, Note 7. Note: The PCB connector edge
`will not be chamfered.
`
`EMI Reduction
`
`To minimize radiation from clock traces on the SO-DIMMs, the following are requirements:
`
`• Clocks must be routed with as much of the trace on an inner signal layer as possible.
`• Clocks on the inner layer will have a 5 mill ground trace surrounding them, with vias stitched to
`ground at 0.5'' intervals, or as often as routing allows.
`• Both internal signal layers and the power plane should have a ground ring routed around the
`perimeter of the board and stitched to ground at intervals <0.5''. The ground rings should be on
`the order of 20 mils wide, but can be reduced to l 0 mils in areas where 20 mils cannot· be
`·
`accommodated.
`
`Component Types and Placement
`
`Components shall be of surface mount type, and. may be mounted on one or bath sides of the PCB.
`Components shall be positioned on the PCB to meet the min and max trace lengths required for SDRAM
`data signals. Bypass capacitors for SDRAM devices must be located as near as practical to the device
`power pins. It is·also important to place each SDRAM in the optimum position to ensure meeting of trace
`length and topology requirements. Pin swapping of data pins within individual bytes should also be used
`for the same reason.
`
`Ex.act spacing numbers are not provided, but are left up to the SO-DIMM manufacturer to determine based
`on manufacturing constraints and signal routing constraints imposed by this specification.
`
`August 2000
`
`19
`
`Revision 1.0C
`
`Polaris Innovations LTD Exhibit 2003
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`Page 2003-19
`
`

`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`Signal ~roups
`
`In this specification, the SDRAM timing-critical signals have been divided into groups whose members
`have identica1 loading and routing topologies. The following table summarizes the signal groups by listing
`the signals contained in each. The following sections will descnbe routing restrictions associated with each
`signal group.
`
`Table 8: Signal Topology Categories
`
`SIGNAL GROUP·.
`
`SIGNALS IN GROUP
`
`Clock
`
`Data
`
`Data Mask
`
`ChJJ! Select
`
`CLKJJ:Qi
`
`QQJ.63:Ql
`
`im_MB_L7:Ql
`
`Stt[_l:Ql
`
`Clock Enable
`
`CKEll:l!J.
`
`Double ~le s~ls
`
`..Af.12:Ql
`B~l:l!J.
`RAS#
`CAS#
`WE#
`
`Signal Topology and Length Restrictions
`
`In order to meet signal quality and setup/hold time requirements for the memory interface, certain routing
`topologies and trace length requirements must be met. The signal topology requirements are shown
`pictorially in the following pages. Each topology diagram is accompanied by a trace length table that lists
`the minimum and maximum lengths allowed for each trace segment and, where applicable, the min and max
`lengths for the entire net. Each diagram also shows where vias are allowed or includes a note that specifies
`where vias are allowed if they are not shown in the diagram.
`
`Routing Rules
`
`General Info:
`
`All signal traces except clocks are routed using 5/5 rules.
`(5 mil traces and 5 mil minimum spacing between adjacent traces).
`
`Clocks are routed using 5 mil traces and 5 mil space to the 5 mil ground trace.
`
`No test points are required.
`
`August 2000
`
`20
`
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`
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`Page 2003-20
`
`

`
`..
`
`intet. ·
`
`133 MHz PC SDRAM Unbuffered SO·DIMM Specification
`
`Topology Diagram Eitplanation
`
`The routing topology diagrams in this section are intended to be used to determine individual signal
`topologies on a SO-DIMM for any supported configuration.
`
`These diagrams are read as follows:
`
`Only the cylinders labeled with length designators represent actual physical trace segments. All
`other lines should be considered zero in length .
`
`. All loads and traces outside of the dashed boxes constitute the base topology which covers the
`minimum loading case for each signal.
`·
`
`Allowed vias are either shown as circles on the topology diagrams or are otherwise documented
`under. each diagram in a separate note.
`
`The topology for a given configuration can be determined by adding the traces and loads within the
`dashed boxes to the base topology. Add only the traces and loads within boxes that apply for the
`desired configuration.
`
`The permitted segment length ranges for that topology are read from the table below each topology
`diagram.
`
`August2000
`
`21
`
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`Page 2003-21
`
`

`
`..
`
`133 MHz PC SCRAM Unbuffered SO·DIMM Specification
`
`Topology for Clock: CLK(l:O)
`
`Special attention must be given to the routing of the SDRAM clock signal(s) to ensure adequate signal
`quality, rise/fall time, minimum skew between clock edges at each SDRAM component, and predictable
`skew to motherboard chipset clocks. For that reason, all utilized clocks are made to look electrically similar
`by loading them with exactly four SDRAM loads. Clock signals must have either four SDRAM loads, or
`they must be terminated into 10 ohms and 10 pf. Trace lengths to the RC termination of unloaded clocks
`must be kept to an absolute minimum. Clock traces must be 5 mils wide with 15 mil spacing to any other
`signal including the clocks themselves.
`
`SD RAM
`Pin
`
`Loaded
`Clock
`
`SORAM .__,,,. L_,,._..-~o_i
`Pin
`
`SO-DIMM
`H=J---0----8--:=-:J-- Connector
`
`Unloaded
`... c_io_c_k _ _ SO·DIMM
`Connector
`
`100hm
`
`10 pF
`
`I Stuff for
`Unloaded
`-=- Clock
`
`Note: Either the L2 or the L3 trace segment may contain one additional via which is not
`shown in the diagram.
`Figure 11: Signal routing topologies for Clocks
`
`Table 9: Trace Length Table for Clock Topologies
`Total Min I Total Max J
`I
`]
`2.55
`2.45
`
`$1!9._ment
`L4
`L1
`LO
`L3
`L2
`0.10
`0.80
`1.00
`Lel!D!_h
`0.50
`0.10
`Tolerance
`±0.05 ±0.02 ±0.02 ±0.02 ±0.05
`Outer
`Inner
`La}"er
`Inner Outer
`Inner
`..
`1 All distances are g1v.en 1n inches and should be kept within tolerance, and routed on the indicated layer.
`2 Total Min and Total Max refer to the min and max respectively of LO + L 1 + L2 + L3 + L4. Also, the total
`min and max limits are tighter than the sum of the individual min and max lengths. This implies that not
`all individual segment lengths may be adjusted to the min or max value at the same time.
`
`August2000
`
`22
`
`Revision 1.0C
`
`Polaris Innovations LTD Exhibit 2003
`Kingston v. Polaris, IPR2016-01622
`Page 2003-22
`
`

`
`133 MHz PC SDRAM Unbuffered SO·DIMM Specification
`
`Topology for Clock with an option to not stuff a row of SDR.AM: CLK[l I
`
`If the PB is designed with the option to not stuff a row ofSDRAM, a jumper must be included to disconnect
`the clock tree from the RC termination. The overall length of the net from the SO-DIMM pin to the
`SDRAM pin, through the jumper, must be the same as for clocks without this option. The diagram and
`table below explain this. In the picture, LO is the sum of the trace lengths on both sides of the 00 jmnper,
`and the distance through the 00 jumper. Trace lengths to the RC tennination must be kept to an absolute
`minimum.
`
`Clock For Optional Row
`OfSDRAM
`
`SDRAM •. _...,~-. __ ...,., ~~,
`Pin
`
`SDRAM ._.,,------~_,..c~~,
`Pin
`
`I
`I
`
`I
`I
`I Stuff for 1
`\... - - -
`J
`
`10 pF
`
`Unloaded
`"="' Clock
`
`Note: Either the L2 or the L3 trace segment may contain one additional via which is not
`shown in the diagram.
`Figure 12: Signal routing topologies for Clocks to Rows with Optional Stuffing
`
`Table 10: Trace Length Table for Clocks to Rows with Optional Stuffing
`Total Min I Total Max]
`l
`2.55
`]
`2.45
`
`.LO
`L1
`81!9._ment
`L2
`L3
`L4
`Lef!9!h
`0.85
`0.25
`0.80
`0.10
`0.50
`Tolerance
`±0.05 ±0.02
`±0.02 ±0.02 ±0.05
`Lqer
`Outer
`Inner
`Inner
`Inner Outer
`. '
`1 All distances are given 1n inches and should be kapt within tolerance, and routed on the indicated layer .
`2 Total Min and Total Max refer to the min and max respectively of LO + L 1 .+ L2 + L3 + L4. Also, the total
`min and max limits are tighter than the sum of the Individual min and max lengths. This implies that not
`all individual segment lengths may be adjusted to the min or max value at the same time.
`
`August 2000
`
`23
`
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`
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`Page 2003-23
`
`

`
`133 MHz PC SCRAM Unbuffered SO·DIMM Specification
`
`Topology for Data: DQ[63:0l
`
`These signals are routed using a balanced "T' topology on any layer. The table defines the line length
`ranges allowed for these signals.
`
`Figure 13: Signal routing topologies for Data
`
`SO-bl MM
`Connector
`
`LO
`
`10 ohms +I· 5%
`
`L1
`r-
`
`L2
`
`SD RAM
`Pin
`
`SD RAM
`Pin
`
`Included for 2 Row SO·DIMM
`
`Total Min Total Max
`
`Note: The L 1 trace segment may contain up to 2 additional vias which are not
`shown in the diagram.
`Table 121: Trace Length Table for Data Topologies
`LO
`LO
`L1
`L2
`L1
`#of
`Comp
`L2
`Width
`loads Min Max Min Max Min Max
`0.10 0.50
`X16
`112
`0
`0.90
`0
`0.25
`1 All distances are given m inches
`2 Total Min and Total Max refer to the min and max respectively of LO+ L 1 + L2. Also, the total
`min and max limits are tighter than the sum of the individual min and max lengths. This
`implies that not all individual segment lengths may be adjusted to the min or max value at the
`same time.
`
`0.60
`
`1.00
`
`August2000
`
`24
`
`Revision 1.0C
`
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`Page 2003-24
`
`

`
`133 MHz PC SCRAM Unbuffered SO-OIMM Specification
`
`Topology for Data Mask: DQMB[7:01
`
`These signals are routed using a balanced "T" topology on any layer. The tables define the line length
`ranges allowed for these signals.
`
`SO-DI MM
`Connector
`
`LO
`r - - - - - - - - - -,
`e==:r--.~a:=::::J
`I
`L1
`I
`I
`I
`I
`I
`I
`
`SDRAM
`Pin
`
`SDRAM
`Pin
`
`Included for 2 Row SO·DIMM
`
`Note: The LO trace segment may contain 1 additional via which is
`not shown in the diagram.
`Figure 14: Signal routing topologies for Data Mask (1/2 Loads)
`
`Table 132: Trace Length Table for Data Mask Topologies (1/2 Loads)
`
`Comp
`Width
`X16
`
`#loads
`
`LO Min
`
`LO Mai:
`
`L1 Min
`
`L1 Max Total Min Total Max
`
`0.75
`1/2
`1.10
`All distances are given in Inches
`
`0.00
`
`0.30
`
`1.00
`
`1.40
`
`August2000
`
`25
`
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`
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`Page 2003-25
`
`

`
`133 MHz PC SDRAM Unbuffered SO-DIMM Specification
`
`Topology for Chip Select: S#(l:O)
`
`This signal is routed using a balanced "comb" topology on any layer. The table below defines the line
`length ranges allowed for these signals.
`
`' ..
`
`SDRAM
`Pin
`
`SO RAM
`Pin
`
`SD RAM
`Pin
`
`SD RAM
`Pin
`
`Note: The LO trace may contain up to 2 vias which are not shown in
`the diagram.
`Figure 15: Signal routing topologies for Chip Select
`
`Table 143: Trace Length Table for Chip Select Topologies
`
`Comp
`Width
`x16
`
`L1
`#of
`LO
`L3
`L3
`L2
`L2
`L1
`LO
`loads Min Max Min Max Min Max Min Max
`4
`0.50
`0.50
`0.10
`0.0
`0.60
`0.05
`0.35
`1.10
`1 All distances are given In Inches.
`2 Total distance is LO+L 1+L3 or LO+L 1+L2+L3. SO-DIMM connector to SDRAM Pin.
`
`·
`
`Total Total
`Min Max
`1.00
`2.30
`
`August2000
`
`26
`
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`
`

`
`infel.
`
`133 MHz PC SCRAM Unbuffered SO·DIMM Specification
`
`Topology for Clock Enable: CKE#[l:O)
`
`' .
`
`This signal is routed using a balanced "comb" topology on any layer. The table below defines the line
`length ranges allowed for each trace segment.
`
`SCRAM
`Pin
`
`SCRAM
`Pin
`
`SCRAM
`Pin
`
`SORAM
`Pin
`
`Note: The LO trace may contain up to 2 vias which are not shown in
`the diagram.
`Figure 16: Signal routing topologies for Clock Enable
`
`Table 154: Trace Length Tables for Clock Enable Topologies ·
`
`Comp
`Width
`x16
`
`Total
`#of
`L3
`L3
`L2
`L2
`L1
`LO
`LO
`L1
`loads Min Max Min Max Min Max Min Max Min
`o.o
`o.o
`1.00
`1.0
`4
`0.50
`1.10
`0.05
`0.35
`0.50
`1 All distances are given in inches.
`2 Total distance is LO+L 1+L3 or LO+L 1+L2+L3. SO·DIMM connector to SDRAM Pin.
`
`Total
`Max
`2.3
`
`August2000
`
`27
`
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`
`

`
`133 MHz PC SDRAM Unbuffered SO·DIMM Specification
`
`Double Cycle Signals: MAx, BAx, SRAS#, SCAS#, WE#
`
`These signals are routed using a balanced, doubl