Kingston Technology Company, Inc. (Petitioner)
`v.
`Polaris Innovations LTD (Patent Owner)
`Original Claims Demonstratives
`Trial No. IPR2016-01622
`U.S. Patent No. 6,850,414
`
`Before Hon. Hon. S. C. MEDLEY, J. R. HOMERE, and M. R. CLEMENTS,
`Administrative Patent Judges
`
`1
`
`KINGSTON 1025
`Kingston v. Polars
`IPR2016-01622
`
`
`v.
`Polaris Innovations LTD (Patent Owner)
`Original Claims Demonstratives
`Trial No. IPR2016-01622
`U.S. Patent No. 6,850,414
`
`Before Hon. Hon. S. C. MEDLEY, J. R. HOMERE, and M. R. CLEMENTS,
`Administrative Patent Judges
`
`1
`
`KINGSTON 1025
`Kingston v. Polars
`IPR2016-01622
`
`
`
`Overview
`
`• Consideration of patentability of amended claims
`
`•
`
`Introduction to the Claims
`
`• Simpson in view of either the Intel Specification or Karabatsos render
`substitute Claim 9 obvious
`
`• Response to Patent Owner’s arguments
`
`• Arbitrary height limitations are not entitled to patentable weight
`
`• Bechtolsheim in view of Tokunaga and Karabatsos renders substitute
`Claim 9 obvious
`
`• Kiehl provides evidence of memory chip sizes contemporaneous with
`the ’414 patent
`
`2
`
`
`
`Consideration of Patentability of Amended Claims
`
`‐ Under Aqua Products, the Board is obligated to consider patentability of
`amended claims.
`“[35 U.S.C. §] 316(e) reaches every proposition of unpatentability at issue
`in the proceeding.”
`Aqua Products, 2017 WL 439000 at *10.
`“When a petitioner does contest an amended claim the Board is free to
`reopen the record to allow admission of any additional relevant prior art
`proffered by a petitioner . . . The Board may consider all art of record in
`the IPR, including any newly added art, when rendering its decisions on
`patentability.”
`Aqua Products, 2017 WL 439000 at *17.
`‐ Patent Owner’s reliance on Amerigen Pharms. Ltd. v. Shire LLC, IPR2015‐02009
`to justify patentability of substitute Claim 9 is unfounded because Amerigen:
`1) is not precedential and
`2) applies to an unrelated set of facts – removing a multiple dependency is
`clearly distinct from adding a limitation to a claim.
`
`3
`
`
`
`Consideration of Patentability of Amended Claims
`
`Non‐Institution decision(s) on Claim 4 are not binding because the Board made
`no decisions on patentability.
`
`IPR2017-00974, Paper 11 at 5.
`
`4
`
`
`
`Canceled Claim 1
`
`Canceled Claim 1
`
`We claim:
`1— am one or said semiconductor memories being 00'1an “5
`PMIBB
`an error comction chip:
`tin—mg a contact strip
`for insertion into another electronic unit; and
`
`
`
`each one 01 said semiconductor memories being encap-
`sulated in a_ having a shorter
`dimension and a longer dimension;
`
`staid housing of each one of said semiconductor memories
`being identically designed and being individually con-
`nected to said printed circuit board;
`
`
`
`
`IIIIHI‘ HIIIIIII
`
`4mm
`
`5
`
`
`
`Canceled Claim 1
`
`Inst. Dec. at 14.
`
`Simpson discloses an electronic PCB with a
`contact strip, at least nine memories each in
`a rectangular housing. The memory
`housings are individually connected to the
`PCB. One memory (memory 16a) operates
`as an error correction chip (see Simpson,
`10:11‐19, 3:9‐16). The longer dimension of
`the error correction chip (16a) is
`perpendicular to the contact strip, and the
`longer dimensions of the other memories
`are parallel to the contact strip.
`
`Pet. at 16‐27
`
`6
`
`
`
`Canceled Claim 1
`
`Simpson clearly describes elements 16A and 16B as “parity memory devices,”
`which would be considered to be ECC chips by one of skill in the art.
`
`Simpson at 10:14-16; 12:10-11.
`
`Subramanian Decl. at ¶63.
`
`Parity error detection is consistent
`with the description of the ECC chip
`function provided in the ’414 Patent.
`
`Pet. at 23‐25
`
`7
`
`’414 Pat. at 7:1-9.
`
`
`
`Canceled Claim 1
`
`Simpson discloses and/or renders obvious the
`use of nine identical memory chips.
`
`Simpson at 12:10-11.
`Those of ordinary skill in the art would understand
`that the memory device 16A is identical to each of
`memory devices 12A‐12H.
`Dr. Subramanian Decl. at ¶48.
`
`The disclosure of the ’414 Patent supports
`a finding that it would have been obvious
`for a POSITA to use memories that had
`the same number of pins for memory
`devices 12A‐12H, 16A and 16B.
`
`Pet. at 18‐20; Inst. Dec. at 12‐13
`
`8
`
`’414 Pat. at 6:50-61.
`
`
`
`Canceled Claim 8
`
`PCB dimensions for memory modules had
`been standardized for some time by mid‐
`2001. Dr. Subramanian, therefore, testified
`that it would have been obvious to design
`Simpson’s PCB to meet the standardized
`width of 5.25 inches.
`Subramanian Decl. at ¶¶ 106-109.
`
`For example, the Intel Specification discloses a
`standardized memory module with a 133.37 mm (~5.25
`inch) wide PCB.
`
`Intel Spec. at 11.
`
`Inst. Dec. at 14.
`
`Pet. at 41‐43
`
`9
`
`
`
`Canceled Claim 8
`
`Karabatsos also discloses a memory module with a 5.25 inch wide printed circuit board.
`
`Opp. to MTA. at 16, 22.
`
`10
`
`
`
`Substitute Claim 9
`
`Patent Owner relies on the Board’s decision not to institute IPR proceedings against
`Claim 4 as justification that the 1‐1.2 inch height limitation is patentable.
`
`“[T]he substitute claim is the same as challenged Claim 8 in every respect,
`except that it simply adds the limitations of Claim 4 . . .”
`PO MTA, p. 1.
`“[T]he limitation that already appears in Claim 4 has already been found to not
`have been shown by Petitioner in this case to be disclosed or suggested in the
`prior art.”
`PO MTA, p. 4.
`
`PO MTA at 1‐5.
`
`11
`
`
`
`The Intel Specification
`
`Pet. at 35‐38.
`
`12
`
`
`
`Karabatsos
`
`Karabatsos explicitly discloses a memory module PCB height “between 1.125 and
`1.250 inches.
`
`Karabatsos also clearly indicates that such dimensions were motivated by
`market demand.
`
`Opp. to MTA at 15‐17.
`
`13
`
`
`
`Motivation to apply 1‐1.2” height to Simpson
`
`Similar to the width limitations of canceled Claim 8, a POSITA would understand
`how to apply a known and standardized PCB height to Simpson’s PCB.
`– Pet. at 36‐37.
`
`Dr. Bernstein (Patent Owner’s Expert Witness) Depo. at 170:7-8 Opp. to MTA at 7.
`
`Pet. at 36‐37.
`
`14
`
`
`
`Motivation to apply 1‐1.2” height to Simpson
`
`Adopting a known standard is a simple design choice.
`
`Pet. at 6-7.
`
`Opp. to MTA at 11 (quoting Simpson).
`
`Pet. at 36‐38; Opp. to MTA at 11‐14.
`
`15
`
`
`
`Motivation to apply 1‐1.2” height to Simpson
`
`Market forces at the time were in favor of shorter PCB dimensions.
`
`Market forces and design needs are indications of obviousness. KSR v.
`Teleflex, 550 U.S. 398, 421 (2007).
`
`Opp. to MTA at 13 (quoting Karabatsos).
`
`Pet. at 36‐38; Opp. to MTA at 11‐14.
`
`16
`
`
`
`Patent Owner Arguments – Chip Size
`
`POPR at 41-42.
`
`Yet, “it is well established that patent drawings do not define the
`precise proportions of the elements and may not be relied on to show
`particular sizes if the specification is completely silent on the issue.”
`Hockerson‐Halberstadt, Inc. v. Avia Group Int’l, 222 F.3d 951, 956, (Fed.
`Cir. 2000).
`Opp. to MTA at 5.
`
`Opp. to MTA at 4‐11.
`
`17
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`Kiehl’s Chips
`
`Opp. to MTA at 4‐9.
`
`18
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`Chips having dimensions disclosed by Kiehl could clearly fit on a 5.25” by 1.2” PCB.
`
`Dr. Subramanian 2nd Decl. at ¶¶19-22.
`
`Opp. to MTA at 4‐9.
`
`19
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`Intel TSOP Chips
`
`Opp. to MTA at 4‐9.
`
`20
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`The Intel TSOP chips could clearly fit on a 5.25” by 1.2” PCB.
`
`Dr. Subramanian 2nd Decl. at ¶¶23-24.
`
`Opp. to MTA at 4‐9.
`
`21
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`Micron Chips
`
`Dr. Subramanian 2nd Decl. at ¶25.
`
`Opp. to MTA at 4‐9.
`
`22
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`The Micron chips could clearly fit on a 5.25” by 1.2” PCB.
`
`Dr. Subramanian 2nd Decl. at ¶¶25-26.
`
`Opp. to MTA at 4‐9.
`
`23
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`Karabatsos Chips
`
`Karabatsos at ¶[0023].
`
`Dr. Subramanian 2nd Decl. at ¶27.
`
`Opp. to MTA at 4‐9.
`
`24
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`Chips having dimensions disclosed by Karabatsos could clearly fit on a 5.25” by
`1.2” PCB.
`
`Dr. Subramanian 2nd Decl. at ¶¶27-29.
`
`Opp. to MTA at 4‐9.
`
`25
`
`
`
`Existing Chip Sizes allow 1.2” PCB height
`
`The PCB area remaining after placing any of the Kiehl, Intel, Micron, or
`Karabatsos chips is sufficient to accommodate other memory module
`components. Dr. Subramanian 2nd Decl. at ¶29.
`
`‐
`
`‐
`
`Karabatsos’ own memory module layout leaves less area than any of
`the above examples and is sufficient space for these other components.
`
`Karabatsos’ own layout leaves only 0.234” inches in excess PCB height
`and only 0.655” in excess PCB width.
`
`‐ By comparison, the most limiting of the above examples (e.g., using
`Karabatsos’ chips) leaves 0.274” inches in excess PCB height and 1.223”
`in excess PCB width.
`
`Opp. to MTA at 4‐9.
`
`26
`
`
`
`Patent Owner Arguments – Sockets
`
`POPR at 41.
`But, as Dr. Subramanian testified during his deposition, “chip size” sockets
`existed in the prior art.
`
`For Example
`
`Dr. Subramanian Depo. at 167:4-11.
`
`Opp. to MTA at 10‐11.
`
`27
`
`Fujizaki at 5:23-24.
`
`
`
`Patent Owner Arguments – Sockets
`
`Dr. Subramanian 2nd Decl. at ¶30.
`
`Fujizaki at 2:28-32.
`
`Fujizaki at 5:23-24.
`
`Opp. to MTA at 10‐11.
`
`28
`
`
`
`Patent Owner Arguments – “Individually Connected”
`
`Inst. Dec. at 8.
`
`‐ Patent Owner’s “Stacked Chip” argument is irrelevant to socket connections.
`
`‐ Each of Simpson’s Chips are clearly connected individually to the PCB, whether
`soldered or connected via a socket and are none of the chips are stacked.
`
`Opp. to MTA at 10‐11.
`
`Like solder, a socket
`provides both a
`mechanical and an
`electrical connection
`to the PCB
`
`29
`
`
`
`Arbitrary height limitations are not entitled to independent
`patentable weight
`
`‐ Relative dimensions are typically deemed matters of choice and are not
`patentable distinctions. In re Rose, 220 F.2d 459, 463 (C.C.P.A. 1955).
`
`‐ Even optimized dimensions are not given patentable weight. “[W]here
`the general conditions of a claim are disclosed in the prior art, it is not
`inventive to discover the optimum workable ranges by routine
`experimentation.” In re Applied Materials, Inc., 692 F.3d 1289, 1295
`(Fed. Cir. 2012).
`
`‐ “In the case where the claimed ranges ‘overlap or lie inside ranges
`disclosed by the prior art’ [e.g., the Intel Spec. and Karabatsos] a prima
`facie case of obviousness exists.” MPEP 2144.05(I) (citing In re
`Wertheim, 541 F.2d 257 (C.C.P.A. 1976).
`
`Opp. to MTA at 23‐25.
`
`30
`
`
`
`Substitute Claim 9 is obvious in view of Bechtolsheim,
`Tokunaga, and Karabatsos
`
`Bechtolsheim discloses an electronic PCB with a contact strip, at least nine memories
`each in a rectangular housing. The memory housings are individually connected to the
`PCB. The longer dimensions of the memories are parallel to the contact strip.
`
`Opp. to MTA at 17‐23.
`
`31
`
`
`
`Substitute Claim 9 is obvious in view of Bechtolsheim,
`Tokunaga, and Karabatsos
`
`Bechtolsheim’s design anticipates the use of error correction.
`
`Bechtolsheim at 3:64-67.
`Tokunaga demonstrates that it was well‐known to configure a memory chip to provide
`ECC functions.
`
`Tokunaga at 9:11-16.
`A POSITA would be motivated to look to Tokunaga to configure one of the memory
`chips to perform error correction. Moreover combinations of familiar elements are
`obvious when they do no more than yield predictable results. KSR v. Teleflex, 550 U.S.
`396, 401 (2007).
`
`Opp. to MTA at 17‐23.
`
`32
`
`
`
`Substitute Claim 9 is obvious in view of Bechtolsheim,
`Tokunaga, and Karabatsos
`
`‐ Bechtolsheim demonstrates that it was known to place a chip vertically on a PCB
`among other horizontally oriented chips.
`‐ There is no indication in the ’414 Patent that orienting the ECC chip vertically rather
`than another chip is anything other than design choice.
`Such arrangements are per se obvious. “When a patent ‘simply arranges old
`elements with each performing the same function it had been known to perform’
`and yields no more than one would expect from such an arrangement, the
`combination is obvious.” KSR 550 U.S. at 417.
`
`‐
`
`Opp. to MTA at 17‐23.
`
`33
`
`
`
`Substitute Claim 9 is obvious in view of Bechtolsheim,
`Tokunaga, and Karabatsos
`
`‐
`
`It would have been possible for a POSITA to implement Bechtolsheim’s arrangement
`on a 5.25” by 1.2” PCB (as disclosed by Karabatsos) using memory chips similar to
`those disclosed by Kiehl.
`
`‐ Arranged as indicated below, the memory chips disclosed by Kiehl would result in a
`total height of 0.945 inches leaving 0.255 inches remaining, and a total width of
`4.095 inches leaving 1.155 inches remaining.
`
`‐ A POSITA would be motivated to make such modification in order to address the
`market demands for more compact memory modules discussed in Karabatsos.
`
`Opp. to MTA at 17‐23.
`
`34
`
`
`
`Kiehl provides evidence of chip sizes that were
`contemporaneous with the ’414 patent
`
`‐ Both Kiehl and the ’414 patent were filed in Germany within two months of
`each other.
`
`‐ Kiehl's disclosure is representative of memory chips that would have existed
`at the time of the ’414 patent.
`
`Sur‐reply at 7‐8.
`
`35
`
`
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