IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Attorney Docket No.: 37307-0007IP1
`
`In re Patent of: Benisek et al.
`US Patent No.: 6,850,414
`Issue Date:
`February 1, 2005
`Appl. Serial No.: 10/187,763
`§ 371 (c)(1) Date: July 2, 2002
`Title:
`ELECTRONIC PRINTED CIRCUIT BOARD HAVING A
`PLURALITY OF IDENTICALLY DESIGNED, HOUSING-
`ENCAPSULATED SEMICONDUCTOR MEMORIES
`
`Attorney Docket No.: 37307-0007IP1
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`DECLARATION OF VIVEK SUBRAMANIAN
`
`
`
`I, Vivek Subramanian, declare as follows:
`
`I.
`1.
`
`Introduction.
`I am making this declaration at the request of the Real Party in Interest
`
`(Kingston Technology Company, Inc.) in the matter of Inter Partes Review of U.S.
`
`Patent No. 6,850,414 (the “’414 patent”).
`
`2.
`
`I am being compensated for my work. My compensation does not depend on
`
`the outcome of this proceeding.
`
`3.
`
`I have been asked to consider whether certain references disclose or render
`
`obvious the claims of the ’414 Patent, either alone or in combination with each
`
`other.
`
`
`
`1
`
`KINGSTON 1022
`Kingston v. Polaris
`IPR2016-01622
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`In re Patent of: Benisek et al.
`US Patent No.: 6,850,414
`Issue Date:
`February 1, 2005
`Appl. Serial No.: 10/187,763
`§ 371 (c)(1) Date: July 2, 2002
`Title:
`ELECTRONIC PRINTED CIRCUIT BOARD HAVING A
`PLURALITY OF IDENTICALLY DESIGNED, HOUSING-
`ENCAPSULATED SEMICONDUCTOR MEMORIES
`
`Attorney Docket No.: 37307-0007IP1
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`DECLARATION OF VIVEK SUBRAMANIAN
`
`
`
`I, Vivek Subramanian, declare as follows:
`
`I.
`1.
`
`Introduction.
`I am making this declaration at the request of the Real Party in Interest
`
`(Kingston Technology Company, Inc.) in the matter of Inter Partes Review of U.S.
`
`Patent No. 6,850,414 (the “’414 patent”).
`
`2.
`
`I am being compensated for my work. My compensation does not depend on
`
`the outcome of this proceeding.
`
`3.
`
`I have been asked to consider whether certain references disclose or render
`
`obvious the claims of the ’414 Patent, either alone or in combination with each
`
`other.
`
`
`
`1
`
`KINGSTON 1022
`Kingston v. Polaris
`IPR2016-01622
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`4.
`
`I have been advised that a patent claim may be invalid as obvious if the
`
`differences between the subject matter patented and the prior art are such that the
`
`subject matter as a whole would have been obvious at the time of the invention to a
`
`person having ordinary skill in the art. I have also been advised that several factual
`
`inquiries underlie a determination of obviousness. These inquiries include the
`
`scope and content of the prior art, the level of ordinary skill in the field of the
`
`invention, the differences between the claimed invention and the prior art, and any
`
`objective evidence of non-obviousness.
`
`5.
`
`I have been advised that objective evidence of non-obviousness directly
`
`attributable to the claimed invention, known as “secondary considerations of non-
`
`obviousness,” may include commercial success, satisfaction of a long-felt but
`
`unsolved need, failure of others, copying, skepticism or disbelief before the
`
`invention, and unexpected results. I am not aware of any such objective evidence
`
`of non-obviousness that is directly attributable to the subject matter claimed in the
`
`’414 patent at this time.
`
`6.
`
`In addition, I have been advised that the law requires a “common sense”
`
`approach of examining whether the claimed invention is obvious to a person
`
`skilled in the art. For example, I have been advised that combining familiar
`
`elements according to known methods is likely to be obvious when it does no more
`
`than yield predictable results. I have further been advised that this is especially true
`
`
`
`2
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`in instances where there are a limited numbers of possible solutions to technical
`
`problems or challenges.
`
`7.
`
`I have been informed that all claims of the ’414 Patent are subject to this
`
`inter partes review.
`
`II. Materials Reviewed
`8.
`In forming the opinions that I express below, I considered my own
`
`knowledge of the art plus at least the following references:
`
`a. The ’414 Patent
`
`b. UK Patent Application GB 2 289 573 A (“Simpson”)
`
`c. U.S. Patent Application Publication No. 2002/0006032 A1
`
`(“Karabatsos”)
`
`d. U.S. Patent No. 5,973,951 (“Bechtolsheim”)
`
`e. U.S. Patent No. 6,038,132 (“Tokunaga”)
`
`f. PC SDRAM Unbuffered DIMM Specification, Version 1.0
`
`(“Intel Specification”)
`
`g. English Translation of German Publication No.
`
`DE 101 42 361 A1 (“Kiehl”)
`
`h. Intel Small Outline Package Guide
`
`i. Micron 64Mb: x32 SDRAM Features
`
`j. U.S. Patent No. 4,954,088 (“Fujizaki”)
`
`
`
`3
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`k. The File History of U.S. Patent No. 6,850,414
`
`III. Qualifications
`9.
`I summarize my relevant knowledge and experience below. My Curriculum
`
`Vitae contains additional information and is attached as Exhibit 1010.
`
`10. I received a B.S. in electrical engineering from Louisiana State University in
`
`1994, an M.S. in electrical engineering from Stanford University in 1996, and a
`
`Ph.D. in electrical engineering from Stanford University in 1998.
`
`11. I co-founded Matrix Semiconductor, Inc. in 1998 to develop high density
`
`memory technology.
`
`12. I have been teaching in the Electrical Engineering and Computer Sciences
`
`Department at the University of California, Berkeley since 2000. I was an
`
`Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to 2011,
`
`and a Professor from 2011 to the present.
`
`13. I have been an adjunct professor at the Sunchon National University in
`
`Sunchon, Korea since 2009, leading research in printed electronics.
`
`14. I have been an independent consultant in the semiconductor industry since
`
`2000, focusing on memory technology, flexible electronics, and RFID technology.
`
`15. I have published more than 200 technical papers in journals and at
`
`conferences.
`
`
`
`4
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`16. I am a named inventor on over 40 U.S. Patents, many of which are in the
`
`field of memory design.
`
`IV. Simpson Memory Module Layout is not limited to use with memory
`
`chips of a particular physical size.
`
`17. Simpson’s teachings are clearly not limited to a memory module that
`
`contains only a particular size or type of memory chip. For instance, Simpson
`
`states that while, “[t]he first example is based on a standard 72 terminal DRAM
`
`memory module but . . . this technique can equally be applied to . . . 30, 144 and
`
`168 terminal modules, and also to other types of memory.” Simpson at 13:3-6.
`
`From this, one of skill in the art would understand that Simpson’s layout of
`
`memory chips is not limited to chips with a particular physical size, memory
`
`capacity, or number of terminals. Instead, Simpson’s layout is more broadly
`
`applicable, and may be implemented using any memory chips available at the time
`
`or that might be developed later. In fact, Simpson even invites artisans to modify
`
`of its example embodiment. Id. at 14:10-12 (“The quantity, position and type [of
`
`memory chips and sockets] are dependent upon the design preferences of the
`
`module designer.”)
`
`18.
`
`In addition, Simpson does not even mention physical dimensions of either its
`
`memory chips or its memory module. Consequently, it would be obvious to one of
`
`skill in the art to look to a standards document such as the Intel Specification to
`
`
`
`5
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`provide standardized dimensions for a memory module. In that regard, the Intel
`
`Specification complements Simpson’s disclosure by providing a known design
`
`standard for the height and width of a 168 terminal memory module. Intel
`
`Specification at 7.
`
`V.
`
` It would have been physically possible for one of skill in the art to
`
`implement Simpson’s memory layout on a 5.25” by 1.2” memory
`
`module.
`
`19. Because Simpson does not discuss particular memory chip makes and
`
`models, one of skill in the art must look to other sources if he or she wanted to
`
`build a memory module according to Simpson’s design. A few exemplary
`
`references that disclose physical dimensions of memory chips available in 1999 or
`
`earlier include, in no particular order, the “Intel Small Outline Package Guide,” the
`
`Micron 64Mb: x32 SDRAM Features specification sheet, U.S. Patent Application
`
`Publication No. 2002/0006032 to Karabatsos, and German Patent Publication No.
`
`DE 101 24 361 A1 to Kiehl.
`
`20. The Kiehl reference clearly demonstrates that it was possible to fit two rows
`
`of memory chips on a 5.25” x 1.2” PCB. FIG. 1 of Kiehl (reproduced below)
`
`illustrates two rows of memory chips, with a top row of chips oriented vertically
`
`and the second row of chips oriented horizontally. Kiehl’s chip orientation is even
`
`less height efficient than Simpson’s because of the orientation of the chips in the
`
`
`
`6
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`top row. Yet, as Kiehl notes, his the memory module has a “width of 5.25 in
`
`(13.33 cm)” and a “height of less than 1.2 in (3.048 cm), or preferably less than
`
`1.125 in (2.85 cm).” Kiehl at [0002], [0024]. Thus, Kiehl demonstrates that
`
`memory chips were available that would permit the implementation of Simpson’s
`
`layout on a PCB with a height of between 1.125 and 1.2 inches. It is my opinion
`
`that Kiehl’s memory chips would fit within the same height if reoriented according
`
`to Simpson’s chip layout.
`
`
`
`
`
`21.
`
`It is fairly straightforward to determine the total space on a PCB that Kiehl’s
`
`memory chips would occupy if arranged according to Simpson’s layout. The total
`
`height of a PCB that would be occupied by memory chips using Simpson’s layout
`
`is equal to two times the individual width of a memory chip (e.g., 2*Wchip = Htotal).
`
`Similarly, the total length of a PCB that would be occupied by memory chips using
`
`Simpson’s layout is equal to four times the length of a memory chip plus the width
`
`of one memory chip (e.g., 2*Lchip + Wchip = Ltotal). Kiehl states that the memory
`
`
`
`7
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`chips shown in FIG. 1 have a “width b of about 8mm” (0.315 inches) and a “length
`
`l of about 14 to 16mm” (0.557 – 0.630 inches). Kiehl at [0024]. Consequently,
`
`even using Kiehl’s maximum memory chip length, the total distance length-wise
`
`for placing Kiehl’s memory chips would be 2.835 inches (4*0.63+0.315), and the
`
`total distance height-wise would be 0.63 inches (2*0.315). Thus, assuming PCB
`
`dimensions of 5.25 inches by 1.2 inches, one could implement Simpson’s memory
`
`chip layout using chips with dimensions disclosed by Kiehl and have 2.415 inches
`
`in excess length and 0.570 inches in excess height available for spacing between
`
`chips, memory module pins, memory sockets, and other memory module
`
`components (e.g., capacitors and resistors).
`
`22. These calculations are represented visually in the figure below, which is
`
`drawn to scale. The figure is not intended to represent an actual memory layout,
`
`but merely the relative area occupied by memory chips compared to the total area
`
`of a memory module PCB. The boxes labeled “Kiehl” represent memory chips
`
`with the dimensions disclosed by Kiehl. The larger rectangle represents a 5.25” by
`
`1.2” PCB. Further, the blue region represents the total area of the PCB that would
`
`be occupied by memory chips according to Simpson’s layout and the yellow region
`
`represents the remaining area of the PCB available for other components and
`
`spacing between chips. It is my opinion that the area represented by the yellow
`
`
`
`8
`
`
`
`region is sufficient space for the remaining components of a memory module (see
`
`Attorney Docket No.: 37307-0007IP1
`
`0.630"
`
`0.570"
`
`my additional discussion below).
`
`5.25"
`
`Kiehl
`Kiehl
`
`Kiehl
`Kiehl
`
`Kiehl K
`Kiehl
`
`iehl
`
`0.630"
`
`Kiehl
`Kiehl
`
`0.315"
`
`1.20"
`
`
`
`23. As another example, the Intel TSOP memory chips shown on page 3-1 of the
`
`“Intel Small Outline Package Guide” would fit on a 5.25” by 1.2” PCB if arranged
`
`according to Simpson’s layout. The Intel memory chips have a height (“Package
`
`Body Width E”) of 0.315 inches and a length (“Terminal Dimension D”) of 0.787
`
`inches. See Intel Small Outline Package Guide at 3-1. It should be noted that the
`
`length of the Intel chips is greater than twice the width. Therefore, the single
`
`vertically oriented Intel chip will occupy more of the PCB height than the stacked
`
`horizontal chips, and the total PCB height required to implement Simpson’s chip
`
`layout is simply the length of the Intel memory chips or 0.787 inches.
`
`Consequently, the total distance height-wise for placing the Intel memory chips
`
`would be 0.787 inches and the calculated total distance length-wise for placing the
`
`Intel memory chips would be 3.463 inches (4*0.787+0.315). Thus, assuming PCB
`
`dimensions of 5.25 inches by 1.2 inches, one could implement Simpson’s memory
`
`
`
`9
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`chip layout using the Intel chips and have 1.787 inches in excess length and 0.413
`
`inches in excess height available for spacing between chips, memory module pins,
`
`memory sockets, and other memory module components (e.g., capacitors and
`
`resistors).
`
`24. These calculations for the Intel chips are represented visually in the figure
`
`below, which is drawn to scale. As with the figure above, the figure below is not
`
`intended to represent an actual memory layout, but merely the relative area that
`
`would be occupied by the Intel memory chips compared to the total area of a
`
`memory module PCB. The boxes labeled “Intel” represent the dimensions of the
`
`Intel memory chips. The larger rectangle represents a 5.25” by 1.2” PCB. Further,
`
`the blue region represents the total area of the PCB that would be occupied by
`
`memory chips according to Simpson’s layout and the yellow region represents the
`
`remaining area of the PCB available for other components and spacing between
`
`chips. It is my opinion that the area represented by the yellow region is sufficient
`
`space for the remaining components of a memory module (see my additional
`
`discussion below).
`
`
`
`10
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`
`
`5.25"
`
`Intel
`Intel
`
`Intel
`Intel
`
`0.630"
`
`0.570"
`
`Intel
`
`0.413"
`
`0.315"
`
`1.20"
`
`Intel
`Intel
`
`Intel
`Intel
`
`25. As another example, the Micron memory chips shown on page 12 of the
`
`Micron 64Mb: x32 SDRAM Features specification sheet would fit on a 5.25” by
`
`1.2” PCB if arranged according to Simpson’s layout. The Micron memory chips
`
`have a height of 0.463 inches and a length of 0.875 inches. See Micron 64Mb: x32
`
`SDRAM Features specification sheet at 12. Using the calculations discussed
`
`above, the total distance length-wise for placing the Micron memory chips would
`
`be 3.963 inches (4*0.875+0.463), and the total distance height-wise would be
`
`0.926 inches (2*0.463). Thus, assuming PCB dimensions of 5.25 inches by 1.2
`
`inches, one could implement Simpson’s memory chip layout using the Micron
`
`chips and have 1.287 inches in excess length and 0.274 inches in excess height
`
`available for spacing between chips, memory module pins, memory sockets, and
`
`other memory module components (e.g., capacitors and resistors).
`
`26. These calculations for the Micron chips are represented visually in the figure
`
`below, which is drawn to scale. As with the figures above, the figure below is not
`
`intended to represent an actual memory layout, but merely the relative area that
`
`
`
`11
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`would be occupied by the Micron memory chips compared to the total area of a
`
`memory module PCB. The boxes labeled “Micron” represent the dimensions of
`
`the Micron memory chips. The larger rectangle represents a 5.25” by 1.2” PCB.
`
`Further, the blue region represents the total area of the PCB that would be occupied
`
`by memory chips according to Simpson’s layout and the yellow region represents
`
`the remaining area of the PCB available for other components and spacing between
`
`chips. It is my opinion that the area represented by the yellow region is sufficient
`
`space for the remaining components of a memory module (see my additional
`
`0.926"
`
`0.274"
`
`1.287"
`
`
`
`discussion below).
`
`5.25"
`
`0..463"
`
`Micron
`
`Micron M
`
`Micron
`
`Micron
`
`Micron
`
`Micron
`
`icron
`
`1.20"
`
`Micron
`
`Micron
`
`27. As a fourth example, the memory chips disclosed by Karabatsos would also
`
`fit on a 5.25” by 1.2” PCB if arranged according to Simpson’s layout. Karabatsos
`
`discloses SDRAM chips having a height of 22.62 mm (0.891 inches) and width of
`
`11.76 mm (0.463 inches). See Karabatsos at Fig. 6, [0023]. Using the calculations
`
`discussed above, the total distance length-wise for placing the memory chips
`
`disclosed by Karabatsos would be 4.027 inches (4*0.891+0.463), and the total
`
`
`
`12
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`distance height-wise would be 0.926 inches (2*0.463). Thus, assuming PCB
`
`dimensions of 5.25 inches by 1.2 inches, one could implement Simpson’s memory
`
`chip layout using the chips disclosed by Karabatsos and have 1.223 inches in
`
`excess length and 0.274 inches in excess height available for spacing between
`
`chips, memory module pins, memory sockets, and other memory module
`
`components (e.g., capacitors and resistors).
`
`28. These calculations for Karabatsos’s chips are represented visually in the
`
`figure below, which is drawn to scale. As with the figures above, the figure below
`
`is not intended to represent an actual memory layout, but merely the relative area
`
`that would be occupied by Karabatsos’s memory chips compared to the total area
`
`of a memory module PCB. The boxes labeled “Karabatsos” represent the
`
`dimensions of Karabatsos’s memory chips. The larger rectangle represents a 5.25”
`
`by 1.2” PCB. Further, the blue region represents the total area of the PCB that
`
`would be occupied by memory chips according to Simpson’s layout and the yellow
`
`region represents the remaining area of the PCB available for other components
`
`and spacing between chips. It is my opinion that the area represented by the yellow
`
`region is sufficient space for the remaining components of a memory module.
`
`29. For example, Karabatsos demonstrates that Karabatsos discloses a
`
`minimum PCB height of 1.125 inches, which according to Karabatsos’s layout
`
`would leave only 0.234 inches of distance in height remaining
`
`
`
`13
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`(1.125 - 0.891 = 0.234) and only 0.655 inches of distance in length remaining
`
`(5.25 – (8*0.463 + 0.891)), which is sufficient space according to Karabatsos. See
`
`Karabatsos at Fig. 6, [0023]. Consequently, the distances of 0.274 inches and
`
`greater in height and 1.223 inches and greater in length that would remain if any of
`
`the of the memory chips as discussed above were used to implement Simpson’s
`
`layout would also be sufficient for placing the remaining memory module
`
`components and allowing space between chips.
`
`5.25"
`
`Karabatsos Karabatsos
`
`Karabatsos Karabatsos
`
`0.926"
`
`0.274"
`
`arabatsos
`
`0..463"
`
`Karabatsos Karabatsos K
`
`1.20"
`
`Karabatsos Karabatsos
`
`4.027"
`
`1.223"
`
`
`
`30. Moreover, the dimensions calculated above would be sufficient space to
`
`accommodate Simpson’s sockets. For example, Fujizaki demonstrates that sockets
`
`that were no wider than the memory chip packages were available before the filing
`
`date of the ’414 Patent. Fujizaki’s sockets were specifically designed to permit
`
`“close mounting of the package[s] on [a] printed board.” Fujizaki at col. 2:31-32;
`
`see also Figs. 2, 5, 8, and col. 2:28-32, col. 2:47-31, col. 5:18-24. Accordingly, it is
`
`my opinion that neither chip size nor socket size would have prevented a person of
`
`
`
`14
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`ordinary skill who implementing Simpson’s memory chip layout on a standard
`
`sized memory module of 5.25” by 1.2” using known components.
`
`VI.
`
`It would have been physically possible for one of skill in the art to
`
`implement Simpson’s memory layout on a 5.25” by 1.2” memory
`
`module.
`
`
`
`
`
`31.
`
`It be physically possible for one of skill in the art to fit three rows of 6
`
`horizontal memory chips and one ECC memory chip oriented vertically (as in the
`
`layout shown in Becholsheim’s FIG. 2a reproduced below) using Kiehl’s memory
`
`chips. Stacked three high, as in Bechtolsheim, the total height of three horizontally
`
`oriented memory chips would be 0.945 inches (3*0.630) leaving 0.255 inches
`
`(1.2 – 0.945) of space available of a 1.2 inch high PCB for memory module pins
`
`and spacing between chips. Furthermore, arranged as shown below with six
`
`horizontal memory chips long plus one vertically oriented chip, the total length
`
`occupied by the memory chips would be 4.095 inches (6*0.63 + 0.315) leaving
`
`1.155 inches (5.25 – 4.095) of space available of a 5.25 inch long PCB for memory
`
`module pins and spacing between chips. As discussed above, this would be
`
`sufficient space for such components.
`
`
`
`15
`
`
`
`Attorney Docket No.: 37307-0007IP1
`
`VII. Conclusion
`32. I declare under penalty of perjury under the laws of the United States of
`
`
`
`America that the foregoing is true and correct.
`
`
`
`Executed this 17th day of August 2017.
`
`
`
`
`
`
`
`16
`
`
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