64Mb: x32 SDRAM
`Features
`
`SDR SDRAM
`MT48LC2M32B2 – 512K x 32 x 4 Banks
`
`Features
`• PC100-compliant
`• Fully synchronous; all signals registered on positive
`edge of system clock
`• Internal pipelined operation; column address can
`be changed every clock cycle
`• Internal banks for hiding row access/precharge
`• Programmable burst lengths: 1, 2, 4, 8, or full page
`• Auto precharge, includes concurrent auto precharge
`and auto refresh modes
`• Self refresh mode (not available on AT devices)
`• Auto refresh
`– 64ms, 4096-cycle refresh
`(commercial and industrial)
`– 16ms, 4096-cycle refresh
`(automotive)
`• LVTTL-compatible inputs and outputs
`• Single 3.3V ±0.3V power supply
`• Supports CAS latency (CL) of 1, 2, and 3
`
`Options
`• Configuration
`– 2 Meg x 32 (512K x 32 x 4 banks)
`• Plastic package – OCPL1
`– 86-pin TSOP II (400 mil) standard
`– 86-pin TSOP II (400 mil) Pb-free
`– 90-ball VFBGA (8mm x 13mm) Pb-
`free
`• Timing – cycle time
`– 5ns (200 MHz)
`– 5.5ns (183 MHz)
`– 6ns (167 MHz)
`– 6ns (167 MHz)
`– 7ns (143 MHz)
`• Operating temperature range
`– Commercial (0˚C to +70˚C)
`– Industrial (–40˚C to +85˚C)
`– Automotive (–40˚C to +105˚C)
`• Revision
`
`Marking
`
`2M32B2
`
`TG
`P
`B5
`
`
`-5
`-552
`-6A3
`-62
`-72
`
`None
`IT
`AT4
`:G/:J
`
`Notes:
`
`1. Off-center parting line.
`2. Available only on revision G.
`3. Available only on revision J.
`4. Contact Micron for availability.
`
`Table 1: Key Timing Parameters
`
`CL = CAS (READ) latency
`
`Speed Grade
`-5
`-55
`-6A
`-6
`-7
`
`Clock
`Frequency (MHz)
`200
`183
`167
`167
`143
`
`Target tRCD-tRP-CL
`3-3-3
`3-3-3
`3-3-3
`3-3-3
`3-3-3
`
`tRCD (ns)
`15
`16.5
`18
`18
`20
`
`tRP (ns)
`15
`16.5
`18
`18
`20
`
`CL (ns)
`15
`16.5
`18
`18
`21
`
`1
`PDF: 09005aef811ce1fe
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`Products and specifications discussed herein are subject to change by Micron without notice.
`
`KINGSTON 1012
`Kingston v. Polaris
`IPR2016-01622
`
`

`

`Table 2: Address Table
`
`Parameter
`Configuration
`Refresh count
`Row addressing
`Bank addressing
`Column addressing
`
`Table 3: 64Mb (x32) SDR Part Numbering
`
`Part Numbers
`MT48LC2M32B2TG
`MT48LC2M32B2P
`MT48LC2M32B2B51
`
`Architecture
`2 Meg x 32
`2 Meg x 32
`2 Meg x 32
`
`Note:
`
`1. FBGA Device Decoder: www.micron.com/decoder.
`
`64Mb: x32 SDRAM
`Features
`
`2 Meg x 32
`512K x 32 x 4 banks
`4K
`2K A[10:0]
`4 BA[1:0]
`256 A[7:0]
`
`Package
`86-pin TSOP II
`86-pin TSOP II
`90-ball VFBGA
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`2
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Features
`
`Contents
`General Description ......................................................................................................................................... 7
`Automotive Temperature .............................................................................................................................. 7
`Functional Block Diagrams ............................................................................................................................... 8
`Pin and Ball Assignments and Descriptions ....................................................................................................... 9
`Package Dimensions ....................................................................................................................................... 12
`Temperature and Thermal Impedance ............................................................................................................ 14
`Electrical Specifications .................................................................................................................................. 17
`Electrical Specifications – IDD Parameters ........................................................................................................ 19
`Electrical Specifications – AC Operating Conditions ......................................................................................... 21
`Functional Description ................................................................................................................................... 24
`Commands .................................................................................................................................................... 25
`COMMAND INHIBIT .................................................................................................................................. 25
`NO OPERATION (NOP) ............................................................................................................................... 26
`LOAD MODE REGISTER (LMR) ................................................................................................................... 26
`ACTIVE ...................................................................................................................................................... 26
`READ ......................................................................................................................................................... 27
`WRITE ....................................................................................................................................................... 28
`PRECHARGE .............................................................................................................................................. 29
`BURST TERMINATE ................................................................................................................................... 29
`REFRESH ................................................................................................................................................... 30
`AUTO REFRESH ..................................................................................................................................... 30
`SELF REFRESH ....................................................................................................................................... 30
`Truth Tables ................................................................................................................................................... 31
`Initialization .................................................................................................................................................. 36
`Mode Register ................................................................................................................................................ 38
`Burst Length .............................................................................................................................................. 40
`Burst Type .................................................................................................................................................. 40
`CAS Latency ............................................................................................................................................... 42
`Operating Mode ......................................................................................................................................... 42
`Write Burst Mode ....................................................................................................................................... 42
`Bank/Row Activation ...................................................................................................................................... 43
`READ Operation ............................................................................................................................................. 44
`WRITE Operation ........................................................................................................................................... 53
`Burst Read/Single Write .............................................................................................................................. 60
`PRECHARGE Operation .................................................................................................................................. 61
`Auto Precharge ........................................................................................................................................... 61
`AUTO REFRESH Operation ............................................................................................................................. 73
`SELF REFRESH Operation ............................................................................................................................... 75
`Power-Down .................................................................................................................................................. 77
`Clock Suspend ............................................................................................................................................... 78
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`3
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Features
`
`List of Figures
`Figure 1: 2 Meg x 32 Functional Block Diagram ................................................................................................. 8
`Figure 2: 86-Pin TSOP (Top View) .................................................................................................................... 9
`Figure 3: 90-Ball VFBGA (Top View) ............................................................................................................... 10
`Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12
`Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5 ........................................................................... 13
`Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View) ................................................. 15
`Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) ................................................ 16
`Figure 8: ACTIVE Command .......................................................................................................................... 26
`Figure 9: READ Command ............................................................................................................................. 27
`Figure 10: WRITE Command ......................................................................................................................... 28
`Figure 11: PRECHARGE Command ................................................................................................................ 29
`Figure 12: Initialize and Load Mode Register .................................................................................................. 37
`Figure 13: Mode Register Definition ............................................................................................................... 39
`Figure 14: CAS Latency .................................................................................................................................. 42
`Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 43
`Figure 16: Consecutive READ Bursts .............................................................................................................. 45
`Figure 17: Random READ Accesses ................................................................................................................ 46
`Figure 18: READ-to-WRITE ............................................................................................................................ 47
`Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 48
`Figure 20: READ-to-PRECHARGE .................................................................................................................. 48
`Figure 21: Terminating a READ Burst ............................................................................................................. 49
`Figure 22: Alternating Bank Read Accesses ..................................................................................................... 50
`Figure 23: READ Continuous Page Burst ......................................................................................................... 51
`Figure 24: READ – DQM Operation ................................................................................................................ 52
`Figure 25: WRITE Burst ................................................................................................................................. 53
`Figure 26: WRITE-to-WRITE .......................................................................................................................... 54
`Figure 27: Random WRITE Cycles .................................................................................................................. 55
`Figure 28: WRITE-to-READ ............................................................................................................................ 55
`Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 56
`Figure 30: Terminating a WRITE Burst ............................................................................................................ 57
`Figure 31: Alternating Bank Write Accesses ..................................................................................................... 58
`Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 59
`Figure 33: WRITE – DQM Operation ............................................................................................................... 60
`Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 62
`Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 63
`Figure 36: READ With Auto Precharge ............................................................................................................ 64
`Figure 37: READ Without Auto Precharge ....................................................................................................... 65
`Figure 38: Single READ With Auto Precharge .................................................................................................. 66
`Figure 39: Single READ Without Auto Precharge ............................................................................................. 67
`Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 68
`Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 68
`Figure 42: WRITE With Auto Precharge ........................................................................................................... 69
`Figure 43: WRITE Without Auto Precharge ..................................................................................................... 70
`Figure 44: Single WRITE With Auto Precharge ................................................................................................. 71
`Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 72
`Figure 46: Auto Refresh Mode ........................................................................................................................ 74
`Figure 47: Self Refresh Mode .......................................................................................................................... 76
`Figure 48: Power-Down Mode ........................................................................................................................ 77
`Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 78
`Figure 50: Clock Suspend During READ Burst ................................................................................................. 79
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`4
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`Figure 51: Clock Suspend Mode ..................................................................................................................... 80
`
`64Mb: x32 SDRAM
`Features
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`5
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Features
`
`List of Tables
`Table 1: Key Timing Parameters ....................................................................................................................... 1
`Table 2: Address Table ..................................................................................................................................... 2
`Table 3: 64Mb (x32) SDR Part Numbering ......................................................................................................... 2
`Table 4: Pin and Ball Descriptions .................................................................................................................. 11
`Table 5: Temperature Limits .......................................................................................................................... 14
`Table 6: Thermal Impedance Simulated Values ............................................................................................... 15
`Table 7: Absolute Maximum Ratings .............................................................................................................. 17
`Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 17
`Table 9: Capacitance ..................................................................................................................................... 18
`Table 10: IDD Specifications and Conditions – Revision G ................................................................................ 19
`Table 11: IDD Specifications and Conditions – Revision J ................................................................................. 20
`Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 21
`Table 13: AC Functional Characteristics ......................................................................................................... 22
`Table 14: Truth Table – Commands and DQM Operation ................................................................................. 25
`Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 31
`Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 33
`Table 17: Truth Table – CKE ........................................................................................................................... 35
`Table 18: Burst Definition Table ..................................................................................................................... 41
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`6
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`General Description
`
`General Description
`The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
`67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous in-
`terface (all signals are registered on the positive edge of the clock signal, CLK). Each of
`the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each
`of the 16,777,216-bit banks is organized as 2048 rows by 256 columns by 32 bits.
`
`Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
`location and continue for a programmed number of locations in a programmed se-
`quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
`lowed by a READ or WRITE command. The address bits registered coincident with the
`ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
`bank; A[10:0] select the row). The address bits registered coincident with the READ or
`WRITE command are used to select the starting column location for the burst access.
`
`The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
`locations, or the full page, with a burst terminate option. An auto precharge function
`may be enabled to provide a self-timed row precharge that is initiated at the end of the
`burst sequence.
`
`The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
`tion. This architecture is compatible with the 2n rule of prefetch architectures, but it al-
`so allows the column address to be changed on every clock cycle to achieve a high-
`speed, fully random access. Precharging one bank while accessing one of the other
`three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-
`dom-access operation.
`
`The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
`mode is provided, along with a power-saving, power-down mode. All inputs and out-
`puts are LVTTL-compatible.
`
`SDRAM devices offer substantial advances in DRAM operating performance, including
`the ability to synchronously burst data at a high data rate with automatic column-ad-
`dress generation, the ability to interleave between internal banks to hide precharge
`time, and the capability to randomly change column addresses on each clock cycle dur-
`ing a burst access.
`
`Automotive Temperature
`The automotive temperature (AT) option adheres to the following specifications:
`
`• 16ms refresh rate
`• Self refresh not supported
`• Ambient and case temperature cannot be less than –40°C or greater than +105°C
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`7
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Functional Block Diagrams
`
`Functional Block Diagrams
`
`Figure 1: 2 Meg x 32 Functional Block Diagram
`
`
`
`4
`
`4
`
`DQM[3:0]
`
`32
`
`32
`
`DATA
`OUTPUT
`REGISTER
`
`DATA
`INPUT
`REGISTER
`
`32
`
`DQ[31:0]
`
`BANK 3
`
`BANK 2
`BANK 1
`BANK 0
`
`BANK0
`MEMORY
`ARRAY
`(2048 x 256 x 32)
`
`SENSE AMPLIFIERS
`
`8192
`
`I/O GATING
`DQM MASK LOGIC
`READ DATA LATCH
`WRITE DRIVERS
`
`256
`(x32)
`
`COLUMN
`DECODER
`
`CONTROL
`LOGIC
`
`DECODE
`
`COMMAND
`
`CKE
`CLK
`
`CS#
`
`WE#
`
`CAS#
`RAS#
`
`MODE REGISTER
`
`REFRESH
`COUNTER
`
`11
`
`11
`
`11
`
`ROW-
`ADDRESS
`MUX
`
`11
`
`BANK 0
`ROW-
`ADDRESS
`LATCH
`&
`DECODER
`
`2048
`
`A[10:0],
`BA[1:0]
`
`13
`
`ADDRESS
`REGISTER
`
`2
`
`BANK
`CONTROL
`LOGIC
`
`COLUMN-
`ADDRESS
`COUNTER/
`LATCH
`
`8
`
`2
`
`8
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`8
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Pin and Ball Assignments and Descriptions
`
`Pin and Ball Assignments and Descriptions
`
`Figure 2: 86-Pin TSOP (Top View)
`
`
`
`86
`85
`84
`83
`82
`81
`80
`79
`78
`77
`76
`75
`74
`73
`72
`71
`70
`69
`68
`67
`66
`65
`64
`63
`62
`61
`60
`59
`58
`57
`56
`55
`54
`53
`52
`51
`50
`49
`48
`47
`46
`45
`44
`
`VSS
`DQ15
`VSSQ
`DQ14
`DQ13
`VDDQ
`DQ12
`DQ11
`VSSQ
`DQ10
`DQ9
`VDDQ
`DQ8
`NC
`VSS
`DQM1
`NU
`NC
`CLK
`CKE
`A9
`A8
`A7
`A6
`A5
`A4
`A3
`DQM3
`VSS
`NC
`DQ31
`VDDQ
`DQ30
`DQ29
`VSSQ
`DQ28
`DQ27
`VDDQ
`DQ26
`DQ25
`VSSQ
`DQ24
`VSS
`
`1234567891
`
`0
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`
`VDD
`DQ0
`VDDQ
`DQ1
`DQ2
`VSSQ
`DQ3
`DQ4
`VDDQ
`DQ5
`DQ6
`VSSQ
`DQ7
`NC
`VDD
`DQM0
`WE#
`CAS#
`RAS#
`CS#
`NC
`BA0
`BA1
`A10
`A0
`A1
`A2
`DQM2
`VDD
`NC
`DQ16
`VSSQ
`DQ17
`DQ18
`VDDQ
`DQ19
`DQ20
`VSSQ
`DQ21
`DQ22
`VDDQ
`DQ23
`VDD
`
`Note:
`
`1. Package may or may not be assembled with a location notch.
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`9
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Pin and Ball Assignments and Descriptions
`
`Figure 3: 90-Ball VFBGA (Top View)
`
`
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`DQ26
`
`DQ24
`
`VSS
`
`VDD
`
`DQ23
`
`DQ21
`
`DQ28
`
`VDDQ
`
`VSSQ
`
`VDDQ
`
`VSSQ
`
`DQ19
`
`VSSQ
`
`DQ27
`
`DQ25
`
`DQ22
`
`DQ20
`
`VDDQ
`
`VSSQ
`
`DQ29
`
`DQ30
`
`DQ17
`
`DQ18
`
`VDDQ
`
`VDDQ
`
`DQ31
`
`NC
`
`NC
`
`DQ16
`
`VSSQ
`
`VSS
`
`DQM3
`
`A3
`
`A2
`
`DQM2
`
`VDD
`
`A5
`
`A6
`
`A10
`
`A0
`
`A1
`
`A4
`
`A7
`
`A8
`
`NC
`
`NC
`
`BA1
`
`NC
`
`CLK
`
`CKE
`
`A9
`
`BA0
`
`CS#
`
`RAS#
`
`DQM1
`
`NU
`
`NC
`
`CAS#
`
`WE#
`
`DQM0
`
`VDDQ
`
`DQ8
`
`VSS
`
`VDD
`
`DQ7
`
`VSSQ
`
`VSSQ
`
`DQ10
`
`DQ9
`
`DQ6
`
`DQ5
`
`VDDQ
`
`VSSQ
`
`DQ12
`
`DQ14
`
`DQ1
`
`DQ3
`
`VDDQ
`
`DQ11
`
`VDDQ
`
`VSSQ
`
`VDDQ
`
`VSSQ
`
`DQ4
`
`DQ13
`
`DQ15
`
`VSS
`
`VDD
`
`DQ0
`
`DQ2
`
`A B C D E F G H J K L M N P R
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`10
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Pin and Ball Assignments and Descriptions
`
`Table 4: Pin and Ball Descriptions
`
`Symbol
`CLK
`
`CKE
`
`CS#
`
`CAS#, RAS#,
`WE#
`DQM[3:0]
`
`BA[1:0]
`
`A[10:0]
`
`DQ[31:0]
`VDDQ
`VSSQ
`VDD
`VSS
`NC
`NU
`
`Input
`
`Type Description
`Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
`edge of CLK. CLK also increments the internal burst counter and controls the output registers.
`Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
`clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
`power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-
`gress). CKE is synchronous except after the device enters power-down and self refresh modes,
`where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-
`cluding CLK, are disabled during power-down and self refresh modes, providing low standby
`power. CKE may be tied HIGH.
`Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-
`coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already
`in progress will continue, and DQM operation will retain its DQ mask capability while CS# is
`HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
`ered part of the command code.
`Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-
`tered.
`Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
`an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
`output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0
`corresponds to DQ[7:0]; DQM1 corresponds to DQ[15:8]; DQM2 corresponds to DQ[23:16]; and
`DQM3 corresponds to DQ[31:24]. DQM[3:0] are considered same state when referenced as
`DQM.
`Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE-
`CHARGE command is being applied.
`Input Address inputs: A[10:0] are sampled during the ACTIVE command (row address A[10:0]) and
`READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select
`one location out of the memory array in the respective bank. A10 is sampled during a PRE-
`CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec-
`ted by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE
`REGISTER command.
`Data input/output: Data bus.
`I/O
`Supply DQ power supply: DQ power to the die for improved noise immunity.
`Supply DQ ground: DQ ground to the die for improved noise immunity.
`Supply Power supply: 3.3V ±0.3V.
`Supply Ground.
`No connect: These pins/balls should be left unconnected.
`–
`–
`Not used.
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`11
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Package Dimensions
`
`Package Dimensions
`
`Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P
`
`
`
`22.22 ±0.08
`
`0.50
`TYP
`
`0.20
`
` +0.07
`-0.03
`
`See Detail A
`
`0.61
`
`2X 0.10
`
`2X 2.80
`
`11.76 ±0.20
`
`10.16 ±0.08
`
`2X R 0.75
`
`Pin #1 ID
`
`2X R 1.00
`
`0.15
`
` +0.03
`-0.02
`
`1.20 MAX
`
`0.10
`
`Plated lead finish:
`TG (90% Sn, 10% Pb) or P (100% Sn) 0.01 ±0.005 thick per side
`Plastic package material: Epoxy novolac
`Package width and length do not include
`mold protrusion. Allowable protrusion is
`0.25 per side.
`
`0.10
`
` +0.10
`-0.05
`
`0.50 ±0.10
`
`Detail A
`
`0.25
`
`Gage
`plane
`
`0.80
`TYP
`
`Notes:
`
`1. All dimensions are in millimeters.
`2. Package width and length do not include mold protrusion; allowable mold protrusion is
`0.25mm per side.
`3. "2X" means the notch is present in two locations (both ends of the device).
`4. Package may or may not be assembled with a location notch.
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`12
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Package Dimensions
`
`Solder ball material:
` 62% Sn, 36% Pb, 2% Ag or
` 96.5% Sn, 3%Ag, 0.5% Cu
`Substrate material:
` Plastic laminate
`Mold compound:
` Epoxy novolac
`
`Ball A1 ID
`
`Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5
`
`
`
`0.65 ±0.05
`
`Seating plane
`
`0.12 A
`
`A
`
`90X Ø0.45
`Dimensions apply
`to solder balls post
`reflow. The pre-reflow
`diameter is 0.42 on a
`0.40 SMD ball pad.
`
`Ball A9
`
`11.20 ±0.10
`
`5.60 ±0.05
`
`6.40
`
`0.80 TYP
`
`Ball A1 ID
`Ball A1
`
`0.80 TYP
`
`C L
`
`13.00 ±0.10
`
`6.50 ±0.05
`
`C L
`
`3.20 ±0.05
`
`4.00 ±0.05
`
`8.00 ±0.10
`
`1.00 MAX
`
`Notes:
`
`1. All dimensions are in millimeters.
`2. Package width and length do not include mold protrusion; allowable mold protrusion is
`0.25mm per side.
`3. Recommended pad size for PCB is 0.33mm ±0.025mm.
`
`PDF: 09005aef811ce1fe
`64mb_x32_sdram.pdf - Rev. V 09/14 EN
`
`13
`
`Micron Technology, Inc. reserves the right to change products or specifications without notice.
`© 1999 Micron Technology, Inc. All rights reserved.
`
`

`

`64Mb: x32 SDRAM
`Temperature and Thermal Impedance
`
`Temperature and Thermal Impedance
`It is imperative that the SDRAM device’s temperature specifications, shown in Temper-
`ature Limits below, be maintained to ensure the junction temperature is in the proper
`operating range to meet data sheet specifications. An important step in maintaining the
`proper junction temperature is using the device’s thermal impedances correctly. The
`thermal impedances are listed in Table 6 (page 15) for the applicable die revision and
`packages being made available. These thermal impedance values vary according to the
`density, package, and particular design used for each device.
`
`Incorrectly using thermal impedances can produce significant errors. Read Micron
`technical note TN-00-08, “Thermal Applications” prior to using the thermal impedan-
`ces listed in Table 6 (page 15). To ensure the compatibility of current and future de-
`signs, contact Micron Applications Engineering to confirm thermal impedance values.
`
`The SDRAM device’s safe junction temperature range can be maintained when the TC
`specification is not exceeded. In applications where the device’s ambient temperature
`is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-
`perature specifications.
`
`Table 5: Temperature Limits
`
`Parameter
`Operating case temperature
`
`Junction temperature
`
`Ambient temperature
`
`Peak reflow temperature
`
`Notes:
`
`Commercial
`Industrial
`Automotive
`Commercial
`Industrial
`Automotive
`Commercial
`Industrial
`Automotive
`
`Symbol
`TC
`
`TJ
`
`TA
`
`TPEAK
`
`Min
`0
`–40
`–40
`0
`–40
`–40
`0
`–40
`–40
`–
`
`Max
`80
`90
`105
`85
`95
`110
`70
`85
`105
`260
`
`Unit
`°C
`
`Notes
`1, 2, 3, 4
`
`°C
`
`°C
`
`°C
`
`3
`
`3, 5
`
`
`
`1. MAX operating case temperature TC is measured in the center of the package on the
`top side of the device, as shown in Figure 6 (page 15) and Figure 7 (page 16).
`2. Device functi