U.S. Patent
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`Sheet 25 M32
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`US 6,332,183 B1
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`U.S. Patent
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`Dec. 18,2001
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`Sheet 26 M32
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`U.S. Patent
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`Dec. 18,2001
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`Sheet 27 M32
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`Dec. 18,2001
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`Dec. 18,2001
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`Sheet 29 0132
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`US 6,332,183 B1
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`US. Patent
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`Dec. 18,2001
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`Sheet 30 of 32
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`U.S. Patent
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`Dec. 18,2001
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`Sheet 31 of 32
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`Us 6,332,183 B1
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`US. Patent
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`Dec. 18,2001
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`Sheet 32 of 32
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`US 6,332,183 B1
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`2
`reliable and nondefective memory module. Such an embodi-
`ment takes advantage of the manner in which defective cells
`are localized on each memory chip, and combines multiple
`memory chips to provide a memory bus that is of the desired
`width and granularity. In addition, it is possible with such an
`embodiment
`to provide a computer system in which the
`main memory is synchronized with the system clock, and is
`constructed, at least in part, from partially defective memory
`chips.
`invention as well as other
`The nature of the present
`embodiments of the present invention may be more clearly
`understood by reference to the following detailed descrip-
`tion of the invention. to the appended claims, and to the
`several drawings herein.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. I is a block diagram of a prior art corrlphter system
`using a wait state control device with DRAM memory chips.
`FIG. 2 is a block diagram of a computer system employ-
`ing SDRAM memory chips,
`FIG. 3 isa block diagram of a partially defective SDRAM
`component.
`FIG. 4 is it memory map showing the localized nature of
`defective memory cells in one emborlimertt til" the present
`invention.
`FIG. 4A is a memory map showing defective memory
`cells corresponding to a defect that dilfers from that of FIG.
`4.
`
`FIG. 5 is an embodiment of the present invention using
`six partially defective SDRAM components to make a 64-bit
`memory module.
`FIGS, 6 and 7 are embodiments of the present invention
`using sixteen defective SDRAM components where four hits
`in each of the eight bit memory cells are defective.
`DETAILED DESCRIPTION
`FIG. 1 is a block diagram of a prior art computer system
`comprising a microprocessor 16, a memory controller 14,
`and main memory 12. In the system shown, main memory
`12 is made up ofdynamic random access memory (DRAM).
`Also shown in FIG. 1 is a wait state control device 18 and
`a system clock 20. As is well known in the art, due to
`ditferences in speed between the processor 16 and the
`DRAM 12, it is often necessary to insert “wait states" when
`the processor carries out a memory operation involving the
`DRAM 12. Typically,
`the DRAM 12 is slower than the
`processor 16, so one or more additional states are added to
`the microprocessor’s memory access cycle to cnsure that the
`memory 12 is given a sullicient amount of time to parry out
`the memory (read/write) operation.
`In addition, the clock 20 in the system of FIG. 1 is not a
`direct input to the DRAM 1.2. Instead, as is well known in
`the art, control signals are derived from the clock, and the
`DRAM I2 is operated through the use of these control
`signals. The signals presented to the DRAM device 12
`change relatively slowly compared to the rate at which the
`clock changes.
`FIG. 2 shows a block diagram of a computer system in
`one embodiment of the present invention, where the com»
`puter system comprises a clock 20, a processor 16, a
`memory controller 22, and main memory 24. Often,
`the
`clock 20 operates at 66 MHZ or 100 MHz, but it may operate
`at any speed. Unlike FIG. 1, the main memory in FIG. 2 is
`made up of one or more SDRAM chips, and the SDRAM
`memory is synchroni'/.ed with the clock 20, which means
`
`1
`METHOD FOR RECOVERY OF USEFUL
`AREAS OF PARTIAI.I.Y DEFECTIVE
`SYNCHRONOUS MEMORY COMPONENTS
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`This application includes subject matter related to appli-
`catiorl Ser. No. t)9f035,629, llled concurrently herewith on
`Mar. 5, 1998.
`
`Fll-‘.l.I) 0|" TIIE lNVl_-‘.N'l’l()N
`
`The present invention relates generally to the use partially
`defective synchronous memory chips. More particularly. the
`present invention relates to the configuration of defective
`SDRAM components to create a nondelective memory
`module or array.
`BACKGROUND AND SUMMARY 01'‘ Till.‘
`|)lSCI.()SURIi
`
`As is well known in the art, during the production of
`monolithic memory devices from silicon wafers, some of the
`memory storage cells can become defective and unreliable.
`The defective cells can be the result of a number of causes,
`such as impurities introduced in the process of manufactur-
`ing the monolithic memory device t'rom the silicon wafer, or
`ltJC:tllZC(.l imperfections in the silicon substrate itself.
`Often, while some memory cells are defective, many
`other cells on the same memory chip are not defective, and
`will work reliably and accurately. In addition, it is often the
`case that the detective cells are localivted and confined to
`particular outputs from the memory device. The remaining,
`nondetective outputs can be relied upon to provide a con-
`sistent and accurate representation of the information in the
`storage cell,
`Techniques have been developed for salvaging the non-
`rtetective portions ot‘ defective asynchronous memory tech-
`nologies (e.g., l)l~’./\M). Asynchronous memory technolo-
`gies are relatively slow devices that operate in response to
`control signals generated by a memory controller. rather
`than in response to the system clock. The control signals
`allow the asynchronous memory device to operate at a speed
`that is much slower than the system Clock, and that ensures
`reliable read and write memory operations.
`Synchronous memory devices such as SDRAM, on the
`other hand, are much faster devices that operate on the
`system clock. SDRAM is an improvement over prior
`memory technologies principally because SDRAM is
`capable of synchronizing itself with the microprocessor’s
`clock. This synchronization can eliminate the time delays
`and wait states often necessary with prior memory technolo-
`gies (c.g., DRAM), and it also allows for fast consecutive
`read and write capability.
`However, no attempts have been made to salvage non-
`dcfective portions of synchronous memory. Some people
`skilled in the art may believe that the use of techniques for
`salvaging defective memory devices would not work with
`higher—speect synchronous memory devices such as S[)R/\M
`because they operate at much higher speeds than previous
`memory devices, such as asynchronous DRAM. For
`SDRAM, it may he believed that the rate at which the clock
`input cycles and the load on the device driving the inputs
`(e..g.,
`the clock and the address) to the SDRAM devices
`would make reliable input transitions unattainable.
`The present invention addresses the problem of salvaging
`partially defective synchronous memory devices.
`In one
`embodiment of the present
`invention, multiple partially
`defective SDRAM con11Jonents are configured to provide a
`
`49
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`3
`it operates synchronously with the clock 20. This
`that
`synchronization can eliminate some or all of the wait states
`normally necessary with DRAM devices, and it also allows
`for fast consecutive read and write capability. Unlike FIG. 1,
`in FIG. 2 the clock 20 is provided as an input to the memory
`24. Thus, in FIG. 2, at least some of the inputs tn the memory
`24 may change at a rate approaching or equal to the rate of
`the clock 20.
`FIG. 3 is a block diagram of a partially defective SDRAM
`component 26 having twelve address inputs At] to All, and
`eightdataoutputs D0!) to l)Q7.’I'he component 26 is a 1024
`Kx83><2 SDRAM. The “8" in this description represents the
`eight output lines, meaning the data width is 8 bits wide (the
`granularity may also be eight bits). The “'l024K” is the
`addressable space in each bank of memory within the
`SDRAM, and the ‘‘2’‘
`indicates that
`there are two such
`1024K banks of memory within this component. Generally,
`components such as that described in FIG. 3 are mounted on
`SlMMs (Single In-line Memory Modules) or l)lMMs (Dual
`Inline Memory Modules), but any other appropriate pack-
`aging technology could be used to practice one or more of
`the inventions described herein.
`In operation. the SDRAM component 26 is addressed by
`using a multiplexed row and column address, as is well
`known in the art. The twelve address inputs trn the memory
`component are first presented with an eleven bit row address
`on A0 to A10. After the row address has been presented to
`the SDRAM 26, an nine bit column address is presented to
`the SDRAM 26 on address inputs A0 to A8. Thus, the full
`address is twenty hits wide, thereby making a l(J24K address
`space based on the row and column addresses. The SDRAM
`26 has two of these 1024K banks of memory addressable
`with the row and column addresses, The particular 1024K
`hank within the SDRAM component
`is selected by an
`additional
`row address bit, which is presented to the
`SDRAM with the row address on address input All.
`The SDRAM component shown in FIG, 3 is partially
`defective in the sense that some of the DO outputs do not
`consistently present valid or accurate data. In the particular
`SDRAM shown in FIG. 3, data outputs D02 to DOS are
`defective, whereas data outputs D00, D01, D06, and D0?
`are not defective. Thus, these latter DO outputs can be relied
`upon for accurate and consistent data, whereas the data
`outputs D02 to DOS cannot.
`FIG. 4 is a rnernory map of the SDRAM Component of
`FIG. 3, showing the portions of memory that are defective.
`As can be seen from FIG. 4,
`in the particular SDRAM
`component of FIG. 3,
`the defects are such that every
`addressable eight bit memory location has both reliable and
`unreliable (or unused) DQ outputs, and they are consistently
`arranged within each addressable octet.
`This result may follow from the nature of the defect,
`where certain DQ outputs always present valid data, whereas
`other DQ outputs may not be reliable, and may occasionally
`present bad data. Defects in the silicon or impurities intro-
`duced in the manufacturing process will often result
`in
`defects like those illustrated in FIG. 4,
`FIG. Sis a schematic diagram ofa memory module in one
`embodiment of the present invention where multiple par—
`tially defective SDRAM components are combined to create
`a nondefeclive 5l2Kx64x2 memory module. The edge
`connector 52 is connected to each of the partially defective
`SI2k><1{t><2 SDRAM components 54 to 59. Each of the
`SDRAM components are defective in a manner similar to
`that shown in FIG. 4. The SDRAM Cornponents 54, 55, 57,
`and 58 each have four detective or unused [)0 outputs (i.e.,
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`4
`D00 to D03), and the remaining twelve DQ outputs are not
`defective. The SDRAM components 56 and 59 have eight
`unreliable or unused DQ outputs (DQO to DQ7), and eight
`reliable and nnndeliective DQ outputs. By using the twelve
`nnndetective DQ outputs from SDRAM components54, 55,
`57, and 58 and by using the eight nondefeetive DQ outputs
`from SDRAM components 56 and 59,
`a 5IlKx64:-<2
`memory module can be constructed from the six partially
`defective SDRAM components as shown in FIG. 5.
`In a manner similar to that described in connection with
`FIG. 3, the Wm components in FIG. 5 are addressed by
`first presenting an eleven bit row address followed by an
`eight bit column address. Thus,
`the memory address is
`nineteen bits wide. An additional bit is presented at address
`input All with the eleven bit row address to select one of the
`two 512K memory banks within each SDRAM component.
`l-71G. 6 is a schematic oi‘ another embodiment of the
`present invention, where sixteen partially defective ][l’_’4I(><
`8x2 SDRAM components 72 to 87 are used to create a
`lO2.4K><64x2 memory module. Each of the partially defec—
`live SDRAM components in FIG. 6 has four unreliable or
`unused outputs (DQO to D03) and four nondefective outputs
`(D04 [0 D07). Using the four nondefective outputs from
`each of the sixteen SDRAM components provides a 64 bit
`quad word data path.
`The SDRAM components of FIG. 6 are addresstd by first
`presenting an eleven bit row address followed by a nine bit
`column address. Thus, the memory address is twenty bits
`wide. An additional bit is presented at address input All
`with the eleven-bit row address to select one of the two
`1024K memory banks within each SDRAM component.
`It should be understood that the present invention does‘ rtot
`necessarily require any particular arrangement [or the defec-
`tive DQ outputs. For example, in FIG. 6, the defective DQ
`outputs need not be the same foreacb component 71-87, and
`the defective outputs may not be consecutive or symtnctric.
`As can be seen from FIG. 6, the components 72 and 80 make
`up the low order byte ot‘ data in the 64-bit quad word. It is
`possible that component 72 may have only three defective
`outputs, thereby allowing five bits in the low order byte to
`be taken from component 72, and only three bits from
`component 80. Any other combination would also be appro-
`priate. Similarly,
`the deiective outputs in component 80
`could come in any combination, and need not be DQO, D01,
`DQ2, DQ3. Rather,
`the defective outputs could be DQl,
`DQ4, D06, and DQ7, or any other combination.
`FIG. 7 is a schematic of another embodiment of the
`present invention, where sixteen partially defective lMx8>-<2
`SDRAM components 92 to 107 are used to create a
`lM><64><2 memory module. Each of the partially defective
`SDRAM components in FIG. 7 have four unreliable or
`unused outputs and four nttndefective outputs. This emboLli~
`ment dilfers from that in FIG. 6 in that the outputs DQO to
`DQ3 are nondefective, whereas outputs DQ4 to DQ7 are
`defective. The four nondefcctive outputs from each of the
`sixteen SDRAM components provides a 64 bit quad word
`data path.
`Although the SDRAM componentsin FIG. 7' are 1Mx8x2
`components having two banks of tMx8 bit memory,
`it is
`possible that they could be 2M><8 bit components having
`only a single bank of memory. In such an embodiment, the
`components are addressed by tlrst presenting a twelve hit
`row address to the addrem inputs A0 to All, followed by a
`nine bit column address, which is presented at address inputs
`A0 to A8. Thus, the full address is 21 bits wide, thereby
`providing a 2M address space, and the SDRAM cornpunents
`haw-.(nrare treated as having) only a single bank ofmemory.
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`It is also possible that the memory components have more
`than two banks of memory. In some more modern devices,
`two bank select lines (cg, EM] and BAI) are used to select
`one of four banks of memory in a particular component or
`module. (Often, but not necessarily, such select signals are
`presented to the component with the row address.) As one
`skilled in the art would recognize, the present invention is
`applicable to memory components of this nature, and is
`applicable generally to memory components having any
`number of banks of memory.
`Although the present
`invention has been shown and
`described with respect to preferred embodiments, various
`changes and modifications that are obvious to a person
`skilled in the art to which the invention pertains, even if not
`shown or specilically described herein. are deemed to lie
`within the spirit and scope of the invention and the following
`claims.
`What is claimed is:
`1. A method of accessing a memory module comprising
`the acts of:
`presenting a row address to the address inputs of each of
`a plurality of partially defective SDR/\.M components
`that have at least one unreliable data output. and that
`also have a plurality of valid data outputs, wherein the
`valid data outputs are data outputs that provide reliable
`and accurate data; and
`presenting a column address to the address inputs. of each
`SDRAM component;
`aggregating the valid data outputs of each of the SDRAM
`components to provide a data path; and
`communicating the data from the valid data outputs to a
`|Tll.C|'l'|p|’0L‘C5§U|'.
`2. The method of claim 1, wherein the act of presenting
`a row address includes the act of presenting a row address -
`to the address inputs of partially defective SDRAM
`components, where for each of these SDRAM components,
`the plurality of valid data outputs are the same for each
`addressable memory location within that component so that
`the same portion of each addressable memory location
`within any given SDRAM component consistently provides
`valid and accurate data.
`3. The method of claim 2, wherein the act of presenting
`a row address to the address inputs of each of a plurality of
`partially defective SDRAM components includes the act of
`presenting a row address to SDRAM components mounted
`on SIMMs.
`4. The method of claim 3, wherein the act of presenting
`a row address to the address inputs of each of a plurality of
`partially defective SDRAM components includes the act of
`presenting a new address to SDRAM components mounted
`on l)lMMS.
`5. A method of accessing memory cells in a memory
`module having a plurality of SDRAM components, each of
`the SDRAM components having a plurality of address .
`inputs, and wherein each of the SDRAM components further
`comprises a plurality of hanks of memory that are addres-
`sable by the address inputs, the rnethod comprising the acts
`of:
`
`6
`presenting a column address to the address inputs of each
`SDRAM component;
`selecting one of the plurality of banks within each
`SDRAM component by presenting at least one selec-
`tion bit at the address inputs when the row address is
`presented to the address inputs, wherein each of the
`SDRAM components is partially defective such that
`each SDRAM components has at least one unreliable
`data output, and also a plurality of valid data outputs
`that provide reliable and accurate data;
`aggregating the valid data outputs of each of the SDRAM
`components to provide a data path; and
`communicating the data from the valid data outputs from
`each of the SDRAM components to a microprocessor.
`6. The method of claim 5, wherein the act of presenting
`a row address includes the act of presenting a row address
`to the address inputs of partially defective SDRAM
`components, where for each of these SD]-‘LAM components,
`the plurality of valid data outputs are the same for each
`addressable memory location within that component so that
`the same portion of each addressable memory location
`within any given SDRAM component consistently provides
`valid and accurate data.
`1. The method of claim 6, wherein the act of presenting
`a row address to the address inputs of each of a plurality of
`partially defective SDRAM components includes the act of
`presenting a row address to SDRAM components mounted
`on $IMMs.
`S. The method of claim '1, wherein the act of presenting
`a row address to the address inputs of each of a plurality of
`partially defective SDRAM components includes the act of
`presenting a row address to SDRAM components mounted
`on I)lMMs.
`9. A method of enabling data access between a memory
`module having data outputs and a microprocessor compris-
`ing the acts of:
`determining which SDRAM data outputs of a group of
`SDRAM components are defective;
`assembling a set of SDRAM components from the group
`of SDRAM components. wherein at least one of the
`SDRAM components has defective SDRAM data
`outputs, such that each memory module data output is
`connected to an operative SDRAM data output; and
`applying a clock signal that is processed to synchronously‘
`apply operating signals t.o the memory module and the
`microprocessor
`to cfiect data access between the
`memory module and the microprocessor.
`10. ‘Die method of claim 9 firlher comprising sorting
`SDRAM components based on which of the data outputs of
`the respective SDRAM components are defective.
`11. The method of claim 10 further comprising providing
`sorted SDRAM corttponettts with predetennined numbers
`and arrangements of defective SDRAM data outputs for
`assemble on predetermined, complementary memory mod-
`ulcs.
`12. The method of claim 9 wherein determining which
`data outputs are defective includes testing SDRAM oompo-
`nenm prior to assembling the SDR.I\.M components on a
`memory module.
`
`US 6,332,183 B1
`
`presenting a row address to the address inputs of each
`SDRAM component;
`
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`PATENT APPLICATION SERIAL NO.
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`u'.s. DEPARTMENT OF COMMERCE
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`B E ¢ Washington D.C. 20231
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`Case Docket No. 6325
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`Tnmsrriirtcd herewith for filing is the patent application of:
`Inventor: Richard Weber and Corey l.'.arsen
`For: Method for Recovery of Useful Areas or Partially Defective Synchronous Memory Components
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`Enclosed an:
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`8 sheets of Specification, 2 sheets ofclairrts. 1 sheet of in-bstract
`6 Sheen of inforrrtal drawings
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`CIDIIIEI
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`An assi3:rtme.nI: of the invention to
`A certified copy of application.
`Acombinod Declaration and Power of Attorney.
`A Verified Statement to establish small entity status under 37 CM! 1.9 and 3'? CFR L27.
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`The filing fee has been calculated as shown:
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`The Corn:-nissionet is hereby authorized tocharge pay1nen't of the following fees during the pendency of this application
`or credit any overpayment to Deposit Account No. 04-1420. Aduplicate copy of thisshect is encloaed.
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`Pillsbury Cenier South
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`Form P'I‘0- I 032
`ASSISTANT COMMISSIONER FOR PATENTS
`Box Application
`Washington D.C. 20231
`Dear Sir:
`
`Case Docket No. 6325
`
`
`
`T‘r2u-srnittcd ltcrcv.-ith for filing is the patent application of-.
`Inventor: Richard Weber and Corey Larsen _
`For: Method for Recovery of Usefirl Areas oFP_a.:tial1y Dcfoclivc Synchronous Memory Component:
`
`Enclosed are:
`
`8 sheets ofSpet:ification. '2 sheets of Claims. I shoot of Abstract
`6 sheetrof informal drawings
`
`An assignment of the invention to
`A certified copy of application.
`A combined Declaration and Power of Attorney.
`A Verified Statement to establish small entity status under 31 CRR L9 and 3‘! CFR L21’.
`
`CIDDCI
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`The filing for. has been calculated as shown:
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`A check in the amount of $790.00 to cover the filing fee is enclosed.
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`‘The Commissioner is hereby authoriled to charge payment oftlie following fees a.5_5ol':iaI:od with this communication or
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`or crcdit any overpayment to Deposit Account No. D-l-1420. A duplicate copy ufthis sheet is enclosed.
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`1.31 Kb}.
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`Any filing fees unrlu 3'! CFR i.l 6 for presentation of extra claims.
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`Pillsbury Ccntcr Soutli
`220 South Sixth Street
`Minneapolis, MN 55402
`Telephone: 6 l1r'340~StiS9
`Arrorncy for Applicant
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`ihereby certify that this paper or Fee is ‘being deposited with
`the United States Postal Service ‘Express Mail Post Office to
`Addresses” service under 37 CPR LID an the date indicated
`above and is addressed Iotlte Assistant Commissioner for
`Patems. Washixignun DC. 20231
`Eiuma. Smith '
`Name
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`
`Signature
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`SPECIFICATION
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`TO WHOM IT MAY CONCERN:
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`BE IT KNOWN THAT WE, Richard Weber, 3. Citizen of the United States and a resident
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`of Boise, Ada County, Idaho, and Corey Larsen, a Citizen of the United States and a resident of
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`Marsing, Owyhee County, Idaho. have invented certain new and useful improvements in
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`METHOD FOR RECOVERY OFUSEFUL AREAS OF PARTIALLY DEFECTIVE
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`SYNCHRONOUS MEMORY COMPONENTS
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`of which the following is a specification.
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`TITLE:
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`METHOD FOR RECOVERY OF USEFUL AREAS OF PARTIALLY
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`DEFECTIVE SYNCI-IRONOUS MEMORY OOMPONENTS
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`\ ;
`FIELD OF THE INVENTION
`’§°%
`The present invention relates generally to the use partially defective synchronous memory
`chips. More particularly, the present invention relates to the configuration of defective SDRAM
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`components to create a nondefective memory module or array.
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`BACKGROUND AND SUMMARY OF THE DISCLOSURE
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`As is well known in the art, during the production of monolithic memory devices from silicon
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`wafers, some of the memory storage cells can become defective and unreliable. The defective cells
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`I can be the result of a number of causes, such as impurities introduced in the process of
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`manufacturing the monolithic memory device from the silicon wafer. or localized imperfections in
`the silicon substrate itself.
`Often, while some memory cells are defective. many other cells on the same memory chip
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`are not defective. and will work reliably and accurately.
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`In addition, it is often the case that the
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`defective cells are localized and confined to particular outputs from the memory device. The
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`remaining. nondefective outputs can be relied upon to provide a consistent and accurate
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`representation of the information in the storage cell.
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`A
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`Techniques have been developed for salvaging the non-defective portions of defective
`asynchronous‘ memory technologies {e.g., DRAM). Asynchronous memory technologies are
`relatively slow devices that operate in response to control signals generated by a memory controller,
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`rather than in response to the system clock. The control -signals allow the asynchronous memory
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`"device to operate at a speed that is much slower than the system clock, and that ensures reliable read
`and write memory operations.
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`Synchronous memory devices such as SDRAM, on the other hand, are much faster devices
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`that operate on the system clock. SDRAM is an improvement over prior memory technologies
`principally because SDRAM is capable of synchronizing itself with the microprocessors clock. This
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`synchronization caneliminate the time delays and wait states often necessary with prior memory
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`technologies (e.g., DRAM), and it also allows for fast consecutive read and write capability.
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`However. no attempts have been made to salvage non-defective portions of synchronous
`memory. Some people skilled in the art may believe that the use of techniques for salvaging
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`defective memory devices would not workwith higher-speed synchronous memory devices such as
`SDRAM because they operate at much higher speeds than previous memory devices. such as
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`asynchronous DRAM. For SDRAM. it may be believed that the rate at which the clock input cycles
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`and the load on the device driving the inputs (e.g., the clock and the address} to the SDRAM devices {'-
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`would make reliable input transitions unattainable.
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`l
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`The present invention addresses the problem of- salvaging partially defective synchronous
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`memory devices. In one embodiment ofthe present invention, multiple partially defective SDRAM
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`_ components are configured to provide a reliable and nondefective memory module. Such an
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`embodiment takes advantage of the manner in which defective cells are localized on each memory
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`chip, and combines multiple memory chips to provide a memory bus that is of the desired width and
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`granularity. In addition, it is possible with such an embodiment to_ provide a computer system in
`which t_he main memory is synchronized with the system clock, and is constructed, at least in part,
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`from partially defective" memory chips.
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`The nature of the present invention as well as other embodiments of the present invention
`may be more clearly understood by reference to the following detailed description of the invention,
`to the appended claims, and to the several drawings herein.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`Figure 1 is a block tliag1‘a.m of a prior art computer system using a wait state control device
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`with DRAM memory chips.
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`Figure 2 is a block diagram of a oomputer system employing SDRAM memory chips.
`Figure 3 is a block diagram of a partially defective SDRAM component.
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`Figure 4 is a memory map showing the localized nature of defective memory cells in one-
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`embodiment of the present invention.
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`I11?!-1. Manual. 199:
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`Figure 3 is an embodiment of the present invention using six partially defective SDRAM
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`components to make a 64—bit memory module.
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`Figures 6 and 7 are embodiments of the present invention using sixteen defective SDRAM
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`components where four bits in each of the eight hit memory cells are defective.
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`DETAILED DESCRIPTION
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`Figure 1 is a block diagram of a prior art computer system comprising a microprocessor 16.
`a memory controller 14, and main memory 12.
`].n the system shown, main memory 12 is made up,-
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`of dynamic random access memory (DRAM). Also shown in Figure l is a wait state control device
`18 and a system clock 20. As is well known in the art, due to differences in speed between the -
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`processor 16 and the DRAM 12, it is often necessary to insert "wait states" when the processor
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`carries out a memory "operation involving the DRAM 12. Typically, the DRAM 12 is slower than
`the processor 16, so one or more additional states are added to theIrnicroprocessor's memory access
`cycle to ensure that the memory 12 is given a sufficient amount of time to carry out the memory
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`(readfwrite) operation.
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`In addition, the clock 20 in the system of Figure 1 is not a direct input to the DR