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`Attorney Docket No.: 37307-0007IP1
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`In re Patent of: Benisek et al.
`US Patent No.: 6,850,414
`Issue Date:
`February 1, 2005
`Appl. Serial No.: 10/187,763
`§ 371 (c)(1) Date: July 2, 2002
`Title:
`ELECTRONIC PRINTED CIRCUIT BOARD HAVING A
`PLURALITY OF IDENTICALLY DESIGNED, HOUSING-
`ENCAPSULATED SEMICONDUCTOR MEMORIES
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`Attorney Docket No.: 37307-0007IP1
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`DECLARATION OF VIVEK SUBRAMANIAN
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`I, Vivek Subramanian, declare as follows:
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`I.
`1.
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`Introduction.
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`I am making this declaration at the request of the Real Party in Interest
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`(Kingston Technology Company, Inc.) in the matter of Inter Partes Review of U.S.
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`Patent No. 6,850,414 (the “’414 patent”).
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`2.
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`I am being compensated for my work. My compensation does not depend on
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`the outcome of this proceeding.
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`3.
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`I have been asked to consider whether certain references disclose or render
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`obvious the claims of the ’414 Patent, either alone or in combination with each
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`other.
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`KINGSTON 1006
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`Attorney Docket No.: 37307-0007IP1
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`4.
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`I have been advised that a patent claim may be invalid as obvious if the
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`differences between the subject matter patented and the prior art are such that the
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`subject matter as a whole would have been obvious at the time of the invention to a
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`person having ordinary skill in the art. I have also been advised that several factual
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`inquiries underlie a determination of obviousness. These inquiries include the
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`scope and content of the prior art, the level of ordinary skill in the field of the
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`invention, the differences between the claimed invention and the prior art, and any
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`objective evidence of non-obviousness.
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`5.
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`I have been advised that objective evidence of non-obviousness directly
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`attributable to the claimed invention, known as “secondary considerations of non-
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`obviousness,” may include commercial success, satisfaction of a long-felt but
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`unsolved need, failure of others, copying, skepticism or disbelief before the
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`invention, and unexpected results. I am not aware of any such objective evidence
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`of non-obviousness that is directly attributable to the subject matter claimed in the
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`’414 patent at this time.
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`6.
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`In addition, I have been advised that the law requires a “common sense”
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`approach of examining whether the claimed invention is obvious to a person
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`skilled in the art. For example, I have been advised that combining familiar
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`elements according to known methods is likely to be obvious when it does no more
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`than yield predictable results. I have further been advised that this is especially
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`Attorney Docket No.: 37307-0007IP1
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`true in instances where there are a limited numbers of possible solutions to
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`technical problems or challenges.
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`7.
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`I have been informed that all claims of the ’414 Patent are subject to this
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`inter partes review.
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`II. Materials Reviewed
`8.
`In forming the opinions that I express below, I considered my own
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`knowledge of the art plus at least the following references:
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`a. The ’414 Patent
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`b. UK Patent Application GB 2 289 573 A (“Simpson”)
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`c. Intel PC SDRAM Unbuffered DIMM Specification Rev. 1
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`(“Intel Specification”)
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`d. U.S. Patent Application Publication US2002/0196612 A1
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`(“Gall”)
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`e. PC133 SDRAM Registered DIMM Design Specification Rev.
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`1.1 (“PC133 Specification”)
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`f. The File History of U.S. Patent No. 6,850,414
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`g. The File History of U.S. Patent No. 6,332,183
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`III. Qualifications
`9.
`I summarize my relevant knowledge and experience below. My Curriculum
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`Vitae contains additional information and is attached as Exhibit 1010.
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`10. I received a B.S. in electrical engineering from Louisiana State University in
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`1994, an M.S. in electrical engineering from Stanford University in 1996, and a
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`Ph.D. in electrical engineering from Stanford University in 1998.
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`11. I co-founded Matrix Semiconductor, Inc. in 1998 to develop high density
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`memory technology.
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`12. I have been teaching in the Electrical Engineering and Computer Sciences
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`Department at the University of California, Berkeley since 2000. I was an
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`Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to 2011,
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`and a Professor from 2011 to the present.
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`13. I have been an adjunct professor at the Sunchon National University in
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`Sunchon, Korea since 2009, leading research in printed electronics.
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`14. I have been an independent consultant in the semiconductor industry since
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`2000, focusing on memory technology, flexible electronics, and RFID technology.
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`15. I have published more than 200 technical papers in journals and at
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`conferences.
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`16. I am a named inventor on over 40 U.S. Patents, many of which are in the
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`field of memory design.
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`IV. Person of Ordinary Skill in the Art and State of The Art
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`17. In my opinion, a person of ordinary skill in the art as of the time of the ’414
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`Patent would have a Bachelor’s degree in Electrical Engineering and at least 2
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`years’ experience working in the field of semiconductor memory design. I believe
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`this to be a reasonable statement of the level of ordinary skill in the art for the
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`patent and claims at issue. I also believe that I was one of ordinary skill in the art
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`through my education and work experience during the time that I was in
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`University.
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`18. The opinions that I provide in this declaration are consistent with the
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`knowledge and experience of one of ordinary skill in the art at the priority date of
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`the ’414 Patent.
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`19. At the time of the ’414 Patent’s priority date, those of ordinary skill in the
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`art recognized that, within specified design dimensions and tolerances, memory
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`modules and/or error correction devices could be interchanged and oriented in a
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`finite number of ways within the physical size constraints set forth by the industry
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`standards. See Ex. 1002, Simpson, 2:10-15 and Ex. 1003 (Intel Specification).
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`V. Overview of the ’414 Patent
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`20. The ’414 Patent is directed to a printed circuit board (“PCB”) that has at
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`least nine memories chips that are arranged to appreciably reduce the height of the
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`printed circuit board. Ex. 1001, 2:45-3:10. The specification discloses that one of
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`the at least nine chips be an error correction chip and that one be arranged
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`vertically on the printed circuit board, such that the error correction chip
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`determines the maximum height of the printed circuit board, while the other
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`semiconductor memories are arranged horizontally. Ex. 1001, 3:11-27, 6:1-4.
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`21. The supposed invention “is achieved by virtue of the fact that, in the case of
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`the printed circuit board of the generic type, the housings of the identically
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`designed semiconductor memories, other than the error correction chip, are
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`arranged on the printed circuit board in a manner such that they are oriented with
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`their longer dimension parallel to the contact strip.” Ex. 1001, 3:4-10. According
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`to the patent, this allows “a certain, albeit small, narrowing of the printed circuit
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`board.” Ex. 1001, 3:44-46.
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`22. Notably, though as seen in Fig. 1A (front side) and 1B (rear side), the prior
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`art is admitted by the applicant for the patent to disclose a printed circuit board
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`with all semiconductor memories 4 arranged vertically, including the error
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`correction chip 5. Ex. 1001, Figs. 1A and 1B. The purportedly inventive printed
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`circuit board, disclosed by the ’414 Patent, with an error correction chip 5 arranged
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`vertically and remaining semiconductor memories 4 arranged horizontally. Ex.
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`1001, Figs. 2 and 3.
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`FIG. 1A shows the front side of a
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`FIG. 2 shows the front side of an
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`conventional printed circuit board.
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`inventive printed circuit board.
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`FIG. 1B shows the rear side of the
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`conventional printed circuit board.
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`FIG. 3 shows the rear side of the
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`printed circuit board shown in FIG. 2.
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`23. The specification of the patent asserts that the prior art design of Figs. 1A
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`and 1B predetermines the size of the printed circuit board because two resistors
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`“must be arranged between one semiconductor memory 4 and the contact strip 2,
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`because the upper limit for the length of the leads of the resistors from the contact
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`strip 2 permits no other arrangement.” Ex. 1001, 5:59-6:4.
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`24. The specification also explains that by arranging the semiconductor modules
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`horizontally, there is “no need for any resistors” between the housing and the
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`contact strip, and thus “the actual printed circuit board height is determined only
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`by the error correction chip 4b that is brought up to the contact strip 2.” Ex. 1001,
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`6:19-39. Accordingly, this small “reduction of the printed circuit board height
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`enables incorporation into even flatter elements of e.g. network computers.” Ex.
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`1001, 6:47-49. As I describe further below, turning a DRAM chip on its side was
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`well within the skill level of a person even not versed in the art—a person skilled
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`in the art would certainly not find this change inventive.
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`VI. Claim Construction
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`25. The specification of the ’414 does not specifically define the term “error
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`correction,” as recited in the claims of the ’414 patent. However, the specification
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`of the patent does explain that the error correction chip “checks the correctness of
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`the data before the data are passed on.” Ex. 1001 at 7:2-5. It further describes that
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`“the reason for this arrangement is that one of the semiconductor memories is used
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`as an error correction chip in order to perform error checking on data that will be
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`stored in the rest of the semiconductor memories or that will be read from the
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`memories.” Ex. 1001 at 1:51-54. There is no further description in the ’414 patent
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`as to how the error correction chip would correct errors beyond error checking.
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`The remainder of the description related to the error correction chip is directed to
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`its location and physical orientation. The use of the term within the claim itself
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`provides no additional guidance.
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`26. One or ordinary skill in the art would understand that error detection is
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`typically a part error of error correction. In view of the specification, one of
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`ordinary skill in the art would further understand that the broadest reasonable
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`construction of “error correction chip” based on the specification to mean “a chip
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`that is able to perform at least error checking on data stored in other semiconductor
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`memories.”
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`VII. Simpson
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`27. I have been advised, and my understanding is, that Simpson is eligible to
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`serve as prior art for the ’414 Patent under 35 U.S.C. § 102(a). Simpson was
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`published on November 22, 1995 in the United Kingdom, at least five years before
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`the priority date of the ‘414 patent. See Ex. 1002, Simpson. Based on my review
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`of the ’414 patent file history, Simpson was not cited by the USPTO or considered
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`by the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
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`28. Simpson teaches a memory module that “allows the user to customize the
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`module at the point of use rather than having to use the module configured during
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`its manufacture.” Ex. 1002, Simpson, at 7:8-10. Figs. 1 and 3 below illustrate a
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`first face and a second face, respectively, of the preferred embodiment of the
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`invention and design of a printed circuit board.
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`29.
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`30.
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`31. In Simpson, the printed circuit board 2 has a connection terminal 10 for
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`insertion into a module receptacle. Ex. 1002, Simpson, at 10:21-28. The printed
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`circuit board 2 also has memory devices 12A-12H on one face of the printed
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`circuit board 2 that are electrically and mechanically connected. Ex. 1002,
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`Simpson, at 10:1-5, Fig. 2. Both faces include sockets 14A-J to add additional
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`memory or logic devices as needed. Ex. 1002, Simpson, at 10:5-12, Fig. 3.
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`Additional memory devices 18A-H can be added using sockets 14C-J. Ex. 1002,
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`Simpson, at 10:21-30.
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`32. Further, parity memory devices 16 are situated on both faces of the printed
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`circuit board. Ex. 1002, Simpson, at 10:32-11:13. Fig. 1 illustrates the parity
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`memory device 16A arranged perpendicular to the connection terminal 10. Ex.
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`1002, Simpson, at Fig. 1. And, also as illustrated in Fig. 1, sockets 14C-H are
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`arranged parallel to the connection terminal 10. Id. Simpson appreciates that any
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`devices can be added or replaced by sockets as long as the module has a sufficient
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`amount of memory devices to function. Ex. 1002, Simpson, at 8:5-11.
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`VIII. The Intel Specification
`33. I have been advised, and my understanding is, that the Intel Specification is
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`eligible to serve as prior art for the ’414 patent under 35 U.S.C. § 102(a). The Intel
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`Specification has a copyright year of 1997. See Ex. 1003, Intel Specification, at 2.
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`A revision date of February 1998 is listed on the face of the document. Id. at 1.
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`Based on my review of the ’414 patent file history, the Intel Specification was not
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`cited by the USPTO or considered by the Examiner during prosecution. See Ex.
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`1007, the ’414 Patent File History.
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`34. The Intel Specification describes “the electrical and mechanical
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`requirements for 168-pin, 3.3 volt, 64-bit and 72-bit wide, 4 clock, unbuffered
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`Synchronous DRAM Dual In-Line Memory Modules (SDRAM DIMMs).” Ex.
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`1003, Intel Specification, at 7. The document “focuses on six layer double-sided
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`assembly PCB designs.” Id. The Intel Specification recognizes that it “largely
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`follows the JEDEC defined 168-pin unbuffered SDRAM DIMM as of JEDEC
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`committee meeting of December 1996.” Id.
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`35. Though the Intel Specification is directed to a double-sided six layer design,
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`the document specifically recognizes that the same “PCB designs will also work
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`for single sided population with or without stuffing the ECC [error correcting
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`code] Devices.” Id. at 9. Importantly, the Intel Specification details the exact
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`mechanical, physical design ranges for the printed circuit board thus giving the
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`“specific dimensions and tolerances for a 168-pin DIMM.” Id. at 11.
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`36. The Intel Specification thus provides a detailed example of a physical
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`structure that a person of ordinary skill would have understood and likely adhered
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`to at the time of the priority date of the ’414 patent.
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`IX. Simpson and the Intel Specification at the Time of the Invention
`37. Simpson alone, the Intel Specification alone, or in combination discloses the
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`same technology that is allegedly the invention of the ’414 Patent.
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`38. It would have been obvious to modify the printed circuit board and memory
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`module design of Simpson to incorporate the constraints disclosed in the Intel
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`Specification. In the resulting design, Simpson would be constrained and adapted
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`to comply with the design specifications—specifically the physical dimensions—
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`described in the Intel Specification. One of ordinary skill in the art would have
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`been motivated to modify Simpson based on the design dimensions of the Intel
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`Specification and would have had a reasonable expectation of success when doing
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`so.
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`39. The market constraints for the mechanical designs of printed circuit boards
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`continued maturing in the years leading up to the priority date of the ’414 patent.
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`And, those skilled in the art by this time could ably modify circuit boards within
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`the physical constraints of the standards at the time.
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`40. One of ordinary skill in the art would recognize that modifying Simpson to
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`align with the design parameters laid out in the Intel Specification would
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`modernize Simpson. The motivation to combine the references was obvious.
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`41. Applying standards to the design of Simpson was within the knowledge of a
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`person of ordinary skill by the priority date of the ’414 patent.
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`X. Certain References Disclose And/Or Render Obvious All Elements of
`Claims 1-8 of the ‘414 Patent.
`A. Simpson alone, or in combination with the Intel Specification,
`renders obvious all elements of Claim 1-8 of the ’414 Patent
`1.
`Claim 1
`a. “An electronic printed circuit board configuration,
`comprising:”
`42. In my opinion, Simpson discloses an electronic printed circuit board
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`configuration. See Ex. 1002, Simpson, at 1:10-23, 2:17-20, and 4:28-5:5. Marked-
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`up Figure 1 of Simpson clearly illustrates an electronic printed circuit board. Id.
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`43.
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`b. “An electronic printed circuit board having a contact
`strip for insertion into another electronic unit; and”
`44. In my opinion, Simpson discloses an electronic printed circuit board having
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`a contact strip for insertion into another electronic unit. See Ex. 1002, Simpson, at
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`2:24-30, 9:8-16, 10:21-30, and 12:10-14. Specifically, Simpson chooses to use the
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`term “connector terminal strip 10” rather than “contact strip;” however, the terms
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`are interchangeable as one of ordinary skill in the art would recognize.
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`45. This marked-up figure below illustrates how Simpson teaches this element.
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`Id.
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`46.
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`c. “A memory module having at least nine identically
`designed integrated semiconductor memories;”
`47. In my opinion, Simpson discloses a memory module having at least nine
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`identically designed integrated semiconductor memories. See Ex. 1002, Simpson,
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`at Figures 1 and 3, 5:12-18, 5:34-35, 7:8-12, 8:5-11, 9:18-27, 10:10-19, 13:7-12,
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`and 13:28-32.
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`48. As shown in Figure 1, on a single side, Simpson discloses a base module 2
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`that “consists of an array of memory devices 12A-12H[.]” Ex. 1002, Simpson,
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`9:18-20; Fig. 1. Module 2 of Simpson also includes a ninth semiconductor
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`memory 16A on that same side. Ex. 1002, 10:14-25 (referring to each of the chips
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`12A-12H and 16A as memory devices). Those of ordinary skill in the art would
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`understand that the memory device 16A is identical to each of memory devices
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`12A-12H. See Ex. 1002, Simpson at 11:22-28 (referring to power and signals
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`collectively for all of the memory devices) and 12:10-14 (describing common
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`capacitors used to supply power to each of the memory devices).
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`49. However, the ’414 patent are not limited to having chips on a single side of
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`the PCB. Simpson makes clear that “memory devices 12 may be mounted on both
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`sides of the module 2.” Ex. 1002, Simpson, 13:7-12. The illustrated embodiments
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`of Simpson envision empty sockets 14C-14J populated with memory devices 18A-
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`18H plugged in for added memory. Simpson, Ex. 1002, 10:14-19; Fig. 3. One of
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`ordinary skill in the art would also plainly recognize that replaceable memory
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`devices 18A-18H could be identical to memory devices 12A-12H, as this decision
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`would merely depend on in order to enable the addition of those eight chips to
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`increase “the module designer memory capacity from 4Mbits to 8Mbits in length
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`by plugging into sockets 14C-14J memory devices 18A-18H. See Ex. 1002,
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`Simpson, 10:10-12; Figs. 1-3. Additionally, sockets 14A-14B could also be filled
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`with memory devices identical to memory devices 12A-12H as one of ordinary
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`skill in the art would recognize. Id.
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`50. This marked-up figure below illustrates how Simpson teaches this element.
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`Id.
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`51.
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`d. “Each one of said semiconductor memories being
`encapsulated in a rectangular housing having a
`shorter dimension and a longer dimension;”
`52. In my opinion, Simpson discloses that each one of said semiconductor
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`memories are encapsulated in a rectangular housing having a shorter dimension
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`and a longer dimension. See Ex. 1002, Simpson, at Figures 1 and 2.
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`53. Marked-up Figure 1 illustrates how Simpson teaches this element. Id.
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`54.
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`55. Also, Marked-up Figure 2 illustrates this element. Id.
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`56.
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`57. Further, in my opinion, a person of ordinary skill in the art would have
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`understood that Figures 1-3 illustrate memory devices 12, 16, and 18 as being—or
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`could be modified to be—encapsulated in housings, as there is nothing inventive
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`about this limitation. Also, Simpson discloses that “memory devices 12A-12H are
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`electrically and mechanically connected to the substrate 4.” Ex. 1002, Simpson, at
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`10:1-5. Thus, one of ordinary skill would understand that memory devices 12A-
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`12H as well as an identical memory device 12 filling socket 14A would be
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`individually connected to the printed circuit board. Id. at 10:14-30.
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`e. “Said housing of each one of said semiconductor
`memories being identically designed and being
`individually connected to said printed circuit board;”
`58. In my opinion, Simpson discloses on its face that the housing of each one of
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`said semiconductor memories can be identically designed and individually
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`connected to the printed circuit board. See Ex. 1002, Simpson, at Figure 2, 7:8-12,
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`8:5-11, 9:18-27, 10:1-5, 10:5-8, 10:10-19, and 10:21-30.
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`59. Simpson discloses that the “memory devices 12A-12H are electrically and
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`mechanically connected to the substrate 4.” Ex. 1002, Simpson, 10:1-5.
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`Additionally, Simpson discloses that “sockets 14A-14J to take additional devices
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`are also attached to the substrate 4.” Id. at 10:5-8. One of ordinary skill would
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`thus understand that memory devices 12A-12H as well as an identical memory
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`device 12 filling socket 14A would be individually electrically connected to said
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`printed circuit board. Id. at 10:14-30.
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`60. Neither claim 1 nor the ’414 patent require that each of the nine
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`semiconductor memories be soldered directly to the printed circuit board—merely
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`connected. One of ordinary skill in the art would understand that connection of a
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`memory chip via a socket is a type of connection. Moreover, one of ordinary skill
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`in the art would consider the choice of whether to use a socket (as for memory
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`device 16A) or solder the chip directly to the board (as in memory devices 12A-
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`12H) is simply a design choice. In the event that the term “connected” is narrowly
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`construed to exclude the use of a socket, it would have been obvious to one of
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`ordinary skill to remove the socket and solder the memory device 16A to the
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`printed circuit board.
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`61. Moreover, as noted above, Simpson explains that the preferred embodiment
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`could be modified such that “memory devices 12 may be mounted on both sides of
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`the module.” Ex. 1002, Simpson, 13:7-12. These memories 12 would be identical
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`and identically mounted based on the specification of Simpson without the use, or
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`need for, sockets 14.
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`f. “One of said semiconductor memories being
`connected as an error correction chip;”
`62. In my opinion, Simpson discloses that one of the semiconductor memories is
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`connected as an error correction chip. See Ex. 1002, Simpson, at 3:9-27, 4:11-13,
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`6:8-9, 7:19-23, 8:5-11, 10:5-12, 10:10-19, 11:10-13, and 12:25-28.
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`63. One of ordinary skill in the art would recognize that the preferred
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`embodiment “can be upgraded by populating empty sockets 14A-14B” with
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`“parity memory devices” because a parity memory device is a known type of error
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`correction chip. See Ex. 1002, Simpson, at 10:11-19. A person of ordinary skill in
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`the art would understand that a basic error correction chip would be identical in the
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`design of Simpson. Simply put, a basic error correction chip works on an 8 to 1
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`ratio. Each bit on the error correction chip corresponds to the bits spread across
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`the eight other identical chips. Thus, the parity chip 16a here would be understood
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`to be an identical error correction chip when compared with memory devices 12A-
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`12H.
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`64. Also, one of skill in the art would understand using a memory chip identical
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`to 12A-12H as an error correction chip because such a modification of Simpson
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`would constitute no more than an obvious design choice—one of a “finite number
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`of identified, predictable solutions”—to one skilled in the art at the time the ’414
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`patent was filed.
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`65. Marked-up Figure 1 illustrates how Simpson teaches this element. Ex. 1002,
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`Simpson at Figure 1.
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`66.
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`g. “Said longer dimension of said housing of said error
`correction chip being oriented perpendicular to said
`contact strip; and”
`67. In my opinion, Simpson discloses that the longer dimension of the housing
`
`of the error correction chip is oriented perpendicular to the contact strip. See Ex.
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`1002, Simpson, at Figure 1.
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`68. Marked-up Figure 1 illustrates this element. Id.
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`69.
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`h. Said longer dimension of said housing of each one of
`said semiconductor memories, other than said error
`correction chip, being oriented parallel with said
`contact strip.”
`70. In my opinion, Simpson discloses that the longer dimension of the housings
`
`of the semiconductor memories, other than the error correction chip, are oriented
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`parallel to the contact strip. See Ex. 1002, Simpson, at Figure 1.
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`71. Marked up Figure 1 illustrates this element. Id.
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`72.
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`2.
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`Claim 2
`a. “The printed circuit board according to claim 1,
`wherein: said housing of said error correction chip
`extends a greater distance away from said contact
`strip than said housing of each one of said
`semiconductor memories, other than said error
`correction chip.”
`73. In my opinion, Simpson discloses that the housing of the error correction
`
`chip extends a greater distance away from the contact strip that the housing of the
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`semiconductor memories, other than the error correction chip. See Ex. 1002,
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`Simpson, at Figures 1 and 3, 7:8-12, 8:5-11, 9:18-27, 10:5-12, 13:7-12, and 13:28-
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`32.
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`74. Simpson discloses a design such that the parity device 16A is a greater
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`distance away from the connection terminals 10 than the housing of the other
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`memory devices 12A-H and 18A-H. Moreover, one of ordinary skill in the art
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`would understand both that Simpson discloses this design and that it would be
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`obvious to modify Simpson in this way.
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`75. Simpson discloses a memory module with up to 18 separate semiconductor
`
`memories. See Ex. 1002, Simpson, at 10:21-30. Moreover, Simpson discloses that
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`“any devices extra to the minimum required to make the module function in a basic
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`form such as the parity and (second face) memory devices could be omitted and
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`replaced with sockets.” Ex. 1002, Simpson, at 8:5-9. Thus, one of ordinary skill in
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`the art would understand that the module design could choose to include or omit
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`Attorney Docket No.: 37307-0007IP1
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`any of the various individual memory chips, as long as functionality was
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`preserved. Id. at 13:28-32 (“Each feature disclosed in this specification (including
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`any accompanying claims, abstract and drawings), may be replaced by alternative
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`features serving the same, equivalent or similar purpose, unless expressly stated
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`otherwise.”).
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`76. One of ordinary skill in the art, would thus understand that the preferred
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`embodiment illustrated in Figures 1 and 3 discloses this limitation. It is simply a
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`matter of design choice under the guidance of Simpson.
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`77. This is illustrated below by modified Figures 1 and 3. See Ex. 1002,
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`Simpson.
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`78.
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`79.
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`
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`80. As shown, by omitting memory devices 12A, B, E, and G and 18A, C, E,
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`and G (as Simpson describes), the error correction chip (16A) extends a greater
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`distance away from said contact strip than said housing of each one of said
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`semiconductor memories, other than said error correction chip, as required by the
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`claim.
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`81. Moreover, as Simpson illustrates the selection of location for memory chips
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`on a PCB was (at least by the time of Simpson) a simple matter of design choice.
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`One of ordinary skill would understand that the second row of memory devices in
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`Simpson could also have been moved lower on the PCB (into the open area
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`between the rows) to achieve a module in which the error correction chip extends
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`further away from the contact strip than the other memory chips.
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`3.
`
`Claim 3
`a. “The printed circuit board according to claim 1,
`wherein: said contact strip has a contact with a
`length;”
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`82. In my opinion, Simpson discloses a contact strip that has a contact length.
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`See Ex. 1002, Simpson, at Figures 1-3.
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`83. Marked-up Figures 1 and 2 from Simpson illustrate this element. Id.
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`84.
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`85.
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`b. “said printed circuit board has a height extending
`perpendicular to said contact strip; and”
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`Attorney Docket No.: 37307-0007IP1
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`86. In my opinion, Simpson discloses a printed circuit board with a height
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`extending perpendicular to the contact strip. See Ex. 1002, Simpson, at Figures 1-
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`3.
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`87. Marked-up Figure 1 of Simpson illustrates this element. Id.
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`88.
`
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`c. “said height of said printed circuit board is equal to a
`sum of said longer dimension of said housing of said
`error correction chip, said length of said contact of
`said contact strip and a safety clearance between said
`error correction chip and said contact strip of less
`than 2 mm.”
`89. In my opinion, Simpson alone, or in combination with the Intel
`
`Specification, discloses that the height of the printed circuit board is equal to a sum
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`of the longer dimension of the error correction chip housing, the contact length of
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`the contact strip, and the safety clearance between the error correction chip and
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`contact strip of less than 2mm.
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`90. The extra material above the housing of the error correction chip is also
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`known to be unnecessary as one of ordinary skill in the art would understand how
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`to remove it and how to organize the capacitors and resistors within the remaining
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`space. A person of ordinary skill in the art would know how to make this
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`modification and would have a reasonable expectation of success when doing so.
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`91. A safety clearance of at least 2 mm was also known to those skilled in the
`
`art. This point is indisputable based on the Intel Specification. The Intel
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`Specification details that the safety clearance can be a minimum of .05mm to
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`.35mm. Ex. 1003, Intel Specification, at 11, 15. Simply, it is an obvious design
`
`choice.
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`92. Marked-up excerpts from the Intel Specification help to illustrate how this
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`element is met. Id.
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`93.
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`94.
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`4.
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`Claim 4
`a. “The printed circuit board according to claim 1,
`wherein: said printed circuit board has a height of 1
`to 1.2 inches perpendicular to said contact strip.”
`95. In my opinion, Simpson could easily be constructed with a height in the
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`range of 1 to 1.2 inches that is perpendicular to the contact strip. By mid-2001, the
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`dimensions of printed circuit boards had been standardized for some time. And,
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`historically, electrical and computer engineers have always endeavored to shrink
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`electronic components.
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`96. Additionally, Simpson in combination with the Intel Specification shows
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`that a height of 1 to 1.2 inches is standard and one that a person of skill in the art
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`would recognize as an obvious design choice because the Intel Specification
`
`specifically describes that the overall module height dimensions for the DIMM
`
`described is in the range of “25.4 mm (1.0”) to 38.10 mm. (1.5”).” Ex. 1003, Intel
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`Specification, at 11, 13.
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`97. Marked-up excerpts from the Intel Specification help to illustrate how this
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`element is met. Id.
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`98.
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