PC133 SDRAM Registered DIMM
`Design Specification
`Revision 1.1
`August 1999
`
`Prepared By IBM and Reliance Computer Corporation
`
`1
`
`KINGSTON 1005
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`All information contained in this document is subject to change without notice. The products described in this document
`are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death
`to persons. The information contained in this document does not affect or change IBM product specifications or warran-
`ties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property
`rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is
`presented as an illustration. The results obtained in other operating environments may vary.
`
`THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be
`liable for damages arising directly or indirectly from any use of the information contained in this document.
`
`Page 2
`
`Revision 1.0
`
`2
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`Product Description .................................................................................................................................. 1
`Product Family Attributes ...................................................................................................................... 1
`
`Environmental Requirements................................................................................................................... 2
`
`Architecture ............................................................................................................................................... 2
`Environmental Parameters.................................................................................................................... 2
`Pin Description ...................................................................................................................................... 2
`Input/Output Functional Description...................................................................................................... 3
`Registered SDRAM DIMM Pinout ......................................................................................................... 4
`Block Diagram: Raw Card Version E .................................................................................................... 9
`Termination for Unused Clock Signals (CK1-CK3) ............................................................................. 10
`Clock Net Wiring (CK0) ....................................................................................................................... 10
`Register Functional Assignments........................................................................................................ 11
`Register Functional Assignments (continued)..................................................................................... 12
`
`Component Details.................................................................................................................................. 13
`Pin Assignments for 64Mb and 128Mb SDRAM Planar Components ................................................ 13
`Pin Assignments for 64Mb and 128Mb 54 pin SDRAM 2 High Stack Package
`(Dual CS Pin)............................................................................................................................................. 14
`Pin Assignments for 256Mb 54 pin SDRAM Planar Components....................................................... 15
`Pin Assignments for 256Mb 54 pin SDRAM 2 High Stack Package
`(Dual CS Pin)............................................................................................................................................. 16
`Pin Assignments for 256Mb 66 pin SDRAM 2 High Stack Package
`(Dual CS Pin)............................................................................................................................................. 17
`(Top View)........................................................................................................................................... 17
`SDRAM Component Specifications .................................................................................................... 18
`Register Component Specifications .................................................................................................... 21
`Register Sourcing................................................................................................................................ 21
`PLL Component Specifications ........................................................................................................... 22
`PLL Sourcing....................................................................................................................................... 22
`DIMM PLL Use.................................................................................................................................... 22
`
`Registered DIMM Details......................................................................................................................... 23
`SDRAM Module Configurations (Reference Designs) ........................................................................ 23
`PC133 Gerber Releases ..................................................................................................................... 24
`Input Loading Matrix............................................................................................................................ 24
`Example Raw Card Version A Component Placement ....................................................................... 25
`Example Raw Card Version B (Planar) and E Component Placement............................................... 26
`Example Raw Card Versions B (Stacked) and C Component Placement .......................................... 27
`Example Raw Card Version D Component Placement....................................................................... 28
`
`Revision 1.0
`
`Page iii
`
`3
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`DIMM Wiring Details ................................................................................................................................ 29
`Signal Groups ..................................................................................................................................... 29
`General Net Structure Routing Guidelines.......................................................................................... 29
`Explanation of Net Structure Diagrams............................................................................................... 30
`Clock Net Structures ........................................................................................................................... 31
`Data Net Structures............................................................................................................................. 33
`Data Mask Net Structures ................................................................................................................... 34
`Chip Select Net Structures .................................................................................................................. 36
`Clock Enable Net Structures ............................................................................................................... 39
`Address/Control Net Structures .......................................................................................................... 43
`Cross Section Recommendations....................................................................................................... 46
`
`Timing Budget.......................................................................................................................................... 47
`DIMM Post-Register Timing ................................................................................................................ 47
`*DIMM Clock Contributions (tSkew).................................................................................................... 47
`
`Serial PD Definition ................................................................................................................................. 48
`Serial Presence Detect Data EXAMPLE............................................................................................. 48
`
`Product Label........................................................................................................................................... 50
`
`DIMM Mechanical Specifications ........................................................................................................... 51
`
`Supporting Hardware .............................................................................................................................. 52
`Clock Reference Board ....................................................................................................................... 52
`
`Application Notes .................................................................................................................................... 53
`Clocking Timing Methodology ............................................................................................................. 53
`Revision Log ....................................................................................................................................... 54
`
`Page iv
`
`Revision 1.0
`
`4
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`Product Description
`
`Product Description
`
`This specification defines the electrical and mechanical requirements for 168-pin, 3.3 Volt, 133MHz, 72-bit
`wide, Registered Synchronous DRAM Dual In-Line Memory Modules (SDRAM DIMMs).These SDRAM
`DIMMs are intended for use as main memory when installed in systems such as servers and workstations.
`
`Reference design examples are included which provide an initial basis for Registered DIMM designs. Modifi-
`cations to these reference designs may be required to meet all system timing, signal integrity and thermal
`requirements for 133MHz support. All registered DIMM implementations must use simulations and lab verifi-
`cation to ensure proper timing requirements and signal integrity in the design.
`
`This specification largely follows the JEDEC defined 168-pin 8-Byte Registered SDRAM DIMM product.
`(Refer to JEDEC standard 21-C, Section 4.5.7, at www.jedec.org).
`
`Product Family Attributes
`
`DIMM Organization
`
`x 72 ECC
`
`DIMM Dimensions (nominal)
`
`5.25" x 1.5"/1.7" x .157"/.320"
`
`Pin Count
`
`SDRAMs Supported
`
`Capacity
`
`Serial PD
`
`Voltage Options
`
`Interface
`
`168
`
`64Mb, 128Mb, 256Mb
`
`64MB, 128MB, 256MB, 512MB, 1GB
`
`Consistent with JEDEC Rev. 2.0
`
`3.3 volt (VDD/VDDQ)
`
`LVTTL
`
`Revision 1.1
`
`Page 5
`
`5
`
`

`
`Environmental Requirements
`
`PC133 SDRAM Registered DIMM Design Specification
`
`Environmental Requirements
`
`PC133 SDRAM Registered DIMMs are intended for use in standard office environments that have limited
`capacity for heating and air conditioning.
`
`Environmental Parameters
`
`Symbol
`
`TOPR
`
`HOPR
`
`TSTG
`
`HSTG
`
`Parameter
`
`Operating Temperature (ambient)
`
`Operating Humidity (relative)
`
`Storage Temperature
`
`Storage Humidity (without condensation)
`
`Barometric Pressure (operating & storage)
`
`Rating
`
`0 to +55
`
`10 to 90
`
`-50 to +100
`
`5 to 95
`
`105 to 69
`
`Units
`
`Notes
`
`°C
`
`%
`
`°C
`
`%
`
`1
`
`1
`
`1
`
`1
`
`K Pascal
`
`1, 2
`
`1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
`operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
`may affect reliability.
`2. Up to 9850 ft.
`
`Architecture
`
`Pin Description
`
`CK(0:3)
`
`Clock Inputs
`
`CKE(0:1)
`
`Clock Enables
`
`RAS
`
`CAS
`
`WE
`
`Row Address Strobe
`
`Column Address Strobe
`
`Write Enable
`
`S(0:3)
`
`Chip Selects
`
`A(0:9,11:12)
`
`Address Inputs
`
`A10/AP
`
`Address Input/Autoprecharge
`
`DQ(0:63)
`
`Data Input/Output
`
`CB(0:7)
`
`ECC Data Input/Output
`
`DQMB(0:7)
`
`Data Mask
`
`VDD
`
`VSS
`
`NC
`
`SCL
`
`SDA
`
`Power (3.3V)
`
`Ground
`
`No Connect
`
`Serial Presence Detect Clock Input
`
`Serial Presence Detect Data Input/Output
`
`BA0-BA1
`
`SDRAM Bank Address
`
`SA(0:2)
`
`Serial Presence Detect Address Inputs
`
`REGE
`
`DU
`
`Register Enable
`
`Don’t Use - leave as NC
`
`WP
`
`NC
`
`Write Protect for SPD on DIMM
`
`No Connect
`
`Page 6
`
`Revision 1.1
`
`6
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`Input/Output Functional Description
`
`Symbol
`
`Type
`
`Polarity
`
`Function
`
`CK0 - CK3
`
`Input
`
`CKE0,1
`
`Input
`
`Positive
`Edge
`
`Active
`High
`
`The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their associ-
`ated clock. CK0 drives the PLL. CK1, CK2 & CK3 are terminated.
`
`Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
`ing the clocks, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh
`mode.
`
`S0 - S3
`
`Input
`
`Active Low
`
`Enables the associated SDRAM command decoder when low and disables the command decoder
`when high. When the command decoder is disabled, new commands are ignored but previous
`operations continue. Physical Bank 0 is selected by S0 and S2; Bank 1 is selected by S1 and S3.
`
`RAS, CAS
`WE
`
`Input
`
`Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to
`be executed by the SDRAM.
`
`BA0, 1
`
`Input
`
`—
`
`Selects which SDRAM bank of four is activated.
`
`A0 - A9,
`A11-12
`A10/AP
`
`Input
`
`—
`
`During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sam-
`pled at the rising clock edge.
`During a Read or Write command cycle, A0-A10 defines the column address (CA0-CA10) when
`sampled at the rising clock edge. In addition to the column address, AP is used to invoke autopre-
`charge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
`selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled.
`During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which
`bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or
`BA1. If AP is low, then BA0 and BA1 are used to define which bank to precharge.
`
`DQ0 - DQ63,
`CB0 - CB7
`
`Input
`Output
`
`—
`
`Data and Check Bit Input/Output pins.
`
`DQMB0 -
`DQMB7
`
`Input
`
`Active
`High
`
`The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high
`impedance state when sampled high. In Read mode, DQMB has a latency of two clock cycles in
`Buffered mode or three clock cycles in Registered mode, and controls the output buffers like an
`output enable. In Write mode, DQMB has a zero clock latency in Buffered mode and a latency of
`one clock cycle in Registered mode. In this case, DQMB operates as a byte mask by allowing input
`data to be written if it is low but blocks the write operation if it is high.
`
`VDD, VSS
`
`Supply
`
`Power and ground for the module.
`
`REGE
`
`Input
`
`Active
`High
`(Register
`Mode
`Enable)
`
`The Register Enable pin is used to permit the DIMM to operate in Buffered mode (inputs re-driven
`asynchronously) or Registered mode (signals re-driven to SDRAMs when clock rises, and held
`valid until next rising clock).
`
`SA0 - 2
`
`Input
`
`SDA
`
`Input
`Output
`
`SCL
`
`Input
`
`—
`
`—
`
`—
`
`These signals are tied at the system planar to either VSS or VDD to configure the SPD EEPROM.
`
`This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be
`connected from the SDA bus time to VDD to act as a pull up.
`
`This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
`from the SCL bus time to VDD to act as a pull up.
`
`WP
`
`Input
`
`Active
`High
`
`This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the
`SPD EEPROM.
`
`Revision 1.1
`
`Page 7
`
`7
`
`

`
`Architecture
`
`PC133 SDRAM Registered DIMM Design Specification
`
`egistered SDRAM DIMM Pinout
`
`. R
`
`Pin#
`
`1
`
`2
`
`3
`
`4
`
`Front
`Side
`
`VSS
`
`DQ0
`
`DQ1
`
`DQ2
`
`Pin#
`
`85
`
`86
`
`87
`
`88
`
`Back
`Side
`
`VSS
`
`DQ32
`
`DQ33
`
`DQ34
`
`Pin#
`
`22
`
`23
`
`24
`
`25
`
`Front
`Side
`
`CB1
`
`VSS
`
`NC
`
`NC
`
`Pin#
`
`106
`
`107
`
`108
`
`109
`
`110
`
`Back
`Side
`
`CB5
`
`VSS
`
`NC
`
`NC
`
`Pin#
`
`43
`
`44
`
`45
`
`46
`
`47
`
`Front
`Side
`
`VSS
`
`NC
`
`S2
`
`Pin#
`
`127
`
`128
`
`129
`
`Back
`Side
`
`VSS
`
`CKE0
`
`S3
`
`DQMB2
`
`130 DQMB6
`
`DQMB3
`
`131 DQMB7
`
`Pin#
`
`64
`
`65
`
`66
`
`67
`
`68
`
`Front
`Side
`
`VSS
`
`DQ21
`
`DQ22
`
`DQ23
`
`Pin#
`
`148
`
`149
`
`150
`
`151
`
`152
`
`Back
`Side
`
`VSS
`
`DQ53
`
`DQ54
`
`DQ55
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`DQ3
`
`VDD
`
`DQ4
`
`DQ5
`
`DQ6
`
`DQ7
`
`89
`
`90
`
`91
`
`92
`
`93
`
`94
`
`DQ35
`
`VDD
`
`DQ36
`
`DQ37
`
`DQ38
`
`DQ39
`
`26
`
`27
`
`28
`
`29
`
`30
`
`31
`
`VDD
`
`WE
`
`VDD
`
`CAS
`
`111
`
`DQMB0
`
`112 DQMB4
`
`DQMB1
`
`113 DQMB5
`
`S0
`
`NC
`
`114
`
`115
`
`S1
`
`RAS
`
`48
`
`49
`
`50
`
`51
`
`52
`
`NC
`
`VDD
`
`NC
`
`NC
`
`CB2
`
`132
`
`133
`
`134
`
`135
`
`136
`
`NC
`
`VDD
`
`NC
`
`NC
`
`CB6
`
`69
`
`70
`
`71
`
`72
`
`73
`
`VSS
`
`DQ24
`
`DQ25
`
`DQ26
`
`DQ27
`
`VDD
`
`153
`
`154
`
`155
`
`156
`
`157
`
`VSS
`
`DQ56
`
`DQ57
`
`DQ58
`
`DQ59
`
`VDD
`
`DQ60
`
`11
`
`12
`
`13
`
`14
`
`15
`
`DQ8
`
`VSS
`
`DQ9
`
`DQ10
`
`DQ11
`
`95
`
`96
`
`97
`
`98
`
`99
`
`DQ40
`
`VSS
`
`DQ41
`
`DQ42
`
`DQ43
`
`32
`
`33
`
`34
`
`35
`
`36
`
`VSS
`
`A0
`
`A2
`
`A4
`
`A6
`
`116
`
`117
`
`118
`
`119
`
`120
`
`121
`
`VSS
`
`A1
`
`A3
`
`A5
`
`A7
`
`A9
`
`53
`
`54
`
`55
`
`56
`
`57
`
`58
`
`CB3
`
`VSS
`
`DQ16
`
`DQ17
`
`DQ18
`
`DQ19
`
`137
`
`138
`
`139
`
`140
`
`141
`
`142
`
`CB7
`
`VSS
`
`DQ48
`
`DQ49
`
`DQ50
`
`DQ51
`
`74
`
`75
`
`76
`
`77
`
`78
`
`79
`
`DQ28
`
`DQ29
`
`DQ30
`
`DQ31
`
`VSS
`
`CK2
`
`158
`
`159
`
`160
`
`161
`
`162
`
`163
`
`DQ61
`
`DQ62
`
`DQ63
`
`VSS
`
`CK3
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`DQ12
`
`DQ13
`
`VDD
`
`DQ14
`
`DQ15
`
`100
`
`101
`
`102
`
`103
`
`104
`
`DQ44
`
`DQ45
`
`VDD
`
`DQ46
`
`DQ47
`
`CB0
`
`105
`
`CB4
`
`37
`
`38
`
`39
`
`40
`
`41
`
`42
`
`A8
`
`A10/AP 122
`
`BA1
`
`VDD
`
`VDD
`
`123
`
`124
`
`125
`
`BA0
`
`A11
`
`VDD
`
`CK1
`
`CK0
`
`126
`
`A12
`
`59
`
`60
`
`61
`
`62
`
`63
`
`VDD
`
`DQ20
`
`NC
`
`NC
`
`CKE1/
`NC
`
`143
`
`144
`
`145
`
`146
`
`VDD
`
`DQ52
`
`NC
`
`NC
`
`147
`
`REGE
`
`80
`
`81
`
`82
`
`83
`
`84
`
`NC
`
`WP
`
`SDA
`
`SCL
`
`VDD
`
`164
`
`165
`
`166
`
`167
`
`168
`
`NC
`
`SA0
`
`SA1
`
`SA2
`
`VDD
`
`Note: All pin assignments are consistent with all 8-byte unbuffered versions.
`
`Page 8
`
`Revision 1.1
`
`8
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`Architecture
`
`Block Diagram: Raw Card Version A (Populated as 1 physical bank of x8 SDRAMs)
`
`RDQMB4
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`RDQMB5
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`RDQMB6
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`RDQMB7
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`CS
`
`D5
`
`CS
`
`D6
`
`CS
`
`D7
`
`CS
`
`D8
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`#Unless otherwise noted,
`resistor values are 10 Ohms.
`
`PLL
`CK0
`CK1, CK2, CK3 Terminated
`
`CS
`
`D0
`
`CS
`
`D1
`
`CS
`
`D2
`
`CS
`
`D3
`
`CS
`
`D4
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`Serial Presence Detect
`
`SCL
`
`WP
`47K
`
`VDD
`
`VSS
`
`SDA
`
`A0
`
`A1
`
`A2
`
`SA0 SA1 SA2
`
`D0 - D8
`
`D0 - D8
`
`Note: DQ wiring may differ from that described
`in this drawing; however DQ/DQMB
`relationships are maintained as shown.
`
`Note: Register, PLL and Serial Presence
`Detect are all connected to VDD.
`
`RS0/RS2
`RDQMB0 - RDQMB7
`RBA0 - RBA1
`RA0-RA12
`RRAS
`RCAS
`RCKE0
`RWE
`
`BA0-BA1: SDRAMs D0-D8
`A0-A12: SDRAMs D0-D8
`RAS: SDRAMs D0 - D8
`CAS: SDRAMs D0 - D8
`CKE: SDRAMs D0 - D8
`WE: SDRAMs D0 - D8
`
`REGISTE R
`
`RS0
`RDQMB0
`
`#
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`RDQMB1
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`CB0
`CB1
`CB2
`CB3
`CB4
`CB5
`CB6
`CB7
`
`RS2
`RDQMB2
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`RDQMB3
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`S0/S2
`DQMB0 to DQMB7
`BA0-BA1
`A0-A12
`RAS
`CAS
`CKE0
`WE
`VDD
`REGE
`PCK
`
`10k
`
`Revision 1.1
`
`Page 9
`
`9
`
`

`
`Architecture
`
`PC133 SDRAM Registered DIMM Design Specification
`
`Block Diagram: Raw Card Version B (Populated as 1 physical bank of x4 SDRAMs)
`
`RS0
`RDQMB0
`#
`
`DQ0
`DQ1
`DQ2
`DQ3
`
`DQ4
`DQ5
`DQ6
`DQ7
`RDQMB1
`
`DQ8
`DQ9
`DQ10
`DQ11
`
`DQ12
`DQ13
`DQ14
`DQ15
`
`CB0
`CB1
`CB2
`CB3
`RS2
`RDQMB2
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`CS
`
`D0
`
`CS
`
`D1
`
`CS
`
`D2
`
`CS
`
`D3
`
`CS
`
`D4
`
`CS
`
`D5
`
`RDQMB4
`
`DQ32
`DQ33
`DQ34
`DQ35
`
`DQ36
`DQ37
`DQ38
`DQ39
`RDQMB5
`
`DQ40
`DQ41
`DQ42
`DQ43
`
`DQ44
`DQ45
`DQ46
`DQ47
`
`CB4
`CB5
`CB6
`CB7
`
`RDQMB6
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`CS
`
`D9
`
`CS
`
`D10
`
`CS
`
`D11
`
`CS
`
`D12
`
`D13
`
`CS
`
`CS
`
`D14
`
`Serial Presence Detect
`
`SCL
`
`WP
`47K
`
`VDD
`
`VSS
`
`SDA
`
`A0
`
`A1
`
`A2
`
`SA0 SA1 SA2
`
`D0 - D8
`
`D0 - D8
`
`Note: DQ wiring may differ from that described
`in this drawing; however, DQ/DQMB
`relationships are maintained as shown.
`
`Note: Register, PLL and Serial Presence
`Detect are all connected to VDD.
`
`PLL
`CK0
`CK1, CK2, CK3 Terminated
`
`DQ16
`DQ17
`DQ18
`DQ19
`
`DQ20
`DQ21
`DQ22
`DQ23
`
`RDQMB3
`
`DQ24
`DQ25
`DQ26
`DQ27
`
`DQ28
`DQ29
`DQ30
`DQ31
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`CS
`
`D6
`
`CS
`
`D7
`
`CS
`
`D8
`
`DQ48
`DQ49
`DQ50
`DQ51
`
`DQ52
`DQ53
`DQ54
`DQ55
`
`RDQMB7
`
`DQ56
`DQ57
`DQ58
`DQ59
`
`DQ60
`DQ61
`DQ62
`DQ63
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`CS
`
`D15
`
`CS
`
`D16
`
`CS
`
`D17
`
`#Unless otherwise noted, resistor values are 10 Ohms.
`RS0/RS2
`RDQMB0 - RDQMB7
`RBA0 - RBA1
`RA0-RA12
`RRAS
`RCAS
`RCKE0
`RWE
`
`BA0-BA1: SDRAMs D0-D17
`A0-A12: SDRAMs D0-D17
`RAS: SDRAMs D0 - D17
`CAS: SDRAMs D0 - D17
`CKE: SDRAMs D0 - D17
`WE: SDRAMs D0 - D17
`
`REGISTE R
`
`S0/S2
`DQMB0 to DQMB7
`BA0-BA1
`A0-A12
`RAS
`CAS
`CKE0
`WE
`VDD
`REGE
`PCK
`
`10k
`
`Page 10
`
`Revision 1.1
`
`10
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`Architecture
`
`Block Diagram: Raw Card Version B (Populated as 2 physical banks of x4 SDRAMs)
`
`RDQMB0
`#
`
`DQ0
`DQ1
`DQ2
`DQ3
`
`DQ4
`DQ5
`DQ6
`DQ7
`RDQMB1
`
`DQ8
`DQ9
`DQ10
`DQ11
`
`DQ12
`DQ13
`DQ14
`DQ15
`
`RS1
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D0
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D1
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D2
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D3
`
`CB0
`CB1
`CB2
`CB3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`RS3
`RDQMB2
`
`D4
`
`RS0
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D18
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D19
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D20
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D21
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D22
`
`RDQMB4
`
`DQ32
`DQ33
`DQ34
`DQ35
`
`DQ36
`DQ37
`DQ38
`DQ39
`RDQMB5
`
`DQ40
`DQ41
`DQ42
`DQ43
`
`DQ44
`DQ45
`DQ46
`DQ47
`
`CB4
`CB5
`CB6
`CB7
`
`RDQMB6
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D9
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D10
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D11
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D12
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D13
`CS
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D27
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D28
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D29
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D30
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D31
`CS
`
`RS2
`
`D5
`
`D23
`
`D14
`
`D32
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D24
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D25
`
`CS
`
`D26
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQ48
`DQ49
`DQ50
`DQ51
`
`DQ52
`DQ53
`DQ54
`DQ55
`RDQMB7
`
`DQ56
`DQ57
`DQ58
`DQ59
`
`DQ60
`DQ61
`DQ62
`DQ63
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D15
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D16
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D17
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D33
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D34
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D35
`
`Note: DQ wiring
`may differ from that
`described in this
`drawing; however,
`DQ/DQMB relation-
`ships are main-
`tained as shown.
`
`Note: Register, PLL and
`Serial Presence Detect
`are all connected to VDD.
`
`PLL
`Termination
`
`Serial PD
`
`SCL
`
`WP
`
`A0
`
`A1
`
`A2
`
`SDA
`
`47k
`
`SA0
`
`SA1
`
`SA2
`
`VDD
`
`VSS
`
`D0 - D35
`
`D0 - D35
`
`RS0-RS3
`CK0
`CK1, CK2 & CK3
`RDQMB0 - RDQMB7
`RBA0
`BA0, RBA1
`BA1: SDRAMs D0-D35
`RA0-RA12
`A0-A12: SDRAMs D0-D35
`RRAS
`RAS: SDRAMs D0 - D35
`CAS: SDRAMs D0 - D35
`RCAS
`CKE: SDRAMs D0 - D35
`RCKE0
`WE: SDRAMs D0 - D35
`RWE
`
`REGISTER
`
`#: Unless otherwise noted, resistor values are 10 OHMS.
`
`DQ16
`DQ17
`DQ18
`DQ19
`
`DQ20
`DQ21
`DQ22
`DQ23
`RDQMB3
`
`DQ24
`DQ25
`DQ26
`DQ27
`
`DQ28
`DQ29
`DQ30
`DQ31
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D6
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D7
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D8
`
`S0-S3
`DQMB0 to DQMB7
`BA0, BA1
`A0-A12
`RAS
`CAS
`CKE0
`WE
`
`10k
`
`VDD
`REGE
`PCK
`
`Revision 1.1
`
`Page 11
`
`11
`
`

`
`Architecture
`
`PC133 SDRAM Registered DIMM Design Specification
`
`Block Diagram: Raw Card Versions C & D (Populated as 2 physical banks of x4 SDRAMs)
`
`RDQMB0
`#
`
`DQ0
`DQ1
`DQ2
`DQ3
`
`DQ4
`DQ5
`DQ6
`DQ7
`RDQMB1
`
`DQ8
`DQ9
`DQ10
`DQ11
`
`DQ12
`DQ13
`DQ14
`DQ15
`
`RS1
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D0
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D1
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D2
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D3
`
`CB0
`CB1
`CB2
`CB3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`RS3
`RDQMB2
`
`D4
`
`RS0
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D18
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D19
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D20
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D21
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D22
`
`RDQMB4
`
`DQ32
`DQ33
`DQ34
`DQ35
`
`DQ36
`DQ37
`DQ38
`DQ39
`RDQMB5
`
`DQ40
`DQ41
`DQ42
`DQ43
`
`DQ44
`DQ45
`DQ46
`DQ47
`
`CB4
`CB5
`CB6
`CB7
`
`RDQMB6
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D9
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D10
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D11
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D12
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D13
`CS
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D27
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D28
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D29
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D30
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D31
`CS
`
`RS2
`
`D5
`
`D23
`
`D14
`
`D32
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D24
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D25
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D26
`
`DQ48
`DQ49
`DQ50
`DQ51
`
`DQ52
`DQ53
`DQ54
`DQ55
`RDQMB7
`
`DQ56
`DQ57
`DQ58
`DQ59
`
`DQ60
`DQ61
`DQ62
`DQ63
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D15
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D16
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D17
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D33
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D34
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D35
`
`Note: DQ wiring
`may differ from that
`described in this
`drawing; however,
`DQ/DQMB relation-
`ships are main-
`tained as shown.
`
`Note: Register, PLL and
`Serial Presence Detect
`are all connected to VDD.
`
`RS0-RS3
`CK0
`CK1, CK2 & CK3
`RDQMB0 - RDQMB7
`RBA0
`BA0, RBA1
`BA1: SDRAMs D0-D35
`RA0-RA12
`A0-A12: SDRAMs D0-D35
`RAS: SDRAMs D0 - D35
`RRAS
`RCAS
`CAS: SDRAMs D0 - D35
`CKE: SDRAMs D0 - D35
`RCKE0
`WE: SDRAMs D0 - D35
`RWE
`
`REGISTE R
`
`DQ16
`DQ17
`DQ18
`DQ19
`
`DQ20
`DQ21
`DQ22
`DQ23
`RDQMB3
`
`DQ24
`DQ25
`DQ26
`DQ27
`
`DQ28
`DQ29
`DQ30
`DQ31
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D6
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D7
`
`DQM CS
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`
`D8
`
`S0-S3
`DQMB0 to DQMB7
`BA0, BA1
`A0-A12
`RAS
`CAS
`CKE0
`WE
`
`10k
`
`VDD
`REGE
`PCK
`Note: Alternate decks in front and back side stack modules selected to improve heat dissipation characteristics.
`
`#: Unless otherwise noted, resistor values are 10 OHMS.
`
`PLL
`Termination
`
`Serial PD
`
`SCL
`
`WP
`
`A0
`
`A1
`
`A2
`
`SDA
`
`47k
`
`SA0
`
`SA1
`
`SA2
`
`VDD
`
`VSS
`
`D0 - D35
`
`D0 - D35
`
`Page 12
`
`Revision 1.1
`
`12
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`Architecture
`
`Block Diagram: Raw Card Version E (Populated as 2 physical bank of x8 SDRAMs)
`
`RS0
`
`RDQMB0
`
`RS1
`
`*
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`RDQMB1
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`CB0
`CB1
`CB2
`CB3
`CB4
`CB5
`CB6
`CB7
`
`S3
`
`RS2
`
`CS
`
`D0
`
`CS
`
`D1
`
`CS
`
`D2
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`
`D9
`
`CS
`
`D10
`
`RDQMB4
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`RDQMB5
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`CS
`
`DQM
`
`D11
`
`RDQMB6
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`
`D5
`
`CS
`
`D6
`
`CS
`
`D7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`
`D14
`
`CS
`
`D15
`
`CS
`
`D16
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`RDQMB7
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`
`D8
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`
`D17
`
`PLL
`CK0
`CK1, CK2, CK3 Terminated
`
`CS
`
`D3
`
`CS
`
`D4
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`
`D12
`
`CS
`
`D13
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`RS0-RS3
`RDQMB0 - RDQMB7
`RBA0-RBA1
`BA0-BA1:
`SDRAMs D0-D17
`RA0-RA12
`A0-A12: SDRAMs D0-D17
`RRAS
`RAS: SDRAMs D0 - D17
`CAS: SDRAMs D0 - D17
`RCAS
`*CKE0: SDRAMs D0 - D17 or SDRAMs D0-D8
`RCKE0
`
`Serial PD
`
`SCL
`WP
`47K
`
`A0
`
`A1
`
`A2
`
`SA0 SA1 SA2
`
`DQMB2
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`RDQMB3
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`S0-S3
`DQMB0 to DQMB7
`BA0-BA1
`A0-A12
`RAS
`CAS
`CKE0
`
`VDD
`
`SDA
`
`Note: Register, PLL and
`Serial Presence Detect
`are all connected to VDD.
`
`Note: Exact DQ wiring may differ
`from that are described in the
`drawing (except for DQ/DQMB
`relationships which are maintained
`aas shown).
`
`REGISTE R
`
`10k
`
`10k
`
`CKE1
`WE
`VDD
`REGE
`PCK
`*This raw card can be provided with either CKE0 wired to all SDRAMs, or
`CKE0 wired to one physical bank, and CKE1 wired to the second physical bank.
`* All resistor values are 10 ohms.
`
`RCKE1
`RWE
`
`*CKE1: no SDRAMs or D9-D17
`WE: SDRAMs D0 - D17
`
`VDD
`
`VSS
`
`D0 - D17
`
`D0 - D17
`
`Revision 1.1
`
`Page 13
`
`13
`
`

`
`Architecture
`
`PC133 SDRAM Registered DIMM Design Specification
`
`Termination for Unused Clock Signals (CK1-CK3)
`
`Unused
`CLK
`
`10 Ohm
`
`12pF
`
`Clock Net Wiring (CK0)
`
`0ns
`
`SDRAM SDRAM
`
`(4 SDRAM loads max. per output)
`
`CK0
`
`10Ω 12pf
`
`IN
`
`OUT1
`
`PCK
`
`PLL
`
`FDBK
`IN
`
`C
`
`SDRAM
`
`SDRAM
`
`PCK
`OUT ‘N’
`
`Register #1
`
`(Typically 2 or more registers per DIMM)
`
`Register N
`
`Notes
`1. PLL outputs (PCK) must be wired to assure tracking within ± 100ps at the load (any SDRAM to any SDRAM
`or any padding capacitor, or any register to any register).
`2. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
`3. A maximum of four SDRAM loads should be placed on each PLL output. If there are fewer than four loads,
`adjust line lengths and capacitive loading on PLL outputs to compensate for lighter loading.
`4. Feedback capacitor value ‘C’ is to be determined based on the phase characteristics of the PLL, and should
`be selected and verified using the PC100/PC133 Clock Reference Board.
`
`Page 14
`
`Revision 1.1
`
`14
`
`

`
`PC133 SDRAM Registered DIMM Design Specification
`
`Architecture
`
`Register Functional Assignments
`
`Raw Card Version A (Two Registers)
`
`Raw Card Versions B, C, and D (Three Registers)
`
`Register 1
`
`Register 2
`
`Register 1
`
`Register 2
`
`Register 3
`
`In
`
`A0
`
`A1
`
`A2
`
`A3
`
`A4
`
`A5
`
`A6
`
`Out
`
`RA0
`
`RA1
`
`RA2
`
`RA3
`
`RA4
`
`RA5
`
`RA6
`
`In
`
`Out
`
`DQMB2
`
`RDQMB2
`
`DQMB3
`
`RDQMB3
`
`DQMB6
`
`RDQMB6
`
`DQMB7
`
`RDQMB7
`
`S2
`
`RS2
`
`CKE0
`
`RCKE0
`
`BA0
`
`RBA0
`
`In
`
`A0
`
`A1
`
`A2
`
`A3
`
`A4
`
`A5
`
`A6
`
`Out
`
`RA0A
`
`RA1A
`
`RA2A
`
`RA3A
`
`RA4A
`
`RA5A
`
`RA6A
`
`In
`
`A0
`
`A1
`
`A2
`
`A3
`
`A4
`
`A5
`
`A6
`
`Out
`
`RA0B
`
`RA1B
`
`RA2B
`
`RA3B
`
`RA4B
`
`RA5B
`
`RA6B
`
`In
`
`Out
`
`DQMB0
`
`RDQMB0
`
`DQMB1
`
`RDQMB1
`
`DQMB2
`
`RDQMB2
`
`DQMB3
`
`RDQMB3
`
`DQMB4
`
`RDQMB4
`
`DQMB5
`
`RDQMB5
`
`DQMB6
`
`RDQMB6
`
`RDQMB7
`
`A7
`
`A8
`
`A9
`
`S0
`
`RA7
`
`RA8
`
`RA9
`
`RS0
`
`BA1
`
`A10
`
`A11
`
`A121
`
`RBA1
`
`RA10
`
`RA11
`
`RA12
`
`DQMB0
`
`RDQMB0
`
`DQMB1
`
`RDQMB1
`
`DQMB4
`
`RDQMB4
`
`DQMB5
`
`RDQMB5
`
`CAS
`
`RAS
`
`WE
`
`RCAS
`
`RRAS
`
`RWE
`
`1. Only used with 256Mbit SDRAMs.
`
`A7
`
`A8
`
`A9
`
`A10
`
`A11
`
`BA0
`
`BA1
`
`CAS
`
`RAS
`
`CKE0
`
`CKE0
`
`RA7A
`
`RA8A
`
`RA9A
`
`RA10A
`
`RA11A
`
`RBA0A
`
`RBA1A
`
`RCASA
`
`RRASA
`
`CKE0A
`
`CKE0B
`
`A7
`
`A8
`
`A9
`
`A10
`
`A11
`
`BA0
`
`BA1
`
`CAS
`
`RAS
`
`RA7B
`
`RA8B
`
`RA9B
`
`RA10B
`
`RA11B
`
`RBA0B
`
`RBA1B
`
`RCASB
`
`RRASB
`
`DQMB7
`
`S0
`
`S1
`
`S2
`
`S3
`
`WE
`
`WE
`
`A121
`
`A121
`
`RS0
`
`RS1
`
`RS2
`
`RS3
`
`RWEA
`
`RWEB
`
`RA12A
`
`RA12B
`
`Revision 1.1
`
`Page 15
`
`15
`
`

`
`Architecture
`
`PC133 SDRAM Registered DIMM Design Specification
`
`Register Functional Assignments (continued)
`
`Register 1
`
`Register 2
`
`Register 3
`
`Raw Card Version E (Three Registers)
`
`In
`
`A0
`
`A1
`
`A2
`
`A3
`
`A4
`
`A5
`
`A6
`
`Out
`
`RA0A
`
`RA1A
`
`RA2A
`
`RA3A
`
`RA4A
`
`RA5A
`
`RA6A
`
`In
`
`A0
`
`A1
`
`A2
`
`A3
`
`A4
`
`A5
`
`A6
`
`Out
`
`RA0B
`
`RA1B
`
`RA2B
`
`RA3B
`
`RA4B
`
`RA5B
`
`RA6B
`
`RA7B
`
`In
`
`DQMB0
`
`DQMB1
`
`DQMB2
`
`DQMB3
`
`DQMB4
`
`DQMB5
`
`DQMB6
`
`DQMB7
`
`Out
`
`RDQMB0
`
`RDQMB1
`
`RDQMB2
`
`RDQMB3
`
`RDQMB4
`
`RDQMB5
`
`RDQMB6
`
`RDQMB7
`
`A7
`
`A8
`
`A9
`
`A10
`
`A11
`
`BA0
`
`BA1
`
`RAS
`
`CAS
`
`RA7A
`
`RA8A
`
`RA9A
`
`RA10A
`
`RA11A
`
`RBA0A
`
`RBA1A
`
`RRASA
`
`RCASA
`
`A7
`
`A8
`
`A9
`
`A10
`
`A11
`
`BA0
`
`BA1
`
`RAS
`
`CAS
`
`RA8B
`
`RA9B
`
`RA10B
`
`RA11B
`
`RBA0B
`
`RBA1B
`
`RRASB
`
`RCASB
`
`S0
`
`S1
`
`S2
`
`S3
`
`WE
`
`WE
`
`A121
`
`A121
`
`CKE0
`
`CKE12
`
`RS0
`
`RS1
`
`RS2
`
`RS3
`
`RWEA
`
`RWEB
`
`RA12A
`
`RA12B
`
`RCKE0
`
`RCKE1
`
`1. Only used with 256Mbit SDRAMs.
`2. R/C ’E’ can be produced with either CKE0 wired to all SDRAMs (this pin would not be used), or CKE0 can be wired to one physical
`bank and CKE1 wired to the second physical