Trials@uspto.gov
`571-272-7822
`
`
`Paper 7
`Entered: February 15, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2016-01622
`Patent 6,850,414 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, JEAN R. HOMERE, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`CLEMENTS, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314 and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571-272-7822
`
`
`Paper 7
`Entered: February 15, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2016-01622
`Patent 6,850,414 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, JEAN R. HOMERE, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`CLEMENTS, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314 and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2016-01622
`Patent 6,850,414 B2
`
`
`I.
`
`INTRODUCTION
`
`Kingston Technology Company, Inc. (“Petitioner”) filed a Petition
`
`requesting inter partes review of claims 1–8 (“the challenged claims”) of
`
`U.S. Patent No. 6,850,414 (Ex. 1001, “the ’414 patent”). Paper 2 (“Pet.”).
`
`Polaris Innovations Ltd. (“Patent Owner”) filed a Preliminary Response.
`
`Paper 6 (“Prelim. Resp.”). We review the Petition pursuant to 35 U.S.C.
`
`§ 314, which provides that an inter partes review may be authorized only if
`
`“the information presented in the petition . . . and any [preliminary]
`
`response . . . shows that there is a reasonable likelihood that the petitioner
`
`would prevail with respect to at least 1 of the claims challenged in the
`
`petition.” 35 U.S.C. § 314(a); 37 C.F.R. § 42.4(a). Upon consideration of
`
`the Petition and the Preliminary Response, we determine that the
`
`information presented by Petitioner establishes that there is a reasonable
`
`likelihood that Petitioner would prevail in showing the unpatentability of at
`
`least one of the challenged claims of the ’414 patent. Accordingly, pursuant
`
`to 35 U.S.C. § 314, we institute an inter partes review of claims 1 and 5–8
`
`of the ’414 patent.
`
`A. Related Proceedings
`
`The ’414 patent is involved in Polaris Innovations Ltd. v. Kingston
`
`Tech. Co., Inc., Case No. 8:16-cv-300 (C.D. Cal.). Pet. 1; Paper 4, 1.
`
`Petitioner also has filed other petitions seeking inter partes review of related
`
`patents: Case IPR2016-01621 and Case IPR2016-01623.
`
`B. The ’414 patent
`
`The ’414 patent, titled “Electronic printed circuit board having a
`
`plurality of identically designed, housing-encapsulated semiconductor
`
`2
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`IPR2016-01622
`Patent 6,850,414 B2
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`memories,” issued February 1, 2005, from U.S. Patent Application
`
`No. 10/187,763. Ex. 1001 at [54], [45], [21].
`
`The ’414 patent generally relates to an electronic printed circuit board
`
`having a memory module comprised of identically designed semiconductor
`
`memories configured on the printed circuit board. Id. at Abstract.
`
`According to the ’414 patent, “Printed circuit boards of this type are inserted
`
`into motherboards of personal computers or network computers and serve as
`
`the main memory.” Id. at 1:21–23. Figures 1A and 1B are reproduced
`
`below.
`
`Figure 1A shows the front side of a conventional printed circuit board and
`
`Figure 1B shows the rear side of a conventional printed circuit board. Id. at
`
`5:6–10. In a conventional arrangement, semiconductor memories 4 are
`
`arranged on the front and rear sides of the printed circuit board in the same
`
`orientation as error correction chip 5. Id. at 1:62–67. “In the case of this
`
`
`
`3
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`IPR2016-01622
`Patent 6,850,414 B2
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`conventional arrangement . . . there is no more leeway for a further reduction
`
`of the circuit board height (the height of the printed circuit board
`
`perpendicular to the contact strip).” Id. at 2:37–41. In network computers,
`
`however, “the printed circuit boards are inserted into compartment-type
`
`elements having a small height, for which reason the printed circuit boards
`
`themselves should also have only a small height.” Id. at 1:23–27.
`
`To address this problem, the ’414 patent discloses an electronic
`
`printed circuit board in which the error correction chip remains oriented
`
`perpendicular to the contact strip but the other semiconductor memories are
`
`oriented parallel to the contact strip, such that it is “possible to reduce the
`
`height of the printed circuit board while enabling the rectangular housing to
`
`keep the same physical form.” Id. at Abstract. Figure 2 is reproduced
`
`below.
`
`Figure 3 shows the rear side of a printed circuit board according to an
`
`embodiment of the ’414 patent. Id. at 5:13–14. In this arrangement,
`
`housings 5a of semiconductor memories 4a are arranged horizontally on
`
`printed circuit board 1, and only housing 5b of error correction chip 4b is
`
`arranged vertically. Id. at 6:19–28. Housing 5b is “brought up to [] contact
`
`
`
`4
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`IPR2016-01622
`Patent 6,850,414 B2
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`strip 2 as close as possible” because “there is no need for any resistors 8
`
`[between housing 5b and contact strip 2], as in the case of all of the other
`
`identically designed semiconductor memories 4a that are configured
`
`horizontally.” Id. at 6:28–35. “As a result, the height of printed circuit
`
`board 1 can be reduced from a value of H1 to a smaller value H2” (id. at
`
`6:41–42), as shown in Figure 2, which is reproduced below.
`
`Figure 2 shows the front side of a printed circuit board according to an
`
`embodiment of the ’414 patent. Id. at 5:11–12.
`
`
`
`C. Illustrative Claim
`
`Of the challenged claims, claim 1 is independent and claims 2–8
`
`depend from claim 1. Independent claim 1 is illustrative of the challenged
`
`claims and is reproduced below:
`
`1. An electronic printed circuit board configuration,
`comprising:
`
`an electronic printed circuit board having a contact strip for
`insertion into another electronic unit; and
`
`a memory module having at least nine identically designed
`integrated semiconductor memories;
`
`semiconductor memories being
`said
`each one of
`encapsulated in a rectangular housing having a shorter dimension
`and a longer dimension;
`
`5
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`IPR2016-01622
`Patent 6,850,414 B2
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`
`said housing of each one of said semiconductor memories
`being identically designed and being individually connected to said
`printed circuit board;
`
`one of said semiconductor memories being connected as an
`error correction chip;
`
`said longer dimension of said housing of said error
`correction chip being oriented perpendicular to said contact strip;
`and
`
`said longer dimension of said housing of each one of said
`semiconductor memories, other than said error correction chip,
`being oriented parallel with said contact strip.
`
`Ex. 1001, 7:24–8:3.
`
`D. Evidence Relied Upon
`
`Petitioner relies upon the following prior art references:
`
`Simpson
`
`GB 2 289 573 A
`
`Nov. 22, 1995
`
`PC SDRAM UNBUFFERED DIMM SPECIFICATION, REV. 1.0, 1997
`(the “Intel Specification”).
`
`Ex. 1002
`
`Ex. 1003
`
`Pet. 9. Petitioner also relies upon the Declaration of Vivek Subramanian,
`
`Ph.D. (“Subramanian Decl.”) (Ex. 1006).
`
`E. Asserted Grounds of Unpatentability
`
`Petitioner asserts that the challenged claims are unpatentable based on
`
`the following grounds (Pet. 9):
`
`Basis Claims challenged
`References
`§ 103
`1–8
`Simpson
`Simpson and Intel Specification § 103
`1–8
`Intel
`§ 103
`1–8
`
`6
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`Patent 6,850,414 B2
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`
`II. ANALYSIS
`
`A. Claim Construction
`
`In an inter partes review, a claim in an unexpired patent shall be given
`
`its broadest reasonable construction in light of the specification of the patent
`
`in which it appears. 37 C.F.R. § 42.100(b). Under the broadest reasonable
`
`construction standard, claim terms are given their ordinary and customary
`
`meaning, as would be understood by one of ordinary skill in the art in the
`
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`
`1257 (Fed. Cir. 2007). Any special definition for a claim term must be set
`
`forth in the specification with reasonable clarity, deliberateness, and
`
`precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). We must be
`
`careful not to read a particular embodiment appearing in the written
`
`description into the claim if the claim language is broader than the
`
`embodiment. See In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993).
`
`Only terms that are in controversy need to be construed, and then only to the
`
`extent necessary to resolve the controversy. Vivid Techs., Inc. v. Am. Sci. &
`
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`Petitioner proposes a construction for “error correction chip.” Pet. 7–
`
`8. Patent Owner does not propose explicit constructions of any particular
`
`terms, but several of its arguments turn on the meaning of “identically
`
`designed,” “connected,” and “error correction chip.” See, e.g., Prelim. Resp.
`
`23–34. On this record, and for purposes of this Decision, we determine that
`
`only the terms “connected” and “error correction chip” requires express
`
`construction.
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`1. “connected” (claim 1)
`
`Patent Owner argues “Simpson’s alleged error correction chip is not
`
`‘connected’ to the [printed circuit board] as claimed,” because it is mounted
`
`in a socket rather than soldered directly to the printed circuit board. Prelim.
`
`Resp. 31. Petitioner argues that “a socket is a type of connection.” Pet. 22
`
`(citing Subramanian Decl. ¶ 59). We agree with Petitioner. The ’414 patent
`
`does not explicitly define “connected” and Patent Owner identifies nothing
`
`in the Specification to support a construction of that term to exclude
`
`connections via a socket.
`
`On this record, and for purposes of this decision, we agree with
`
`Petitioner that the broadest reasonable interpretation of “connected”
`
`encompasses being connected to the printed circuit board via a socket.
`
`2. “error correction chip” (claim 1)
`
`Petitioner argues that “error correction chip” should be construed to
`
`mean “a chip that is able to perform at least error checking on data stored in
`
`other semiconductor memories.” Pet. 7–8. Patent Owner argues that the
`
`term “error correction chip” excludes Simpson’s parity memory device
`
`because a parity memory device “may provide ‘error detection,’ [but] cannot
`
`perform ‘error correction.’” Prelim. Resp. 32–33. Patent Owner’s
`
`argument is not persuasive. The ’414 patent does not expressly define the
`
`term “error correction chip.” The ’414 patent describes the error correction
`
`chip as “check[ing] the correctness of the data,” but not necessarily
`
`correcting errors:
`
`Data that is transported to the semiconductor memory modules
`4a always contain check data. The error correction chip, namely
`memory module, 4b checks the correctness of the data before
`the data are passed on.
`
`8
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`IPR2016-01622
`Patent 6,850,414 B2
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`Ex. 1001, 7:1–4. More importantly, the ’414 patent expressly discloses an
`
`example in which the “error correction” method is merely a check bit, i.e., a
`
`parity bit, that is added to the data to be communicated to the memory
`
`module:
`
`A wide variety of methods are known according to which the
`error correction chip, namely memory module, 4b can operate.
`An example that shall be mentioned here is the ECC method
`(error correcting code), in which a check bit is added to eight
`bits of data to be communicated.
`
`Ex. 1001, 7:5–9 (emphasis added). This is consistent with Simpson’s
`
`description of the parity bit, which “is assigned to every group of eight data
`
`bits of memory.” Ex. 1002, 3:9–13. Because the ’414 patent expressly
`
`contemplates “a check bit” as one of the “ECC method[s]” that may be
`
`employed by the claimed “error correction chip,” we are persuaded that the
`
`’414 patent uses the term “error correction” broadly enough to encompass
`
`parity.
`
`On this record, and for purposes of this decision, we agree with
`
`Petitioner that the broadest reasonable interpretation of “error correction
`
`chip” is “a chip that is able to perform at least error checking on data stored
`
`in other semiconductor memories.”
`
`B. Claims 1–8: Obviousness over Simpson
`
`Petitioner argues that the challenged claims are unpatentable under
`
`35 U.S.C. § 103(a) as obvious over Simpson alone or in view of the Intel
`
`Specification. Pet. 10–43.1 In light of the arguments and evidence of
`
`
`
`1 Petitioner cites the Intel Specification only with respect to claims 3, 4, and
`8. Pet. 33–34 (claim 3), 36–37 (claim 4), 42–43 (claim 8). Accordingly, we
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`record, we are persuaded that Petitioner has established a reasonable
`
`likelihood that the claims 1 and 5–8 are unpatentable as obvious over
`
`Simpson.
`
`1. Simpson (Ex. 1002)
`
`Simpson describes a memory module with memory devices and with
`
`sockets on one or both faces of the module for coupling additional memory
`
`modules. Ex. 1002, [57]. Figures 1 and 3 of Simpson are reproduced below.
`
`
`
`
`
`
`
`first analyze claims 1–8 for obviousness over Simpson. In the next section,
`we analyze claims 3, 4, and 8 for obviousness over Simpson and the Intel
`Specification.
`
`10
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`Patent 6,850,414 B2
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`Figures 1 and 3 depict a front view and a rear view, respectively, of a
`
`memory module according to Simpson. Id. at 12:19–26. As shown in
`
`Figure 1, printed circuit board 2 includes memory devices 12A–H oriented
`
`horizontally to contact strip 10 and parity memory device 16A mounted in
`
`socket 14A oriented vertically to contact strip 10. Id. at 9:18–10:17.
`
`2. Claim 1
`
`With respect to claim 1, Petitioner relies upon Simpson’s printed
`
`circuit board 2 with contact strip 10 as teaching “an electronic printed circuit
`
`board having a contact strip,” relies upon memory devices 12A–H and 16A
`
`as teaching “nine identically designed integrated semiconductor memories,”
`
`relies upon Figure 1 as teaching that memory devices 12A–H and 16A are
`
`“encapsulated in a rectangular housing,” each of which is “identically
`
`designed” and “individually connected to said printed circuit board.” Pet.
`
`16–23. Petitioner relies upon Simpson’s memory device 16A as teaching
`
`“an error correction chip,” and relies upon Figure 1 as teaching memory
`
`device 16A “being oriented perpendicular to said contact strip,” and memory
`
`devices 12A–H “being oriented parallel with said contact strip.” Pet. 23–27.
`
`Patent Owner argues that (1) Simpson is not directed towards
`
`reducing the height of a printed circuit board (Prelim. Resp. 12–15); (2)
`
`Simpson does not teach nine “identically designed” semiconductor
`
`memories with “identically designed” housings (id. at 18, 24–31); (3)
`
`Simpson’s alleged “error correction chip” is not “connected” to the printed
`
`circuit board (id. at 18, 31–32); and (4) Simpson’s alleged “error correction
`
`chip” performs only error detection, not error correction (id. at 18, 32–33).
`
`We address each argument in turn.
`
`11
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`Patent 6,850,414 B2
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`a. Reducing the height
`
`Patent Owner argues that Simpson is not directed towards reducing
`
`the height of a printed circuit board. Prelim. Resp. 12–15. Patent Owner’s
`
`argument is unpersuasive because it is not commensurate with the claims,
`
`which do not recite reducing the height of a printed circuit board.
`
`b. “identically designed”
`
`Patent Owner argues that “Petitioner never even argues, let alone
`
`attempts to show, that the purported ‘error correction chip’ in Simpson is
`
`‘identically designed’ in comparison with the memory chips.” Prelim. Resp.
`
`25. To the contrary, Petitioner argues that “[t]hose of ordinary skill in the
`
`art would understand that the memory device 16A is identical to each of
`
`memory devices 12A-12H.” Pet. 19 (citing Subramanian Decl. ¶ 48; Ex.
`
`1002, 12:10–14, 22-28).
`
`Patent Owner also argues that Simpson “teaches that these error
`
`correction auxiliary devices are logic devices and, therefore, are not
`
`identically designed to its other memory modules.” Prelim. Resp. 25–26
`
`(citing Ex. 1002, 14:8–10, 10:8–9, 3:30–34, claim 9). Although Patent
`
`Owner recognizes that “it is possible to design a system . . . where the error
`
`correction chip is ‘identically designed’ to the other memory modules” by
`
`placing the logic element elsewhere on the system, Patent Owner argues that
`
`a person of ordinary skill in the art “would not assume that built-in error
`
`correction logic exists elsewhere in any system using Simpson’s [printed
`
`circuit board].” Id. at 27. Patent Owner also argues that the housing of
`
`memory devices 12A–H and the housing of memory device 16A are not
`
`“identically designed” because the housing of memory device 16A includes
`
`two extra pins. Id. at 28–29. The ’414 patent, however, concedes expressly
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`12
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`IPR2016-01622
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`that “the components illustrated [in Figures 2 and 3]”—including memory
`
`modules 4a (the recited “semiconductor memories”) and 4b (the recited
`
`“error correction chip”)—“and their functions correspond to the prior art.”
`
`Ex. 1001, 6:57–60 (emphasis added). As a result, even assuming that
`
`Simpson does not teach explicitly that memory devices 12A–H and its
`
`memory device 16A are not “identically designed,” we are nevertheless
`
`persuaded that Petitioner is correct in asserting that it would have been
`
`obvious to one of ordinary skill in the art at the time that memory devices
`
`12A–H and memory device 16A could be “identically designed.”
`
`c. “connected"
`
`Patent Owner argues that Simpson’s alleged “error correction chip”—
`
`i.e., memory device 16A—is not “connected” to the printed circuit board
`
`because it is in socket 14A. Prelim. Resp. 31–32. This argument is not
`
`persuasive because it is based on a construction of “connected” that we
`
`declined to adopt for the reasons discussed above. We are persuaded by
`
`Petitioner’s contention that “[o]ne of ordinary skill in the art would
`
`understand that connection of a memory chip via a socket is a type of
`
`connection.” Pet. 22 (citing Subramanian Decl. ¶ 60).
`
`d. “error correction chip"
`
`Patent Owner argues that Simpson’s memory device 16A—i.e., a
`
`parity memory device—is not an “error correction chip” because it “may
`
`provide ‘error detection,’ [but] cannot perform ‘error correction.’” Prelim.
`
`Resp. 32–33. This argument is not persuasive because it is based upon a
`
`construction of “error correction chip” that we declined to adopt for the
`
`reasons discussed above. We are persuaded that the ’414 patent uses “error
`
`correction chip” to encompass parity devices and, therefore, are persuaded
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`IPR2016-01622
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`by Petitioner’s contention that Simpson’s memory device 16A, described as
`
`a parity memory device, teaches an “error correction chip.”
`
`At this stage in the proceeding, we are persuaded by Petitioner’s
`
`explanations and supporting evidence regarding independent claim 1. Based
`
`on the record before us, Petitioner has demonstrated a reasonable likelihood
`
`that it would prevail on its assertion that independent claim 1 would have
`
`been obvious over Simpson.
`
`3. Dependent claims 5–8
`
`We have reviewed Petitioner’s explanations and supporting evidence
`
`regarding dependent claims 5–8 and find them persuasive. See Pet. 38–43.
`
`Patent Owner does not argue separately dependent claims 5–8. Based on the
`
`record before us, Petitioner has demonstrated a reasonable likelihood that it
`
`would prevail on its assertion that claims 5–8 would have been obvious over
`
`Simpson.
`
`4. Dependent claims 2-4
`
`Dependent claim 2 recites “said housing of said error correction chip
`
`extends a greater distance away from said contact strip than said housing of
`
`each one of said semiconductor memories, other than said error correction
`
`chip.” Ex. 1001, 8:4–8. Petitioner, recognizing that Simpson’s memory
`
`chips 12A, C, E, and G, extend a greater distance away from contact strip 10
`
`than does the housing of memory device 16A, argues that “by omitting
`
`memory devices 12A, [C], E, and G and 18A, C, E, and G (as Simpson
`
`describes), the error correction chip (16A) extends a greater distance away
`
`from said contact strip than said housing of each one of said semiconductor
`
`memories” (Pet. 30), and includes the annotated figure reproduced below:
`
`14
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`According to Petitioner, the teaching of two rows in Simpson “is simply a
`
`matter of design choice” (Pet. 29) and “[o]ne of ordinary skill in the art
`
`would understand that the module design could choose to include or omit
`
`any of the various individual memory chips” (id. at 28). See also id. at 30
`
`(arguing design choice).
`
`Patent Owner argues that, although Petitioner “argues that a [person
`
`of ordinary skill in the art] would be able to make such a modification,”
`
`Petitioner “does not propose a single reason why a [person of ordinary skill
`
`in the art] would be motivated to make this particular modification.” Prelim.
`
`Resp. 35–36. We agree. It is not sufficient to demonstrate that each of a
`
`claim’s limitations is known. See KSR Int’l Co. v. Teleflex Inc., 550 U.S.
`
`398, 418 (2007) (“a patent composed of several elements is not proved
`
`obvious merely by demonstrating that each of its elements was,
`
`independently, known in the prior art”). Petitioner must also explain how a
`
`person of ordinary skill in the art would combine those embodiments and
`
`why such a person would be motivated to do so. In re Chaganti, 2014, WL
`
`274514, *4 (Fed. Cir. 2014) (“It is not enough to say that . . . to do so would
`
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`IPR2016-01622
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`‘have been obvious to one of ordinary skill.’ Such circular reasoning is not
`
`sufficient–more is needed to sustain an obviousness rejection.”). Here,
`
`Petitioner has not explained sufficiently why a person of ordinary skill in the
`
`art would have modified Simpson to omit memory devices 12A, C, E, and
`
`G. Accordingly, on the record before us, we are not persuaded that
`
`Petitioner has provided an articulated reasoning with some rational
`
`underpinning to support the legal conclusion of obviousness. See KSR, 550
`
`U.S. 418 (2007) (citing In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)). As
`
`a result, we are not persuaded that Petitioner has established a reasonable
`
`likelihood that it would prevail in showing that claim 2 would have been
`
`obvious over Simpson.
`
`For claim 3, Petitioner relies upon the same proposed modification as
`
`in claim 2. See, e.g., Pet 33 (explaining for claim 3 that “capacitors 20
`
`. . . could be moved into the empty space provided by the omission of
`
`several memory devices or sockets as explained supra”). Thus, for the same
`
`reasons explained above with respect to claim 2, we are not persuaded that
`
`Petitioner has established a reasonable likelihood that it would prevail in
`
`showing that claim 3 would have been obvious over Simpson.
`
`Claim 4 recites, “said printed circuit board has a height of 1 to 1.2
`
`inches perpendicular to said contact strip.” Petitioner argues that a person of
`
`ordinary skill in the art would have had a reasonable expectation of success
`
`in limiting Simpson to a height of 1 to 1.2 inches and would have been
`
`motivated to do so because, inter alia, “engineers have historically sought to
`
`reduce the size of electronic components.” Pet. 35–36. Patent Owner argues
`
`that Petitioner “does not even explain how Simpson’s two rows of sockets
`
`could fit on a [printed circuit board] with a height of 1.0-1.2 inches.”
`
`16
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`Prelim. Resp. 39. According to Patent Owner, Simpson teaches “sockets
`
`arranged in two rows with dimensions that are significantly larger than the
`
`chip package itself . . . significantly increasing the height of the [printed
`
`circuit board.” Id. at 41. We agree that Petitioner has not explained
`
`sufficiently how or why a person of ordinary skill in the art would have
`
`modified Simpson to achieve a height of “1 to 1.2 inches perpendicular to
`
`said contact strip.” Id. at 39. As a result, we are not persuaded that
`
`Petitioner has established a reasonable likelihood that it would prevail in
`
`showing that claim 4 would have been obvious over Simpson.
`
`5. Conclusion
`
`On this record, we are persuaded that Petitioner has established a
`
`reasonable likelihood that it would prevail in showing that claims 1 and 5–8
`
`are unpatentable as obvious over Simpson alone.
`
`C. Claims 3, 4, and 8: Obviousness over
`Simpson and the Intel Specification
`
`Petitioner argues that the challenged claims are unpatentable under
`
`35 U.S.C. § 103(a) as obvious over Simpson in view of the Intel
`
`Specification. Pet. 10–43. Petitioner cites the Intel Specification, however,
`
`only with respect to claims 3, 4, and 8. Pet. 33–34, 36–37, 42. Accordingly,
`
`we analyze only claims 3, 4, and 8 for obviousness over the combination of
`
`Simpson and the Intel Specification. In light of the arguments and evidence
`
`of record, we are not persuaded that Petitioner has established a reasonable
`
`likelihood that the claims 3 and 4 are unpatentable as obvious over the
`
`combination of Simpson and the Intel Specification. Also, we decline to
`
`institute this ground as to claim 8.
`
`17
`
`
`
`IPR2016-01622
`Patent 6,850,414 B2
`
`
`1. Intel Specification (Ex. 1003)
`
`The Intel Specification describes “the electrical and mechanical
`
`requirements for 168-pin, 3.3 volt, 64-bit and 72-bit wide, 4 clock,
`
`unbuffered Synchronous DRAM Dual In-Line Memory Modules (SDRAM
`
`DIMMs).” Ex. 1003, 7. “This specification largely follows the JEDEC
`
`defined 168-pin unbuffered SDRAM DIMM as of JEDEC committee
`
`meeting of December 1996.” Id. The Intel Specification “give[s] the
`
`specific dimensions and tolerances for a 168-pin DIMM.” Id. at 11.
`
`2. Claims 3 and 4
`
`As discussed above, we are not persuaded that Petitioner has
`
`established a reasonable likelihood that it would prevail in showing that
`
`claims 3 and 4 would have been obvious over Simpson because it has not
`
`explained adequately how and/or why a person of ordinary skill in the art
`
`would have made the proposed modifications to Simpson. In this ground,
`
`Petitioner cites the Intel Specification for its teaching of a safety clearance of
`
`less than 2mm (Pet. 33–34 (for claim 3)) and for its teaching of a height in
`
`the range of 1 to 1.2 inches (Pet. 36–37 (for claim 4)). In both cases,
`
`however, Petitioner continues to rely solely on its argument that the
`
`limitations would have been an “obvious design choice” without explaining
`
`persuasively how and/or why a person of ordinary skill in the art would have
`
`made the proposed modifications to Simpson in view of the teachings of the
`
`Intel Specification. As a result, we are not persuaded that Petitioner has
`
`established a reasonable likelihood that it would prevail in showing that
`
`claims 3 and 4 would have been obvious over the combination of Simpson
`
`and the Intel Specification.
`
`18
`
`
`
`IPR2016-01622
`Patent 6,850,414 B2
`
`
`3. Claim 8
`
`The Board’s rules for AIA inter partes proceedings, including those
`
`pertaining to institution, are “construed to secure the just, speedy, and
`
`inexpensive resolution of every proceeding.” 37 C.F.R. § 42.1(b); accord
`
`35 U.S.C. §§ 316(b) (regulations for AIA inter partes proceedings take into
`
`account “the efficient administration of the Office” and “the ability of the
`
`Office to timely complete [instituted] proceedings”). Because we institute
`
`an inter partes review of claim 8 based on the ground discussed above, we
`
`exercise our discretion not to institute a review based on this ground for
`
`reasons of administrative expediency to ensure timely completion of the
`
`instituted proceeding. See 37 C.F.R. § 42.108(a) (“the Board may authorize
`
`the review to proceed . . . on all or some of the grounds of unpatentability
`
`asserted for each claim”); 35 U.S.C. § 314(a) (authorizing institution of an
`
`inter partes review under particular circumstances, but not requiring
`
`institution under any circumstances); Harmonic Inc. v. Avid Tech., Inc., 815
`
`F.3d 1356, 1368 (Fed. Cir. 2016) (“[U]nder [37 C.F.R. § 42.108(a)], it is
`
`clear that the Board may choose to institute some grounds and not institute
`
`others as part of its comprehensive institution decision.”).
`
`D. Claims 1–8: Obviousness over the Intel Specification
`
`Petitioner argues that the challenged claims are unpatentable under
`
`35 U.S.C. § 103 as obvious over the Intel Specification. Pet. 9.
`
`Claim 1 recites “said longer dimension of said housing of each one of
`
`said semiconductor memories, other than said error correction chip, being
`
`oriented parallel with said contact strip.” Petitioner relies on Intel’s teaching
`
`of an embodiment in which memory devices are oriented parallel to a
`
`contract strip. Pet. 51 (citing Ex. 1003, 34). Petitioner contends that
`
`19
`
`
`
`IPR2016-01622
`Patent 6,850,414 B2
`
`
`One of ordinary skill would recognize that there is nothing
`novel about the orientation of semiconductor memories and that
`it would be obvious to arrange memories on a printed circuit
`board as necessary in any orientation within the specification
`limitations set forth by the Intel Specification. Ex. 1006,
`Subramanian Decl. at ¶137; see also MPEP 2143(A) (Combining
`prior art teaching (vertical vs horizontal orientations) according
`to known methods to produce predictable results—it would be
`predictable that a horizontal orientation would yield a shorter
`height for a PCB.); MPEP 2143(E) (“obvious to try” choosing
`from a finite (horizontal or vertical) number of predictable
`solutions.).
`
`Moreover, the Intel Specification recognizes that a printed
`circuit board could have “components mounted on one or both
`sides of the PCB.” Ex. 1003, Intel Specification at 34. With that
`said, one of ordinary skill in the art would also understand that
`there would be no physical constraints to moving four of the
`memory components from the Intel memory module to the back
`side with a horizontal orientation. Ex. 1006, Subramanian Decl.
`at ¶137.
`
`Id. at 51–52.
`
`Patent Owner argues that “[t]he Petition further fails to articulate even
`
`a single reason why a [person of ordinary skill in the art] would modify the
`
`Intel Specification in the manner proposed to arrive at the claimed
`
`invention” and, instead, “simply makes conclusory assertions that a POSITA
`
`could make the proposed modifications and would have a reasonable
`
`expectation of success in doing so.” Prelim. Resp. 50, 54.
`
`We agree. The embodiment relied upon by Petitioner for this
`
`limitation is different from the embodiment relied upon by Petitioner for
`
`earlier limitations of claim 1. Petitioner does not explain sufficiently why a
`
`person of ordinary skill in the art would have combined the two
`
`embodiments, or otherwise would have modified the first embodiment such
`
`20
`
`
`
`IPR2016-01622
`Patent 6,850,414 B2
`
`that each one of the semiconductor memories, other than the error correction
`
`chip, is oriented parallel with the contact strip. As a result we are not
`
`persuaded that Petitioner has provided an articulated reasoning with some
`
`rational underpinning to support the legal conclusion of obviousness. See
`
`KSR, 550 U.S. 418 (2007) (citing In re Kahn, 441 F.3d 977, 988 (Fed. Cir.
`
`2006)).
`
`On this record, we are not persuaded that Petitioner has established a
`
`reasonable likelihood that it would prevail in showing that claim 1, or claims
`
`2–8 which depend therefrom, would have been obvious over the Intel
`
`Specification.
`
`E. Claims 1–8: Obviousness over
`the Intel Specification and Simpson
`
`Petitioner asserts that the challenged claims are unpatentable under
`
`35 U.S.C. § 103 as obvious over the Intel Specification and Simpson. Pet.
`
`64. This alleged ground, however, consists solely of the following sentence:
`
`“For the same reasons outlined in Subsection X, Subparts A and B, claim 1-
`
`8 of the ’414 patent are rendered obvious by the Intel Specification in view
`
`of Simpson as well. Ex. 1006, Subramanian Decl. at ¶162.”
`
`Because we institute an inter partes review of claims 1 and 5–8 based
`
`on the ground discussed above, we exercise our discretion not to institute a
`
`review based on this ground for reasons of administrative expediency to
`
`ensure timely completion of the instituted proceeding. See 37 C.F.R.
`
`§ 42.108(a) (“the Board may authorize the review to proceed . . . on all or
`
`some of the grounds of unpatentability asserted for each claim”); 35 U.S.C.
`
`§ 314(a) (authorizing institution of an inter partes review under particular
`
`circumstances, but not requiring institution under any circumstances);
`
`21
`
`
`
`IPR2016-01622
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