Trials@uspto.gov
`571-272-7822
`
`
`Paper 33
`Entered: January 29, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2016-01621
`Patent 6,438,057 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, JEAN R. HOMERE, and
`KEN B. BARRETT, Administrative Patent Judges.
`
`HOMERE, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
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`IPR2016-01621
`Patent 6,438,057 B1
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`
`INTRODUCTION
`I.
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`Kingston Technology Company, Inc. (“Petitioner”) challenges claims 1–17
`(“the challenged claims”) of U.S. Patent No. 6,438,057 B1 (Ex. 1001, “the
`’057 patent”), owned by Polaris Innovations Ltd. (“Patent Owner”).1 We
`have jurisdiction under 35 U.S.C. § 6. This Final Written Decision is
`entered pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73. For the
`reasons discussed below, Petitioner has shown by a preponderance of the
`evidence that the challenged claims are unpatentable.
`
`A. Procedural History
`Petitioner filed a Petition requesting an inter partes review of claims
`1‒17 of the ’057 patent. Paper 2 (“Pet.”). Patent Owner filed a Preliminary
`Response. Paper 7 (“Prelim. Resp.”). On February 15, 2017, we instituted
`inter partes review of claims 1, 3, 5–9, 12, 13, and 16 of the ’057 patent
`under 35 U.S.C. § 103(a) as being unpatentable over the combination of
`Atkinson,2 and Broadwater.3 Paper 8 (“Inst. Dec.”), 17. Further, we
`instituted inter partes review of claims 2, 4, 10, 11, 14, 15, and 17 of the
`’057 patent under 35 U.S.C. § 103(a) as being unpatentable over the
`combination of Atkinson, Broadwater, and Miller.4 Id. at 20.
`Thereafter, Patent Owner filed a Patent Owner Response (Paper 18,
`“PO Resp.”), to which Petitioner filed a Reply (Paper 21, “Reply”).
`
`1Patent Owner identifies Polaris Innovations Ltd., Wi-LAN Inc., and
`Quarterhill Inc. as real parties-in-interest. Paper 4, 2; Paper 20, 2.
`2 U.S. Patent No. 6,134,167, issued Oct. 17, 2000 (Ex. 1010) (“Atkinson”).
`3 U.S. Patent No. 4,970,497, issued Nov. 13, 1990 (Ex. 1006)
`(“Broadwater”).
`4 U.S. Patent No. 3,812,717, issued May 28, 1974 (Ex. 1015) (“Miller”).
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`Pursuant to an Order (Paper 22), Patent Owner filed a listing of alleged
`statements and evidence in connection with Petitioner’s Reply that Patent
`Owner considered to be beyond the proper scope of a reply. Paper 23.
`Petitioner filed a response to Patent Owner’s listing. Paper 24.
`We held a consolidated hearing on November 14, 2017, for this case
`and related Cases IPR2016-01622 and IPR2016-01623, and a transcript of
`the hearing is included in the record. Paper 32 (“Tr.”).
`
`B. Related Proceedings
`The parties state that the ’057 patent is the subject of a pending
`lawsuit in the Central District of California Southern Division that includes
`assertions against Petitioner. Pet. 2; Paper 4 (Patent Owner’s Mandatory
`Notice), 1; Ex. 1002.
`
`C. The ’057 patent (Ex. 1001)
`The ʼ057 patent is directed to a method and system for refreshing the
`contents of a dynamic random access memory (DRAM) array. Ex. 1001,
`1:5–7. In particular, the temperature of the DRAM array is utilized to adjust
`a refresh rate at which the contents of the DRAM array are updated. Id. at
`1:7–10. Figure 3 of the ’057 patent is reproduced below:
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`Figure 3 illustrates system 100 for storing data in DRAM array 112.
`Id. at 4:11–12. In particular, Figure 3 depicts memory unit 102 containing
`temperature sensor 110 coupled to DRAM array 112, wherein memory unit
`102 is connected to refresh unit 104 containing temperature processor 120
`coupled to refresh timing 122 and row/column decoders sense amplifiers
`124. Id. at 4:12–30. According to the ’057 patent, “the DRAM array 112
`may be implemented on a semiconductor chip and the temperature sensor
`110 may be thermally coupled to the same semiconductor chip or to an
`intermediate member that is in thermal communication with the
`semiconductor chip.” Id. at 4:22–26.
`More specifically, in system 100 illustrated in Figure 3, upon
`receiving signal 116 from temperature sensor 110 indicating a temperature
`sensed from DRAM array 112, refresh unit 104 produces refresh signal 130
`to refresh DRAM array 112 at a rate that varies in response to received
`temperature signal 116. Id. at 4:30–32. Preferably, DRAM array 112 is
`refreshed at a rate that decreases as the temperature of DRAM array 112
`decreases. Conversely, DRAM array 112 is refreshed at a rate that increases
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`as the temperature of DRAM array 112 increases. Id. at 4:33–37. Further,
`according to the ’057 patent, “the temperature sensor 110 and the DRAM
`array 112 are preferably disposed in a semiconductor package where the
`package includes at least one connection pin 117 operable to provide the
`signal on line 116 to external circuitry, such as the refresh unit 104.” Id. at
`4:49–53. “[T]he temperature sensor 110 preferably includes at least one
`diode 140 having a forward voltage drop that varies as a function of the
`temperature of the DRAM array 112.” Id. at 5:17–20.
`
`D. Illustrative Claim
`Of the instituted claims, claims 1, 13, and 16 are independent. Claims
`2–12 depend from independent claim 1. Claims 14 and 15 depend from
`independent claim 13. Claim 17 depends from independent claim 16.
`Independent claim is illustrative of the challenged claims, and is reproduced
`below:
`1.
`
`An apparatus, comprising:
`a semiconductor package including at least one
`connection pin;
`at least one dynamic random access memory (DRAM)
`array disposed within the package; and
`at least one temperature sensor in thermal communication
`with the DRAM array, operable to produce a signal indicative
`of a temperature of the DRAM array, and coupled to the at least
`one connection pin such that the signal may be provided to
`external circuitry,
`wherein the DRAM array is refreshed at a rate that
`decreases as the temperature of the DRAM array decreases and
`that increases as the temperature of the DRAM array increases.
`Ex. 1001, 5:60–6:7.
`
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`
`II. ANALYSIS
`A. Claim Construction
`The Board interprets claims of an unexpired patent using the broadest
`reasonable construction in light of the specification of the patent in which
`they appear. See 37 C.F.R. § 42.100(b); see Cuozzo Speed Techs., LLC v.
`Lee, 136 S. Ct. 2131, 2142–46 (2016). Under the broadest reasonable
`construction standard, claim terms are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in the
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007).
`In our Decision on Institution, we found no material dispute between
`the parties as to claim construction in the present proceeding. Inst. Dec. 7.
`Patent Owner contends that because Petitioner has not provided in the
`Petition how each of the challenged claims is to be construed, but instead
`advises the Board that the claims are to be construed according to their plain
`and ordinary meaning, Petitioner has failed to demonstrate a scope of the
`claimed invention that permits the Board to apply the asserted references to
`the claims. PO Resp. 13–14. Further, Patent Owner contends Petitioner
`previously argued in the companion district court litigation that the claim
`terms “refresh unit” and “refresh timing unit” in claims 6–11 are means plus
`function recitations with no corresponding structures in the Specification;
`that the cited claim terms are indefinite and cannot be construed. Id. at 16–
`17. According to Patent Owner, Petitioner cannot now request the Board to
`construe those claim terms as anything other than means plus function
`recitations. Id. at 17–18. Patent Owner, therefore, submits that Petitioner
`has failed to meet its burden to demonstrate, with reasonable certainty, the
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`scope of the claims to which the Board is to apply the alleged prior art. Id.
`at 18.
`These arguments are not persuasive. Petitioner was not required to
`make explicit claim constructions for each term of each claim. “It may be
`sufficient for a party to provide a simple statement that the claim terms are
`to be given their broadest reasonable interpretation, as understood by one of
`ordinary skill in the art and consistent with the disclosure.” Office Patent
`Trial Practice Guide, 77 Fed. Reg. 48,756, 48,764 (Aug. 14, 2012). For this
`reason, we disagree with Patent Owner’s contention that Petitioner’s
`statement that the claim terms be given their plain and ordinary meaning is
`insufficient. We also are not persuaded by Patent Owner’s argument that
`Petitioner’s position regarding its proposed claim constructions in the
`District Court for dependent claims 6–11 and prior allegation of
`indefiniteness of the cited claim terms in the district court proceeding “is a
`failure to meet its burden of proof.” PO Resp. 18. We disagree that
`Petitioner’s alleged inconsistent claim construction positions are fatal to
`Petitioner. Moreover, we decline Patent Owner’s invitation to consider on
`the merits Petitioner’s arguments made in the related District Court
`proceeding. PO Resp. 18. Here, neither party proffers an explicit
`construction of, or otherwise disputes the meaning of, any of the claim
`terms. We determine that it is not necessary to provide any express
`interpretation of the claim terms. Only terms that are in controversy need to
`be construed, and then only to the extent necessary to resolve the
`controversy. Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`(Fed. Cir. 1999).
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`B. Level of Ordinary skill in the Art
`
`Both Petitioner’s Declarant, Dr. Vivek Subramanian, and Patent
`Owner’s Declarant, Dr. Joseph Bernstein, contend that a person having
`ordinary skill in the art at the time of the invention would have had (1) a
`Master’s degree in Electrical Engineering, and (2) two to five years of
`experience working in the field of semiconductor design. Ex. 1005 ¶ 17, Ex.
`2008 ¶ 25.
`
`This definition is consistent with the level of ordinary skill reflected in
`the prior art references of record. See Okajima v. Bourdeau, 261 F.3d 1350,
`1355 (Fed. Cir. 2001) (the prior art itself may reflect an appropriate level of
`skill in the art). ; In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In
`re Oelrich, 579 F.2d 86, 91 (CCPA 1978). For purposes of this decision, we
`adopt the undisputed definition of the person of ordinary skill in the art, as
`set forth above.
`
`C. The Parties’ Post-Institution Arguments
`In our Decision on Institution, we concluded that the arguments and
`evidence advanced by Petitioner demonstrated a reasonable likelihood that
`claims 1, 3, 5–9, 12, 13, and 16 of the ’057 patent are unpatentable under
`35 U.S.C. § 103(a) over the combination of Atkinson and Broadwater. Inst.
`Dec. 17. Further, we concluded that the arguments and evidence advanced
`by Petitioner demonstrated a reasonable likelihood that claims 2, 4, 10, 11,
`14, 15, and 17 of the ’057 patent under 35 U.S.C. § 103(a) are unpatentable
`over the combination of Atkinson, Broadwater, and Miller. Id. at 20. We
`must now determine whether Petitioner has established by a preponderance
`of the evidence that the specified claims are unpatentable over the cited prior
`art. 35 U.S.C. § 316(e).
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`
`With a complete record before us, we note that we have reviewed
`arguments and evidence advanced by Petitioner to support its unpatentability
`contentions where Patent Owner chose not to address certain limitations in
`its Patent Owner Response. In this regard, the record now contains
`persuasive, unrebutted arguments and evidence presented by Petitioner
`regarding the manner in which the asserted prior art teaches corresponding
`limitations of the claims against which that prior art is asserted. Based on
`the preponderance of the evidence before us, we conclude that the prior art
`identified by Petitioner teaches or suggests all uncontested limitations of the
`reviewed claims. The limitations of claim 1 and the limitations in the other
`challenged claims that Patent Owner contests in the Patent Owner Response
`are addressed below.
`
`D. Obviousness over the Combination of Atkinson and Broadwater
`Petitioner contends that claims 1, 3, 5–9, 12, 13, and 16 of the ’057
`patent are unpatentable under 35 U.S.C. § 103(a) over the combination of
`Atkinson and Broadwater. Pet. 12–32.
`
`1. Principles of Law
`A claim is unpatentable under § 103(a) if the differences between the
`claimed subject matter and the prior art are such that the subject matter, as a
`whole, would have been obvious at the time the invention was made to a
`person having ordinary skill in the art to which said subject matter pertains.
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of
`obviousness is resolved on the basis of underlying factual determinations,
`including (1) the scope and content of the prior art; (2) any differences
`between the claimed subject matter and the prior art; (3) the level of skill in
`the art; and (4) when in evidence, objective indicia of non-obviousness
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`(i.e., secondary considerations). Graham v. John Deere Co., 383 U.S. 1, 17–
`18 (1966). We analyze this asserted ground based on obviousness with the
`principles identified above in mind.
`
`2. Atkinson Overview
`Atkinson describes a technique for reducing the consumption of
`electric power in the main computer memory. Ex. 1010, 1:16–20. In
`particular, Atkinson discloses a refresh logic device that generates a memory
`refresh signal having a rate, which varies proportionally with the sensed
`temperature of the computer memory. Id. at 5:61–66, 7:41–44.
`Figure 8 of Atkinson is reproduced below.
`
`
`
`As illustrated in Figure 8 of Atkinson, refresh generator 850 includes
`thermistor 800, the temperature of which drops upon sensing a decreased
`temperature of main memory 106 to thereby produce a decrease of the rate
`of the refresh signal. Id. at 22:39–65. “Accordingly, the temperature of
`thermistor 800 represents the temperature of memory storage logic 930, and
`the refresh frequency decreases approximately in proportion to the decrease
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`in the temperature of memory storage logic 930.” Id. at 24:11–17.
`Conversely, when the temperature of thermistor 800 increases upon sensing
`an increased temperature of main memory 106, refresh generator 850
`increases the rate of the refresh signal. Id. at 7:41–44, 21:38–39. Atkinson
`also discloses an alternative embodiment in which refresh generator 950,
`including thermistor 800, is integrated in main memory 906. Id. at 23:37–
`40, 24:11–13, 24:22–23, Fig. 9.
`Atkinson further discloses that that main memory 906 is an alternative
`embodiment of main memory 106 that preferably comprises DRAM
`circuitry (id. at 23:32–34), but may also be other types of DRAM, such as
`synchronous DRAM (SDRAM), extended data output DRAM (EDO RAM),
`and Rambus RAM. Id. at 3:38–46, 9:1–5. Main memory 106 is connected
`to bus 110 to exchange signals therewith. Id. at 12:4–7.
`
`3. Broadwater Overview
`Broadwater relates to a technique for sensing and reducing the effects
`of thermal stress on packaged semiconductor chips. Ex. 1006, 1:6–8,
`Abstract. Figure 1 of Broadwater is reproduced below:
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`As depicted in Figure 1 above, Broadwater describes a chip package
`having thermal stress sensing circuit 6 with input 12 and output 14. Id. at
`3:35–37, 4:31–35. The voltage at output 14 varies as a function of input
`voltage and temperature. Id. at 4:39–41, Fig. 2. Output 14 can be routed to
`gate array 10, as shown, or can be provided to an external pin of the chip
`package. Id. at 4:31–53.
`
`4. Petitioner’s Positions
`Petitioner asserts that the combination of Atkinson and Broadwater
`discloses the elements of claims 1, 3, 5–9, 12, 13, and 16. Pet. 12–32. We
`begin our analysis with claim 1. We have reviewed the Petition, Patent
`Owner Response, and Petitioner’s Reply, as well as the relevant evidence
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`discussed in those papers and other record papers. We are persuaded that
`the record sufficiently establishes Petitioner’s contentions for claims 1, 3, 5–
`9, 12, 13, and 165.
`The preamble of claim 1 recites “an apparatus comprising.” Ex. 1001,
`5:61. Petitioner contends that Atkinson’s description of an apparatus
`containing a main memory with a temperature sensor discloses the preamble
`of claim 1. Pet. 12.
`Claim 1 next recites “a semiconductor package including at least one
`connection pin.” Ex. 1001, 5:62–63. Petitioner contends that Atkinson’s
`description of main memory 106 including any suitable type of memory
`such as DRAM or any of the special types of DRAM devices (e.g., SDRAM,
`EDO DRAM, Rambus DRAM) discloses the “semiconductor package”
`because “[o]ne of ordinary skill in the art would know that SDRAM and
`Rambus DRAM are packaged semiconductor chips.” Pet. 13 (citing Ex.
`1005 ¶ 41; Ex. 1007, 524; Ex. 1010, 4:31–35, 8:65–9:5). Further, Petitioner
`asserts that Atkinson’s description of main memory 106’s connection to bus
`110 discloses the “connection pin” because one of ordinary skill would
`appreciate that “[a]s the main memory is composed of packaged memory
`chips that receive a variety of memory bus signals,” its “connections to the
`memory bus 110 would necessarily require at least one connection pin or it
`would be obvious to have one.” Id. at 13–14 (citing Ex. 1010, 12:4–7,
`
`
`5 We acknowledge Patent Owner’s argument that “Dr. Subramanian’s
`opinions on the ultimate question of obviousness are entitled to no weight”
`because he is not an attorney. PO Response 28–30. We arrive at the
`ultimate conclusion regarding obviousness independently and without
`adopting any purported “lay opinions” on the ultimate issue, id. at 28–29.
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`23:32–37, 12:8–12; Ex. 1005 ¶ 42). We are persuaded by Petitioner’s
`showing and find that Atkinson’s main memory 106 teaches a packaged
`semiconductor chip including at least one connection pin.
`Claim 1 also recites “at least one dynamic random access memory
`(DRAM) array disposed within the package.” Ex. 1001, 5:64–65. Petitioner
`asserts that Atkinson’s description of a “computer system where the main
`memory 106 includes an array of memory devices such as DRAM” discloses
`the “package” having disposed therein the DRAM array. Pet. 14 (citing Ex.
`1010, Figs. 1, 4A, 5, 7–9, 5:57–62, 8:37–9:15; Ex. 1005 ¶ 43). We are
`persuaded by Petitioner’s showing and find that Atkinson’s description of
`the main memory packaged in the semiconductor chip teaches a dynamic
`random access memory.
`Claim 1 further recites “at least one temperature sensor in thermal
`communication with the DRAM array, operable to produce a signal
`indicative of a temperature of the DRAM array.” Ex. 1001, 5:66–6:1.
`Petitioner asserts Atkinson’s description of refresh generator 850, including
`thermistor 800 that directly senses the temperature of the DRAM, discloses
`“the temperature sensor . . . in thermal communication with the DRAM
`array.” Pet. 14–16 (citing Ex. 1010, 22:52–62, 22:39–67, 23:32–37, 24:1–
`26, Fig. 8; Ex. 1005 ¶¶ 44, 45). Further, Petitioner asserts Atkinson
`describes an alternate embodiment wherein a “voltage controlled oscillator
`[(VCO)] combined with a temperature sensor could replace the refresh
`generator,” such that “the temperature sensor couples to main memory 106,
`providing a voltage to the VCO that represents the main memory
`temperature.” Id. at 16 (citing Ex. 1010, 23:5–19). The refresh signal
`produced by the VCO varies with the temperature of the memory device as
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`sensed by the temperature sensor. Id. at 16–17 (citing Ex. 1010, 6:46–62,
`7:46–48). We are persuaded by Petitioner’s showing and find that
`Atkinson’s description of the refresh generator, and alternatively the voltage
`controlled oscillator combined with the temperature sensor, teaches a sensor
`coupled to the DRAM array to indicate the temperature of the DRAM array.
`Claim 1 also recites “coupled to the at least one connection pin such
`that the signal may be provided to external circuitry.” Ex. 1001, 6:2–3.
`Petitioner asserts that Atkinson describes an on-chip embodiment wherein a
`temperature sensor coupled directly to main memory 106 provides a voltage
`to the VCO that represents the main memory temperature. Pet. 17 (citing
`Ex. 1010, 23:15–17, Fig. 8; Ex. 1005 ¶ 47). According to Petitioner, while
`the on-chip embodiment described by Atkinson does not disclose providing
`the temperature signal to an external circuit, such a modification would have
`been obvious to one of ordinary skill in the art, particularly in view of
`Broadwater’s disclosure of an external pin of a chip package (e.g., DRAM
`memory chip) for outputting a signal indicative of the chip’s temperature.
`Id. (citing Ex. 1005 ¶¶ 47–49); id. at 30 (citing Ex. 1006, 4:31–33, 4:49–53;
`Ex. 1005 ¶¶ 83–84).
`Further, Petitioner asserts that the ordinarily skilled artisan would
`have been motivated to combine the cited disclosures of Atkinson and
`Broadwater because Broadwater’s disclosure of adding an external pin to an
`existing chip package (e.g., Atkinson’s DRAM) would help reduce the
`effects of thermal stress on the DRAM. Id. at 31 (citing Ex. 1006, 1:14–29;
`Ex. 1005 ¶ 85). Additionally, Petitioner concludes that the ordinarily skilled
`artisan would have recognized that the proposed combination would help
`maximize power saving during the self-refresh timing sequence. Id. (citing
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`Ex 1005 ¶ 86). We are persuaded that a person having ordinary skill in the
`art would have found it obvious to combine the teachings of Atkinson and
`Broadwater because we agree that transmitting the sensed temperature of the
`DRAM to an external circuit via an external pin would have been recognized
`by a person having ordinary skill in the art as resulting in a more efficient
`system that maximizes power saving by reducing thermal stress on the
`packaged semiconductor chip.
`Claim 1 also recites “wherein the DRAM array is refreshed at a rate
`that decreases as the temperature of the DRAM array decreases and that
`increases as the temperature of the DRAM array increases.” Ex. 1001, 6:4–
`7. Petitioner asserts Atkinson describes a refresh logic that reduces the rate
`of the refresh signal in response to receiving a signal from the temperature
`sensor indicating a drop in the main memory temperature. Pet. 19 (citing
`Ex. 1010, 13:13–15, 22:2–7). Conversely, the refresh logic increases the
`rate of the refresh signal in response to receiving a signal indicating an
`increase in the temperature of the main memory. Id. (citing Ex. 1010, 7:41–
`44; Ex. 1005 ¶¶ 50–51). According to Petitioner, the refresh frequency
`increases or decreases in proportion to the increase or decrease in the
`temperature of the DRAM as a way to achieve the greatest power savings.
`Id. (citing Ex. 1010, 20:53–56, 24:3–17, Fig. 6; Ex. 1005 ¶ 51). We are
`persuaded by Petitioner’s showing and find that Atkinson’s description of
`the refresh logic teaches a mechanism for providing to the DRAM an
`increased or decreased refresh rate in proportion with the sensed temperature
`of the DRAM.
`Independent claims 13 and 16 are similar to claim 1. Petitioner has
`made a showing with respect to claims 13 and 16 similar to its showing with
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`respect to claim 1. See, e.g., Pet. 26–28. To the extent that claims 13 and 16
`are different from claim 1, Petitioner has accounted for such differences.
`We also have reviewed Petitioner’s showing with respect to dependent
`claims 3, 5–9, and 12. Id. at 21, 23–26. Notwithstanding Patent Owner’s
`arguments, which we have considered and which we address below, we are
`persuaded by Petitioner’s showing, which we adopt as our own findings and
`conclusions, as set forth above, that claims 1, 3, 5–9, 12, 13, and 16 are
`unpatentable as obvious over the combination of Atkinson and Broadwater.
`
`5. Patent Owner’s Assertions
`Concerning the References
`Patent Owner argues that the challenged claims would not have been
`obvious over the combination of Atkinson and Broadwater for the following
`reasons: (a) “Petitioner does not demonstrate a proper motivation to modify
`Atkinson to add Broadwater’s ‘connection pin’ to provide a temperature
`indicative signal to ‘external circuitry,’” as recited in challenged claims 1–17
`(PO Resp. 32–53 (emphasis omitted)); (b) “Petitioner has failed to show it
`was obvious to modify Atkinson to add the ‘diode’ limitations,” as recited in
`dependent claims 2, 4, 10, 11, 14, and 15 (id. at 19–27, 53–57 (emphasis
`omitted)); and (c) “Petitioner has failed to point out where the ‘refresh unit’ .
`. . and ‘refresh timing unit’ . . . limitations are found,” as recited in
`dependent claims 6–11, and 7–11 respectively (id. at 57–60). We address
`each argument in turn.6
`
`6 Patent Owner lists several portions of Petitioner’s Reply and evidence as
`being allegedly beyond the scope of what can be considered appropriate for
`a reply. See Paper 23. We have considered Patent Owner’s listing, but
`disagree that the cited portions of Petitioner’s Reply and reply evidence are
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`a. The Allegation that Petitioner Does Not Demonstrate a Proper Reason to
`Modify Atkinson to Add Broadwater’s “Connection Pin” to Provide a
`Temperature Indicative Signal to “External Circuitry” (claims 1–17)
`Independent claim 1 recites, in relevant part, “at least one connection
`pin such that the signal may be provided to external circuitry.” Independent
`claim 13 recites, in relevant part, “at least one connection pin operable to
`provide the signal to external circuitry.” Independent claim 16 recites, in
`relevant part, “outputting a signal indicative of the temperature of the
`DRAM array to external circuitry.” Patent Owner presents four sub-
`arguments: (i) “The teachings of Atkinson and Broadwater discourage the
`combination” (PO Resp. 37–42 (emphasis omitted)); (ii) “Even if Atkinson
`and Broadwater were not contrary to the Patent’s teaching, there is no reason
`to combine them to make the specific invention claimed” (id. at 42–47
`(emphasis omitted)); (iii) “The proposed Atkinson-Broadwater combination
`would require extensive modifications of Atkinson to practice the claims”
`(id. at 48–50 (emphasis omitted)); and (iv) “Petitioner and its declarant wave
`aside the references’ disclosures and rely on generalities and offhand
`
`
`beyond the scope of what is appropriate for a reply. Replies are a vehicle for
`responding to arguments raised in a corresponding patent owner response.
`Petitioner’s arguments and evidence that Patent Owner objects to (id. at 1)
`are not beyond the proper scope of a reply because we find that they fairly
`respond to Patent Owner’s arguments raised in Patent Owner’s Response.
`See Idemitsu Kosan Co., Ltd. v. SFC Co. Ltd., 870 F.3d 1376, 1381 (Fed.
`Cir. 2017) (“This back-and-forth shows that what Idemitsu characterizes as
`an argument raised ‘too late’ is simply the by-product of one party
`necessarily getting the last word. If anything, Idemitsu is the party that first
`raised this issue, by arguing—at least implicitly—that Arakane teaches away
`from non-energy-gap combinations. SFC simply countered, as it was
`entitled to do.”).
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`comments in each reference” (id. at 50–53 (emphasis omitted)). We address
`each in turn.
`
`i. Whether the teachings of Atkinson and Broadwater
`Discourage the Combination.
`Patent Owner argues that “[t]here is no motivation to couple
`Atkinson’s onboard sensor to a connection pin such that the temperature
`indicative signal may be provided to external circuitry, because in Atkinson
`all external circuitry, particularly any that might affect the DRAM refresh
`rate, is expressly turned off.” PO Resp. 37 (citing Ex. 1010, 4:54–59, 6:6–
`10, 11:4–16). Specifically, Patent Owner argues that every embodiment
`disclosed in Atkinson is focused on performing the refresh operation during
`system sleep with all external logic/circuitry outside of the DRAM module
`off. Id. According to Patent Owner, modifying Atkinson’s onboard module
`in its sleep state (during which the rate of temperature decreases to control
`the DRAM refresh rate) to operate with an external circuitry in active state,
`would go against the thrust of Atkinson. Id. (citing Ex. 2008 ¶ 60). Patent
`Owner stresses that Atkinson’s “on-chip” embodiment with the temperature
`sensor in thermal communication with the array was designed to be self-
`contained to include the temperature sensing refresh generator within main
`memory 906. Id. at 38 (citing Ex. 1010, 24:22– 23, 24:23–27; Ex. 2008 ¶
`61). Further, Patent Owner argues that the “on-chip” embodiment does not
`include a connection pin to provide a signal indicative of the DRAM
`temperature to an external circuit because, in response to the temperature, it
`generates internally a refresh pulse, which does not provide meaningful data
`based on the temperature sensor by a pin to an external circuitry. Id. (citing
`Ex. 1010, Fig. 8, 22:38–23:1). Furthermore, Patent Owner argues that
`adding components to Atkinson’s “on-chip” embodiment with its on-board
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`components would have increased the price, size, and complexity of the unit.
`Id. at 39 (citing Bernstein ¶ 63). Additionally, Patent Owner argues that
`Broadwater is not related to memory, DRAM or refresh, and offers no
`tradeoffs or incentives for additional on-board circuitry or pins for which the
`solution is to reduce or cutoff circuit activity (as opposed to increasing
`circuit activity). Id. at 39–40 (citing Ex. 1006, 5:18–32). According to
`Patent Owner, Broadwater is concerned with combatting thermal stress from
`operating temperatures during operation. Id. at 40 (citing Ex. 1006, 1:30–
`51, 4:66–5:1). In Patent Owner’s words, “while Atkinson is on, Broadwater
`is off, and vice versa.” Id. (citing Ex. 2008 ¶¶ 63–66). Patent Owner argues
`that Atkinson and Broadwater are directed to very different applications. In
`particular, Atkinson is directed to making power use more efficient in
`laptops during system sleep, whereas Broadwater is directed to protecting
`mission critical circuitry in high speed aircraft. Id. (citing Ex. 1010, 3:6–28;
`Ex. 1006, 1:25–31).
`Moreover, Patent Owner argues that although both Atkinson and
`Broadwater are focused on power efficiency, they do so by reducing circuit
`activity, whereas the ’057 patent reduces waste of energy by increasing
`circuit activity. Id. at 40–41. That is, Atkinson prevents waste of energy by
`dropping circuit activity from a default level when the temperature drops,
`and Broadwater prevents waste of energy by dropping circuit activity from a
`default level when the temperature increases. Id. at 41 (citing Ex. 1010,
`13:11–18; Ex. 1005, 5:18–27). In contrast, Patent Owner stresses that the
`’057 patent prevents waste of energy and failure by increasing circuit
`activity from a default level when the temperature increases. Id. (citing Ex.
`1001, 3:55–66; Ex. 2008 ¶¶ 69–70). Therefore, Patent Owner submits that
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`both Atkinson and Broadwater disclose cutting the temperature of the
`circuits, whereas the ’057 patent teaches increasing the circuitry temperature
`most when it is at its hottest. Id. (citing Ex. 1006, 5:18–27; Ex. 1010,
`13:11–18;, Ex. 1001, 2:34–36, 3:55–58; Ex. 2008 ¶ 71).