PRELIMINARY
`
`Am79C971
`PCnet™-FAST
`Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
`
`DISTINCTIVE CHARACTERISTICS
`n Single-chip Fast Ethernet controller for the
`Peripheral Component Interconnect (PCI) local
`bus
`— 32-bit glueless PCI host interface
`— Supports PCI clock frequency from DC to 33 MHz
`independent of network clock
`— Supports network operation with PCI clock from
`15 MHz to 33 MHz
`— High performance bus mastering architecture
`with integrated Direct Memory Access (DMA)
`Buffer Management Unit for low CPU and bus
`utilization
`— PCI specification revision 2.1 compliant
`— Supports PCI Subsystem/Subvendor ID/Vendor
`ID programming through the EEPROM interface
`— Supports both PCI 5.0-V and 3.3-V signaling
`environments
`— Plug and Play compatible
`— Supports an unlimited PCI burst length
`— Big endian and little endian byte alignments
`supported
`
`n Integrated 10BASE-T and 10BASE-2/5 (AUI)
`Physical Layer Interface
`— Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3
`and Blue Book Ethernet-compliant solution
`— Automatic Twisted-Pair receive polarity detection
`and correction
`— Internal 10BASE-T transceiver with Smart
`Squelch to Twisted-Pair medium
`— IEEE 802.3 and N-Way-compliant
`auto-negotiable 10BASE-T interface
`n Supports General Purpose Serial Interface
`(GPSI)
`n Media Independent Interface (MII) for connecting
`external 10- or 100-Megabit per second (Mbps)
`transceivers
`— IEEE 802.3-compliant MII
`— Intelligent Auto-Poll™ external PHY status
`monitor and interrupt
`
`— Includes intelligent on-chip Network Port Manag-
`er that provides auto-port selection between MII,
`on-chip 10BASE-T port, and AUI without soft-
`ware support
`— Supports both auto-negotiable and non
`auto-negotiable external PHYs
`— Supports 10BASE-T, 100BASE-TX/FX,
`100BASE-T4, 100BASE-T2, and any future IEEE
`802.3-compliant MII PHYs at full- or half-duplex
`n Internal/external loopback capabilities on all
`ports
`n Supports patented External Address Detection
`Interface (EADI)
`— Receive frame tagging support for inter-
`networking applications
`n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
`Media Access Controller (MAC) compliant with
`IEEE/ANSI 802.3 and Blue Book Ethernet
`standards
`n Full-duplex operation supported in AUI,
`10BASE-T, MII, and GPSI ports with independent
`Transmit (TX) and Receive (RX) channels
`n Flexible buffer architecture
`— Large independent internal TX and RX FIFOs
`— SRAM-based FIFO buffer extension supporting
`up to 128 kilobytes (Kbytes)
`— 1/2 Gigabit per second (Gbps) internal data
`bandwidth
`— Programmable FIFO watermarks for both TX and
`RX operations
`— RX frame queuing for high latency PCI bus host
`operation
`— Programmable allocation of buffer space
`between RX and TX queues
`n Extensive LED status support
`n EEPROM interface supports jumperless design
`and provides through-chip programming
`— Supports full programmability of half-/full-duplex
`operation for external 100 Mbps PHYs through
`EEPROM mapping
`
`This document contains information on a product under development at Advanced Micro Devices. The information
`is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
`product without notice.
`
`Publication# 20550 Rev: B Amendment/0
`Issue Date: May 1996
`
`Page 1
`
` Dell Inc.
` Exhibit 1019
`
`

`
`
`
`P R E L I M I N A R Y
`
`n Supports optional Boot PROM and 1 Megabyte
`(Mbyte) Flash for diskless node application
`n Look-Ahead Packet Processing (LAPP) data
`handling technique reduces system overhead by
`allowing protocol analysis to begin before the
`end of a receive frame
`n Includes Programmable Inter Packet Gap (IPG)
`to address less network aggressive MAC
`controllers
`n Offers the Modified Back-Off algorithm to
`address the Ethernet Capture Effect
`n IEEE 1149.1-compliant JTAG Boundary Scan test
`access port interface and NAND tree test mode
`for board-level production connectivity test
`
`GENERAL DESCRIPTION
`The Am79C971 controller is a single-chip 32-bit full-
`duplex, 10/100-Megabit per second (Mbps) highly-
`integrated Ethernet system solution, designed to
`address high-performance system application require-
`ments. It is a flexible bus mastering device that can be
`used in any application, including network-ready PCs
`and bridge/router designs. The bus master architecture
`provides high data throughput in the system and low
`CPU and system bus utilization. The Am79C971 con-
`troller is fabricated with AMD’s advanced low-power
`Complementary Metal Oxide Semiconductor (CMOS)
`process to provide low operating and standby current
`for power sensitive applications.
`
`The Am79C971 controller is a complete Ethernet node
`integrated into a single VLSI device. It contains a bus
`interface unit, a Direct Memory Access (DMA) Buffer
`Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)-
`compliant Media Access Controller (MAC), a large
`Transmit FIFO and a large Receive FIFO, optional
`SRAM-based FIFO extension with support for up to
`128K bytes of external frame buffering, an IEEE 802.3u-
`compliant MII, an IEEE 802.3-compliant Twisted-Pair
`Transceiver Media Attachment Unit (10BASE-T MAU),
`and an IEEE 802.3-compliant Attachment Unit Interface
`(AUI). Both proprietary full-duplex and IEEE 802.3 com-
`pliant half-duplex operation are supported on the MII,
`AUI, GPSI, and 10BASE-T MAU interfaces. 10-Mbps
`operation is supported through the MII, AUI, and
`10BASE-T MAU interfaces, and 100 Mbps operation is
`supported through the MII. The 10BASE-T MAU inter-
`face includes an IEEE 802.3-compliant auto-negotia-
`tion implementation, which will automatically negotiate
`between half- and full-duplex with another IEEE 802.3-
`compliant auto-negotiation 10BASE-T device.
`
`The Am79C971 controller is register compatible with
`the LANCE (Am7990) Ethernet controller, the C-LANCE
`(Am79C90) Ethernet controller, and all Ethernet con-
`trollers in the PCnet Family (except ILACC (Am79C900)),
`
`n Implements low-power management for critical
`battery powered application and green PCs
`— Includes two power-saving sleep modes
`(sleep and snooze)
`— Integrated Magic Packet™ technology support
`for remote power of networked PCs
`n Software compatible with AMD PCnet Family and
`LANCE/C-LANCE register and descriptor
`architecture
`n Compatible with the existing PCnet Family
`driver/diagnostic software
`n 160-pin PQFP package
`
`(Am79C960),
`the PCnet-ISA controller
`including
`PCnet-ISA+ controller (Am79C961), PCnet-ISA II con-
`troller (Am79C961A), PCnet-32 controller (Am79C965),
`PCnet-PCI controller (Am79C970), and PCnet-PCI II
`controller (Am79C970A). The Buffer Management Unit
`supports the LANCE and PCnet descriptor software
`models.
`
`The 32-bit multiplexed bus interface unit provides a
`direct interface to the PCI local bus, simplifying the
`design of an Ethernet node in a PC system. The
`Am79C971 controller provides the complete interface
`to an Expansion ROM or Flash device allowing add-on
`card designs with only a single load per PCI bus inter-
`face pin. With its built-in support for both little and big
`endian byte alignment, this controller also addresses
`non-PC applications. The Am79C971 controller’s ad-
`vanced CMOS design allows the bus interface to be
`connected to either a +5-V or a +3.3-V signaling envi-
`ronment. A compliant IEEE 1149.1 JTAG test interface
`for board-level testing is also provided, as well as a
`NAND tree test structure for those systems that cannot
`support the JTAG interface.
`
`The Am79C971 controller supports auto-configuration
`in the PCI configuration space. Additional Am79C971
`controller configuration parameters,
`including
`the
`unique IEEE physical address, can be read from an
`external nonvolatile memory (EEPROM) immediately
`following system reset.
`
`encoder/decoder
`integrated Manchester
`The
`(MENDEC) eliminates the need for an external Serial
`Interface Adapter (SIA) in the system. The built-in GPSI
`allows the MENDEC to be bypassed.
`
`In addition, the device provides programmable on-chip
`LED drivers for transmit, receive, collision, receive
`polarity, link integrity, activity, link active, or jabber
`status. The Am79C971 controller also provides an
`EADI to allow external hardware address filtering in
`
`2
`
`Am79C971
`
`Page 2
`
`

`
`
`
`P R E L I M I N A R Y
`
`internetworking applications and a receive frame
`tagging feature.
`
`For power sensitive applications where low standby cur-
`rent is desired, the device incorporates two sleep func-
`tions to reduce overall system power consumption,
`excellent for notebooks and green PCs. In conjunction
`with these low power modes, the PCnet-FAST controller
`also has integrated functions to support Magic Packet
`technology, an inexpensive technology that allows re-
`mote wake up of green PCs.
`
`The controller has the capability to automatically select
`either the MII, AUI, or Twisted-Pair transceiver. Only one
`interface is active at any one time. Any of the network
`interfaces can be programmed to operate in either half-
`duplex or full-duplex mode (AUI full-duplex only sup-
`ports the 10BASE-F standard).
`
`The dual Transmit and Receive FIFOs optimize system
`overhead, providing sufficient latency tolerance at
`10 Mbps and for 100-Mbps systems where low laten-
`cies can be guaranteed during frame transmission and
`reception.
`
`In highly loaded 10-Mbps systems, such as servers or
`when using the controller in a 100-Mbps environment,
`the additional frame buffering capability provided by a
`16-bit wide SRAM interface provides high performance
`and high latency tolerance on the system bus and net-
`work.
`
`The Am79C971 controller can use up to 128 Kbytes of
`SRAM as an extension of its dual Transmit and Receive
`FIFOs. When no SRAM is used, the Am79C971 con-
`troller’s FIFOs are programmed to bypass the SRAM
`interface.
`
`ISO/IEC 8802-3 and IEEE 802.3 will be used inter-
`changeably when referring to half-duplex 10 Mbps net-
`works. IEEE 802.3 or IEEE 802.3u will be used
`interchangeably only when referring to half-duplex 100-
`Mbps Ethernet networks, since the IEEE standard is not
`ISO approved yet. Full-duplex is a proprietary standard
`and is not approved by IEEE or ISO.
`
`Am79C971
`
`3
`
`Page 3
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`

`
`
`
`P R E L I M I N A R Y
`
`ORDERING INFORMATION
`Standard Products
`
`AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
`formed by a combination of the elements below.
`
`Am79C971
`
`K
`
`C
`
`\W
`
`ALTERNATE PACKAGING OPTION
`\W = Trimmed and formed in a tray
`
`TEMPERATURE RANGE
`C = Commercial (0(cid:176) C to +70(cid:176) C)
`
`PACKAGE TYPE
`K = Plastic Quad Flat Pack (PQR160)
`
`SPEED OPTION
`Not applicable
`
`DEVICE NUMBER/DESCRIPTION
`Am79C971
`Single-Chip Full-Duplex 10/100 Mbps Ethernet
`Controller for PCI Local Bus
`
`Valid Combinations
`
`Am79C971
`
`KC\W
`
`Valid Combinations
`Valid Combinations list configurations planned to be
`supported in volume for this device. Consult the local
`AMD sales office to confirm availability of specific
`valid combinations and to check on newly released
`combinations.
`
`4
`
`Am79C971
`
`Page 4
`
`

`
`
`
`BLOCK DIAGRAM
`
`P R E L I M I N A R Y
`
`CLK
`RST
`AD[31:00]
`C/BE[3:0]
`PAR
`FRAME
`TRDY
`IRDY
`STOP
`IDSEL
`DEVSEL
`REQ
`GNT
`PERR
`SERR
`INTA
`SLEEP
`
`Expansion Bus Interface
`
`PCI Bus
`Interface
`Unit
`
`Bus(cid:13)
`Rcv(cid:13)
`FIFO
`
`Bus(cid:13)
`Xmt(cid:13)
`FIFO
`
`Buffer
`Management(cid:13)
`Unit
`
`FIFO
`Control
`
`MAC
`Rcv(cid:13)
`FIFO
`
`MAC
`Xmt(cid:13)
`FIFO
`
`Network
`Port
`Manager
`
`Auto
`Negotiation
`
`TCK
`TMS
`TDI
`TDO
`
`JTAG
`Port
`Control
`
`EBUA_EBA[7:0]
`EBDA[15:8]
`EBD[7:0]
`EROMCS
`ERAMCS
`AS_EBOE
`EBWE
`EBCLK
`
`GPSI
`Port
`
`MII(cid:13)
`Port
`
`EADI
`Port
`
`802.3
`MAC
`Core
`
`Manchester(cid:13)
`Encoder/
`Decoder
`(PLS) & (cid:13)
`AUI Port
`
`10BASE-T
`MAU
`
`93C46(cid:13)
`EEPROM
`Interface
`
`LED
`Control
`
`TXEN
`TXCLK
`TXDAT
`RXEN
`RXCLK
`RXDAT
`CLSN
`TX_ER
`TXD[3:0]
`TX_EN
`TX_CLK
`COL
`RXD[3:0]
`RX_ER
`RX_CLK
`RX_DV
`CRS
`MDC
`MDIO
`SRDCLK
`SRD
`SF/BD
`EAR
`RXFRTGD/MIIRXFRTGD
`RXFRTGE/MIIRXFRTGE
`
`XTAL1
`XTAL2
`DO+/-
`DI+/-
`CI+/-
`
`TXD+/-
`TXP+/-
`RXD+/-
`
`EECS
`EESK
`EEDI
`EEDO
`
`LED0
`LED1
`LED2
`LED3
`
`20550B-1
`
`Am79C971
`
`5
`
`Page 5
`
`(cid:13)
`

`
`
`
`P R E L I M I N A R Y
`
`TABLE OF CONTENTS
`DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
`GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
`ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
`Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
`BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
`RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`CONNECTION DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
`PIN DESIGNATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
`Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
`Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
`PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
`Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
`EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
`Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
`Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
`Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
`External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
`IEEE 1149.1 (1990) Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
`System Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
`Software Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
`Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
`DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Slave Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Slave I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Expansion ROM Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
`Slave Cycle Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
`Disconnect When Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
`Disconnect Of Burst Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
`Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
`Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
`Bus Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
`Bus Master DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`Basic Non-Burst Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`Basic Burst Read Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`Basic Non-Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
`Basic Burst Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
`Target Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
`Disconnect With Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
`Disconnect Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
`Target Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
`Master Initiated Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
`Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
`Preemption During Burst Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
`Master Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
`Parity Error Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
`Advanced Parity Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
`Initialization Block DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`
`6
`
`Am79C971
`
`Page 6
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`

`
`
`
`P R E L I M I N A R Y
`
`Descriptor DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
`FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`Non-Burst FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
`Burst FIFO DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
`Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
`Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
`Re-Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
`Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
`Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`Descriptor Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`Transmit Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`Receive Descriptor Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`Receive Frame Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Transmit and Receive Message Data Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Destination Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
`Medium Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
`Collision Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
`Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
`Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`Loss of Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`Late Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
`SQE Test Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`Address Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
`Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
`Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
`Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
`GPSI Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
`AUI Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
`T-MAU Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
`Media Independent Interface Loopback Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
`Miscellaneous Loopback Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`Manchester Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`External Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`External Clock Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Transmitter Timing and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Receiver Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Clock Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`PLL Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Carrier Tracking and End of Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Data Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`Jitter Tolerance Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`Attachment Unit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`Differential Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
`Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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`Twisted-Pair Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`Twisted-Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`Twisted-Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
`Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Twisted-Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Collision Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Signal Quality Error Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
`10BASE-T Interface Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`Full-Duplex Link Status LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`MII Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`MII Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
`MII Network Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
`MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
`MII Management Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
`Auto-Poll External PHY Status Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
`Network Port Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
`Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
`Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
`Automatic Network Selection: Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
`Automatic Network Selection: External PHY Not Present . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
`Automatic Network Selection: External PHY Present but Not Auto-Negotiable . . . . . . . . . . 82
`Automatic Network Selection: External PHY Present and Auto-Negotiable . . . . . . . . . . . . . 83
`Automatic Network Selection: Working with the Micro Linear 6692 . . . . . . . . . . . . . . . . . . . 83
`Automatic Network Selection: Force External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`External Address Detection Interface: Internal PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`External Address Detection Interface: External PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
`External Address Detection Interface: Receive Frame Tagging . . . . . . . . . . . . . . . . . . . . . . 85
`Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
`Expansion ROM—Boot Device Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
`Direct Flash Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
`Flash/EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
`AMD Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
`SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
`External SRAM Configuration . . . . . . . . . . . . . . . .