Am79C971
`
`
`PCnet™-FAST
`Hardware User’s Manual
`
`AMX
`Exhibit 1035-00001
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`

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`CHAPTER
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`1
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`1.1
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`INTRODUCTION
`
`INTRODUCTION
`The PCnet™-FAST board is an advanced PC network interface adapter card targeted for
`
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`
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`the Ethernet-PCI adapter card market. It is based on the Am79C971 PCnet-FAST device,
`a single-chip 32-bit full-duplex, 10/100-Mbps highly integrated Ethernet system solution.
`Designed to address high performance system applications, the flexible bus master archi-
`tecture provides high data throughput in the system and low CPU and system bus utilization.
`
`FAST board supports the PCI Specification (Rev. 2.1), jumperless bus and
`The PCnet-
`media configuration, and driver software compatible with the existing PCnet family of driv-
`ers.
`
`This manual provides a complete description of the PCnet-
`FAST board, with sections
`
`covering the functional description of each building block, the setup and installation of the
`board, and the hardware specification.
`
`It is assumed that the user of this manual has access to the information listed below, since
`references to these documents are made throughout this manual:
`
`n
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`n
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`n
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`n
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`AMD Ethernet/IEEE 802.3 Family, 1994 World Network Data Book/Handbook
`(PID# 14287).
`Am79C971 PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for
`
`
`PCI Local Bus Preliminary Data Sheet (PID# 20550B)
`PCnet Family Network Family Driver Installation Guide (PID# 18233D)
`PCI Specification, Revision 2.1
`
`Publication# 20963 Rev: A Amendment/0
`Issue Date: July 1996
`
`AMX
`Exhibit 1035-00002
`
`

`
`
`
`1-2
`
`Introduction
`Introduction
`
`AMX
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`Exhibit 1035-00003
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`AMX
`Exhibit 1035-00003
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`CHAPTER
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`2
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`2.1
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`FUNCTIONAL DESCRIPTION
`
`BOARD DESCRIPTION
`
`
`The PCnet-FAST board is a 10/100-Mbps PCI network interface card. The Ethernet con-
`nection is implemented through the single RJ-45 jack which is connected to an external
`
`
`10/100 TX transceiver. The transceiver is connected to the PCnet-FAST controller through
`the integrated Media Independent Interface (MII). Due to the high integration of the PCnet-
`
`
`
`FAST device, very few external parts are needed. The PCnet-FAST evaluation board pro-
`vides the remote boot capability via an EPROM on the FLASH device. In addition, SRAMs
`may be added to optimize performance. In most applications, two 15-ns 32x8 SRAMs are
`sufficient to satisfy the buffer requirement.
`
`
`The following diagram illustrates the implementation of the PCnet-
`
`FAST board.
`
`OSC
`
`10/100
`PHY
`
`SRAM
`
`EPROM
`
`SRAM
`
`Am79C971
`PCnet-FAST
`
`Crystal
`
`EEPROM
`
`Transformer
`
`LEDs
`
`RJ-45
`
`20963A-1
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`Figure 2-1 Board Diagram
`
`2.2
`
`ETHERNET NODE CONTROLLER
`
`
`The single-chip Am79C971 PCnet-FAST Ethernet solution is a highly integrated solution
`that contains a Bus Interface Unit (BIU), a DMA buffer management unit, an ISO/IEC
`8802-3 and ANSI/IEEE 802.3-compliant Media Access Control (MAC) function, a flexible
`buffer architecture with an SRAM-based FIFO extension for support up to 128 Kbytes of
`external frame buffering, optional remote boot PROM/FLASH, integrated 10BASE-T and
`10BASE-2/5 (AUI) physical layer interface, and an ANSI/IEEE 802.3-compliant Media In-
`dependent Interface (MII).
`
`Functional Description
`
`2-1
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`AMX
`Exhibit 1035-00004
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`2.3
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`2.4
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`2.5
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`2.6
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`2.7
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`2.8
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`LOCAL BUS INTERFACE
`
`
`The PCnet-FAST board implements the local bus interface to the Peripheral Components
`Interconnect (PCI) revision 2.1 specification through the Am79C971 chip. The BIU in the
`chip is designed to operate as a PCI bus master during normal operations, and some slave
`I/O accesses to the controller are required in normal operation as well. Initialization of the
`Ethernet controller is achieved through a combination of PCI Configuration Space ac-
`cesses, bus slave accesses, bus master accesses, and an optional read of a serial EE-
`PROM that is performed by the controller.
`ETHERNET INTERFACE
`The Ethernet interface for the PCnet-FAST board is achieved through the single RJ-45
`
`
`jack. The RJ-45 jack is connected to an external 10/100-Mbps transceiver connected to
`
`FAST controller through the integrated MII.
`the PCnet-
`EXPANSION BOOT ROM/FLASH
`
`
`The PCnet-FAST board can accommodate up to 256K bits of Boot ROM Code. An external
`latch is used to allow Boot ROM Address and Data Latching when AS_EBOE is asserted.
`
`FAST board supports EPROM or Flash as an Expansion boot ROM device.
`The PCnet-
`Both are configured using the same methods and operate the same way.
`SRAM INTERFACE
`When using the controller in a 100-Mbps environment, additional frame buffering capability
`is provided by a 16-bit wide SRAM interface which provides high performance and high
`latency tolerance on the system bus and network. The controller can use up to 128 Kbytes
`of SRAM as an extension of its dual transmit and receive FIFOs. When no SRAM is used,
`the Am79C971 controller’s FIFOs are programmed to bypass the SRAM interface.
`SERIAL EEPROM INTERFACE
`
`
`The PCnet-FAST board stores the unique IEEE physical address and bus configuration of
`each node in the serial EEPROM. Once powered up, the Am79C971 chip automatically
`detects the presence of the EEPROM and reads the 32 words stored in it through the Mi-
`croWire interface protocol. For details of the MicroWire interface, refer to the Am79C971
`data sheet. The interface also supports the WRITE operation to the EEPROM.
`AUTO-NEGOTIATION CONTROL
`
`
`The PCnet-FAST board implements the Auto-Negotiation standard per the IEEE 802.3
`specification for the 10BASE-T Media Attachment Unit (MAU) and the MII port.
`Auto-Negotiation automatically configures the link between two link partners through the
`Fast Link Pulse. The Fast Link Pulse is made up of a train of 17 clocks alternating with the
`16 data fields for a total of 33 pulses. The two link partners send information in the 16 data
`positions between themselves. Both sides look to see what is possible and then connect
`at the greatest speed and capability (without any software support) as shown in the table
`
`FAST board are as follows:
`below. The Auto-Negotiation capabilities for the PCnet-
`
`Table 2-1
`
`Auto-Negotiation Capabilities
`
`Network Speed
`200 Mbps
`100 Mbps
`20 Mbps
`10 Mbps
`
`Physical Network Type
`100BASE-TX, Full Duplex
`100BASE-TX, Half Duplex
`10BASE-T, Full Duplex
`10BASE-T, Half Duplex
`
`2-2
`
`Functional Description
`
`AMX
`Exhibit 1035-00005
`
`

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`CHAPTER
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`3
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`3.1
`
`3.2
`
`SETUP AND INSTALLATION
`
`BOARD CONFIGURATION
`Configuration of the I/O base address and the interrupt channel is automatic upon power
`up, without any hardware jumpers. The system BIOS routine is responsible for assigning
`
`
`the I/O base address and binding the appropriate interrupt channels to the PCnet-FAST
`board. One may find out what the I/O base assignment and the interrupt channel binding
`through the AMD installation software and configuration utility. For more detailed informa-
`
`PCnet Family Network Driver Installation Guide.
`tion on this utility, refer to the
`10/100BASE-T PHYSICAL CONNECTIONS
`A Data Terminal Equipment (DTE) system with the installed PCnet-FAST board can
`
`
`connect to an Ethernet network using the on-board RJ-45 jack for either 10BASE-T or
`100BASE-TX connection. Figure 3-1 illustrates a typical network configuration for the net-
`
`FAST board.
`work using the PCnet-
`
`DTE
`
`DTE
`
`DTE
`
`Twisted-Pair Cable
`
`Network Hub
`
`8-Pin RJ-45 Jack
`
`20963A-2
`
`
`
`Figure 3-1 PCnet-FAST 10/100BASE-T Physical Connections
`
`
`
`The Auto-Poll™ feature of the PCnet-FAST controller determines that the MII port is used
`
`
`for the network connection. Since an external 10/100-Mbps transceiver is used in the
`
`
`
`FAST board, the Auto-Negotiation feature of the PCnet-FAST controller configures
`PCnet-
`
`Setup and Installation
`
`3-1
`
`AMX
`Exhibit 1035-00006
`
`

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`3.3
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`whether the capability of the network is 10 Mbps or 100 Mbps, and whether it is full or half-
`duplex.
`NETWORK STATUS
`Four LEDs on the bracket provide the network status as shown in the following table:
`
`LED 2
`
`Amber
`
`10/100*
`
`LED 3
`
`Green
`
`COL
`
`On = 100 Mbps
`Off = 10 Mbps
`
`On = Collision
`Off = No Collision
`
`LED
`Color
`
`Function
`
`Meaning
`
`LED 0
`
`Green
`
`LNKST
`
`On = Link Pass
`Off = Link Fail
`
`LED 1
`
`Green
`
`ACT
`
`For XMT:
`On = Transmit
`Off = No Trans.
`For ACT:
`On = Busy
`Off = No Activity
`
`*Valid only when LED 0 is On.
`
`The placement of the LEDs are shown in Figure 3-2.
`
`LED 2
`
`LED 0
`
`LED 3
`
`LED 1
`
`Figure 3-2 LED Placement
`
`20963A-3
`
`3-2
`
`Setup and Installation
`
`AMX
`Exhibit 1035-00007
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`

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`CHAPTER
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`4
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`4.1
`
`HARDWARE SPECIFICATIONS
`
`PCI INTERFACE
`The Am79C971 chip on the PCnet-FAST board contains the interface logic to the PCI bus.
`
`
`Connections to the PCI bus are straightforward in that there is no external glue logic on the
`
`
`
`
`PCnet-FAST board, thus making the PCnet-FAST board fully compliant to the PCI loading
`and trace length specifications.
`
`
`
`The types of PCI cycles supported on the PCnet-FAST board are as follows:
`
`
`
`n
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`n
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`n
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`n
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`n
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`n
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`n
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`Master Memory Read
`Master Memory Write
`Master Memory Read Line
`Slave Configuration Read
`Slave Configuration Write
`Slave I/O Read
`Slave I/O Write
`
`The first three types are the Master cycles that the Am79C971 chip uses to transfer data
`across the PCI bus. The Am79C971 chip owns and controls the address/data bus after its
`request is acknowledged by the system arbiter. If there are two or less double words to
`read, the Am79C971 chip uses the Memory Read cycle; if there are more than two double
`words to read, the Am79C971 chip uses the Memory Read Line cycle. All Master cycles
`also support the four types of slave termination schemes specified in the PCI Revision 2.1
`specification.
`
`The last four types are the Slave cycles that the host CPU uses to access configuration
`and register information in the Am79C971 chip.
`I/O BASE ADDRESS AND INTERRUPT
`In a PCI system, the I/O base address and the interrupt channel that the PCnet-FAST
`
`
`board uses are assigned by the POST routine. Software drivers determine the I/O base
`
`
`address and the interrupt channel assigned to the PCnet-FAST board by reading the PCI
`configuration space of the device.
`
`4.2
`
`Hardware Specifications
`
`4-1
`
`AMX
`Exhibit 1035-00008
`
`

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`Table 4-1
`
`I/O Port Address
`
`I/O Resource
`
`Access Code
`
`APROM
`
`I/O Base address + 0h
`
`RDP
`
`RAP
`
`I/O Base address + 10h
`
`I/O Base address + 12h for word I/O mode (in Am1500 driver compatible
`mode)
`
`I/O Base address + 14h for double word mode
`
`Reset Register
`
`I/O Base address + 14h for word I/O mode (in Am1500 driver compatible
`mode)
`
`I/O Base address + 1Ch for double word I/O mode
`
`BDP
`
`I/O Base adddres + 16h for word I/O mode (in Am1500 driver compatible
`mode)
`
`I/O Base address +1Ch for double word I/O mode
`
`4.3
`
`RJ-45 INTERFACE
`
`
`The PCnet-FAST board is equipped with a RJ-45 type, eight-pin modular interface. The pin
`configuration and definition for the RJ-45 connection are as follows:
`
`Table 4-2
`
`RJ-45 Pinout
`
`Pin Number
`
`Pin 1
`
`Pin 2
`
`Pin 3
`
`Pin 6
`
`Pin 4
`
`Pin 5
`
`Pin 7
`
`Pin 8
`
`Color Code
`
`white/orange band
`
`orange/white band
`
`white/green band
`
`green/white band
`
`blue/white band
`
`white/blue band
`
`solid orange
`
`solid gray
`
`Function
`
`TX+
`
`TX-
`
`RX+
`
`RX-
`
`Not Used
`
`Not Used
`
`Not Used
`
`Not Used
`
`The color code may vary from one cable manufacturer to another. Make sure that the TX+
`and the TX- wires are twisted as a pair and the RX+ and the RX- wires are twisted as an-
`other pair. For 100-Mbps operation, category 5 wire must be used for proper 100BASE-TX
`operation.
`
`Note:Do not use the telephone-type cable commonly known as “silver satin” (flat, with sil-
`
`ver vinyl jacket) to connect the stations as none of the wires are twisted.
`
`SERIAL EEPROM
`The serial EEPROM contains the IEEE physical address unique to each node, the bus
`configuration, and the MAU configuration information. The format of the EEPROM
`contents is the following, beginning with the byte that resides at the lowest EEPROM
`address:
`
`Hardware Specifications
`
`4.4
`
`4-2
`
`AMX
`Exhibit 1035-00009
`
`

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`
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`Table 4-3
`
`EEPROM Address Format
`
`Word
`Address
`00h
`
` Byte
`Addr
`01h
`
`01h
`02h
`03h
`
`04h
`
`05h
`06h
`
`03h
`05h
`07h
`
`09h
`
`0Bh
`0Dh
`
`07h
`
`0Fh
`
`11h
`
`13h
`15h
`17h
`19h
`1Bh
`
`1Dh
`
`1Fh
`21h
`
`23h
`
`25h
`27h
`29h
`
`2Bh
`
`2Dh
`2Fh
`31h
`
`08h
`
`09h
`0Ah
`0Bh
`0Ch
`0Dh
`
`0Eh
`
`0Fh
`10h
`
`11h
`
`12h
`13h
`14h
`
`15h
`
`16h
`17h
`18h
`
`19h
`
`33h
`
`Reserved location; must be 00h
`
`32h
`
`
`Most Significant Byte (MSB)
`2nd byte of the ISO 8802-3
`(IEEE/ANSI 802.3) station
`physical address for this node
`4th byte of node address
`6th byte of node address
`Reserved location; must be 00h
`
`Hardware ID: must be 11h if
`compatibility to AMD drivers is
`desired
`User programmable space
`MSB of two-byte checksum,
`which is the sum of bytes 00h-
`0Bh and bytes 0Eh and 0Fh
`Must be ASCII “W” (57h) if
`compatibility to AMD driver
`software is desired
`BCR2[15:8] (Miscellaneous
`Configuration)
`BCR4[15:8] (Link Status LED)
`BCR5[15:8] (LED1 Status)
`BCR6[15:8] (LED2 Status)
`BCR7[15:8] (LED3 Status)
`BCR9[15:8] (Full-Duplex
`Control)
`BCR18[15:8] (Burst & Bus
`Control)
`BCR22[15:8] (PCI Latency)
`BCR23[15:8] (PCI Subsystem
`Vendor ID)
`BCR24[15:8] (PCI Subsystem
`ID)
`BCR25[15:8] (SRAM Size)
`BCR26[15:8] (SRAM Boundary)
`BCR27[15:8] (SRAM Interface
`Control)
`BCR32[15:8] (MII Control &
`Status)
`BCR33[15:8] (MII Address)
`BCR35[15:8] (PCI Vendor ID)
`Reserved location; must be 00h
`
`Byte
`Addr
`00h
`
`02h
`04h
`06h
`
`08h
`
`0Ah
`0Ch
`
`0Eh
`
`10h
`
`12h
`14h
`16h
`18h
`1Ah
`
`1Ch
`
`1Eh
`20h
`
`22h
`
`24h
`26h
`28h
`
`2Ah
`
`2Ch
`2Eh
`30h
`
`
`Least Significant Byte (LSB)
`1st byte of the ISO 8802-3
`(IEEE/ANSI 802.3) station
`physical address for this node
`3rd byte of node address
`5th byte of node address
`Reserved location; must be
`00h
`Reserved location; must be
`00h
`
`User programmable space
`LSB of two byte checksum,
`which is the sum of bytes 00h-
`0Bh and bytes 0Eh and 0Fh
`Must be ASCII “W” (57h) if
`compatibility to AMD driver
`software is desired
`BCR2[7:0] (Miscellaneous
`Configuration)
`BCR4[7:0] (Link Status LED)
`BCR5[7:0] (LED1 Status)
`BCR6[7:0] (LED2 Status)
`BCR7[7:0] (LED3 Status)
`BCR9[7:0] (Full-Duplex
`Control)
`BCR18[7:0] (Burst & Bus
`Control)
`BCR22[7:0] (PCI Latency
`BCR23[7:0] (PCI Subsystem
`Vendor ID)
`BCR24[7:0] (PCI Subsystem
`ID)
`BCR25[7:0] (SRAM Size)
`BCR26[7:0] (SRAM Bounder)
`BCR27[7:0] (SRAM Interface
`Control)
`BCR32[7:0] (MII Control &
`Status)
`BCR33[7:0] (MII Address)
`BCR35[7:0] (PCI Vendor ID)
`Reserved location; must be
`00h
`Reserved location; must be
`00h
`
`Hardware Specifications
`
`4-3
`
`AMX
`Exhibit 1035-00010
`
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`1Ah
`
`1Bh
`
`1Ch
`
`1Dh
`
`1Eh
`
`1Fh
`
`35h
`
`37h
`
`39h
`
`Reserved location; must be 00h
`
`34h
`
`Reserved location; must be 00h
`
`36h
`
`Reserved location; must be 00h
`
`38h
`
`3Bh
`
`Reserved location; must be 00h
`
`3Ah
`
`3Dh
`
`Reserved location; must be 00h
`
`3Ch
`
`3Fh
`
`Checksum adjust byte for the 64
`bytes of the EEPROM contents,
`checksum of the 64 bytes of the
`EEPROM should total to Ffh
`
`3Eh
`
`Reserved location; must be
`00h
`Reserved location; must be
`00h
`Reserved location; must be
`00h
`Reserved location; must be
`00h
`Reserved location; must be
`00h
`Reserved location; must be
`00h
`
`The IEEE physical address is unique to each node and manufacturer. Each manufacturer
`
`FAST board must only use the address block assigned to the company. AMD
`of the PCnet-
`
`00 00 1A 18 XX XX address block. To apply for an IEEE block address, the board
`uses
`manufacturer must contact:
`
`IEEE Standard Department
`445 Hoer Lane
`Piscataway, NJ 08855-1331
`c/o OUI Registrar
`Tel: (908) 562-3809
`
`The EEPROM contents could either be pre-programmed on an off-line EEPROM program-
`
`FAST board via the MicroWire protocol. The actual
`mer, or be programmed on the PCnet-
`programming procedure on the off-line is left to the user.
`
`Note:The last four digits of the IEEE address can be found on a label attached to the
`
`EEPROM of the PCnet-FAST board.
`
`PHYSICAL DIMENSIONS
`Without the bracket mounted to the board, the physical dimensions of the board are as
`follows:
`
`n
`
`n
`
` 4.7 inches
`Width:
`Height: 3.6 inches
`POWER REQUIREMENTS
`The power requirements are as follows:
`
`4.5
`
`4.6
`
`n
`
`n
`
`C (with NSC 10/100 PHY)
`3.25 W maximum, 5 V DC, at 25
`C (with ICS 10/100 PHY)
`1.90 W maximum, 5 V DC, at 25
`To properly reflect the power consumption of the board in the PCI environment, the
`PRSNT#1 and PRSNT#2 signals on the boards are shorted to Ground according to the
`PCI rev 2.1 Specification.
`
`4-4
`
`Hardware Specifications
`
`AMX
`Exhibit 1035-00011
`
`(cid:176)
`(cid:176)
`

`
`© 1996 Advanced Micro Devices, Inc.
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`Advanced Micro Devices reserves the right to make changes in its products
`without notice in order to improve design or performance characteristics.
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`This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants of merchantability or fitness for
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`a particular application. AMD
` assumes no responsibility for any circuitry other than the circuitry in an AMD product.
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`The information in this publication is believed to be accurate in all respects at the time of publication, but is subject to change without notice. AMD
`assumes no responsibility for any errors or omissions, and disclaims responsibility for any consequences resulting from the use of the information
`included herein. Additionally, AMD assumes no responsibility for the functioning of undescribed features or parameters.
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`Copyright © 1996 Advanced Micro Devices, Inc. All rights reserved.
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`AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
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`Auto-Poll and PCnet are trademarks of Advanced Micro Devices, Inc.
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`Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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`AMX
`Exhibit 1035-00012