(12) United States Patent
`Tsujimura et al.
`
`IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
`
`US006689629B2
`US 6,689,629 B2
`Feb. 10,2004
`
`(io) Patent No.:
`(45) Date of Patent:
`
`(54) ARRAY SUBSTRATE FOR DISPLAY,
`METHOD OF MANUFACTURING ARRAY
`SUBSTRATE FOR DISPLAY AND DISPLAY
`DEVICE USING THE ARRAY SUBSTRATE
`
`(75)
`
`Inventors: Takatoshi Tsujimura, Fujisawa (JP);
`Atsuya Makita, Sagamihara (JP);
`Toshiaki Arai, Yokohama (JP)
`
`(73) Assignee: International Business Machines
`Corporation, Armonk, NY (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 54 days.
`
`(21) Appl. No.: 10/068,500
`Feb. 5, 2002
`(22) Filed:
`
`(65)
`
`(30)
`
`Prior Publication Data
`
`US 2002/0106843 Al Aug. 8, 2002
`Foreign Application Priority Data
`
`(JP)
`
`Feb. 6, 2001
`(51) Int. CI.7
`(52) U.S. CI
`
`2001-029587
`H01L 21/00
`438/25; 438/149; 438/73;
`257/72; 257/748
`
`(58) Field of Search
`
`438/25, 22, 30,
`438/149, 73; 257/72, 748
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,285,301 A * 2/1994 Shirahashi et al.
`6,163,356 A * 12/2000 Song et al
`* cited by examiner
`Primary Examiner—Caridad Everhart
`(74) Attorney, Agent, or Firm—Tiffany L. Townsend
`ABSTRACT
`(57)
`
`. 359/59
`349/152
`
`Disclosed is to provide an array substrate for display, a
`method of manufacturing the array substrate for display and
`a display device using the array substrate for display.
`
`The present invention is an array substrate for display, which
`includes: a thin film transistor array formed on an insulating
`substrate 1; a plurality of wirings 23 and 24 arranged on the
`insulating substrate 1; connection pads 25 and 27 arranged
`on unilateral ends of the wirings 23 and 24 and respectively
`connected therewith; and pixel electrodes 22, wherein
`dummy conductive patterns 29 are arranged between the
`ends of the connection pads 25 and 27 and ends of the pixel
`electrodes 22.
`
`16 Claims, 11 Drawing Sheets
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`U.S. Patent
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`Feb.10,2004
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`Sheet 11 of 11
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`US 6,689,629 B2
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`1
`ARRAY SUBSTRATE FOR DISPLAY,
`METHOD OF MANUFACTURING ARRAY
`SUBSTRATE FOR DISPLAY AND DISPLAY
`DEVICE USING THE ARRAY SUBSTRATE
`
`2
`Moreover, in the gazette of Japanese Patent Laid-Open
`No. Hei 10 (1998)-240150, disclosed is a method of forming
`a tapered shape at an angle ranging from 20 degrees to 70
`degrees on wiring constituted of two layers, in which a pad
`5 formed of aluminum and metal such as molybdenum formed
`on the aluminum is subjected to wet etching. According to
`BACKGROUND OF THE INVENTION
`this method, a specified tapered shape can be imparted to the
`wiring formed of a conductive film of a two-layer structure
`The present invention relates to an array substrate for
`by the wet etching. However, the method never discloses a
`display, a method of manufacturing the array substrate for
`display and a display device using the array substrate for 1° method of evenly etching a substrate region while maintain­
`ing a selection ratio thereof even in the substrate region
`display.
`where the wiring density is lowered.
`A display device using a thin film transistor (TFT) array
`FIGS. 12A and 12B are enlarged schematic views for
`has been frequently used owing to low power consumption
`and capability of downsizing the display device. The thin
`explaining a patterning process using a conventionally used
`film transistor array is manufactured by forming thin film 15 wet process in order to impart the above-described tapered
`transistors, each being composed of electrodes such as a gate
`shape to the wiring. As shown in FIG. 12A, the lower
`electrode, a source electrode and a drain electrode, wirings
`conductive material 3 and an upper conductive material 4
`such as scan lines and signal lines connected with the
`are deposited on the insulating substrate 1 by a method such
`above-mentioned electrodes, and pixel electrodes on an
`as physical vapor deposition. FIG. 12A shows that a pho-
`insulating substrate.
`20 toresist film 5 is coated on a film of the upper conductive
`material 4 and is patterned in a desired shape. The respective
`In recent years, a higher operating speed, a higher reso­
`films are etched by an etchant such as a solution of phos­
`lution and a larger size have been required for the display
`phoric acid, nitric acid, acetic acid or mixtures thereof, and
`device described above in many cases. A high speed and a
`desired tapered shapes are formed thereon.
`high density have been required for each constituent com- ^
`FIG. 12B is a view for explaining an electrochemical
`ponent of the array for display, which forms a display
`process generated as each film is being etched when the
`device. Particularly, in order to operate the thin film tran­
`wiring constituted of the upper conductive material 4 and the
`sistor array at a high speed, it is preferable to use low-
`lower conductive material 3 is subjected to wet etching. In
`resistance aluminum (Al) for the wirings such as the scan
`FIG. 12B, an internal layer portion of the upper conductive
`lines and the signal lines since delay in gate pulses can be
`30 material 4 coated with the photoresist film 5 is not dissolved.
`reduced and a writing speed to the thin film transistor can be
`However, at the end of the photoresist film 5, the upper
`increased.
`conductive material 4 is dissolved by the etchant. When the
`Incidentally, aluminum tends to be easily oxidized in spite
`wiring is formed by the wet etching, the upper conductive
`of its low resistance. Therefore, in many cases, wiring using
`material 4 protected by the photoresist film 5 is further
`aluminum is constituted as a two-layer structure, in which
`35 dissolved in a lateral direction from the end of the photo­
`aluminum is used as a lower conductive material, and a
`resist film 5 to turn into positive ions, and electrons emitted
`material harder to be oxidized than aluminum such as
`as a result are supplied to the lower conductive material 3.
`chromium, tantalum, titanium or molybdenum is used as an
`Thus, the upper conductive material 4 serves as an anode. In
`upper conductive material. FIG. 11 is a view schematically
`this connection, the lower conductive material 3 comes to
`showing a state where wiring 2 is deposited on an insulating
`40 serve as a cathode. Accordingly, an electrochemical cell is
`substrate 1. A lower conductive material film 2a is deposited
`formed. Here, when the etching rate for the upper conduc­
`on an insulating substrate 1 made of such as glass, and an
`tive material 4 is increased to form a required tapered shape,
`upper conductive material film 2b is deposited on the lower
`the density of the electrons generated by dissolving the
`conductive material film 2a. Each of these films 2a and 2b
`upper conductive material 4 and flowing to the lower
`is patterned by, for example, a proper etching process so as
`45 conductive material 3 is increased accompanied with an
`to have tapered ends.
`increase of a dissolution rate of the upper conductive mate­
`In order to form a tapered shape shown in FIG. 11, an
`rial 4. FIG. 12B schematically shows currents I flowing from
`etching rate for the upper conductive material is required to
`the upper conductive material 4 to the lower conductive
`be increased. In order to form the tapered shape shown in
`material 3.
`FIG. 11, various methods have been proposed up to now. For 50
`As the etching rate is increased, the density of the current
`example, in the gazette of Japanese Patent Laid-Open No.
`flowing to an area of the upper conductive material 4, which
`Hei 10 (1998)-90706, a method has been proposed, in which
`is exposed to the etchant, exceeds a current density causing
`dummy connection pads are provided on sides opposite to
`passivity of the upper conductive material 4. In such a case,
`scan line connection pads and signal line connection pads,
`the upper conductive material 4 is passivated not to be
`respectively. According to this method, over etching due to 55
`dissolved by the etchant, and only the lower conductive
`an etchant that will be relatively increased by lowering
`material 3 is dissolved accompanied with the progress of the
`wiring density at ends of the substrate is prevented. Thus,
`etching, resulting in the occurrence of the undercut. When
`undercut of a lower conductive material 3 is prevented, and
`such undercut occurs, the wiring, for example, the gate
`an interlayer short circuit is prevented by imparting a proper
`60 wiring cannot be sufficiently coated with an insulating film
`tapered shape to the wiring 2.
`in some cases, thus causing inconvenience such as an
`However, though this method enables evenness of etching
`interlayer short circuit, resulting in lowering a yield of the
`at the ends of the thin film transistor array substrate to be
`display device.
`improved, the method cannot effectively prevent the under­
`cut of the signal lines in a region where the wiring density
`is apt to be lowered from ends of the pixel electrodes to the 65
`connection pads, for example, in a portion where drawing
`wiring is formed.
`
`US 6,689,629 B2
`
`SUMMARY OF THE INVENTION
`The present invention was made with the foregoing
`problems in mind. An object of the present invention is to
`
`

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`US 6,689,629 B2
`
`60
`
`4
`FIG. 4 is an enlarged view showing another dummy
`conductive pattern in the present invention.
`FIGS. 5A to 5C are views illustrating a method of
`manufacturing the array substrate for display of the present
`invention.
`FIG. 6 is an electron microscope photograph showing a
`pattern shape of wiring in the case of using the dummy
`conductive pattern shown in FIG. 3.
`FIG. 7 is an electron microscope photograph showing a
`pattern shape of wiring in the case of using the dummy
`conductive pattern shown in FIG. 4.
`FIG. 8 is a graph showing a relation between a taper angle
`of the wiring and a pattern density of the wiring.
`FIG. 9 is an electron microscope photograph showing a
`wiring shape in the case of performing etching without using
`the dummy conductive pattern.
`FIG. 10 is an electron microscope photograph showing a
`sectional shape of the wiring shape shown in FIG. 9.
`FIG. 11 is a schematic view showing a tapered shape of
`the wiring.
`FIGS. 12A and 12B are views showing currents formed
`by a cell formed during an etching process.
`
`3
`provide an array substrate for display, a method of manu­
`facturing an array substrate for display and a display device
`using the array substrate for display, which are capable of
`being etched at a sufficiently high etching rate and a suffi­
`cient selection ratio, eliminating undercut, and providing a 5
`large-sized and high-resolution display device.
`The foregoing object of the present invention is achieved
`by providing the array substrate for display, the method of
`manufacturing an array substrate for display and the display
`device using the array substrate for display of the present
`invention.
`Specifically, according to the present invention, provided
`is an array substrate for display, comprising: a thin film
`transistor array formed on an insulating substrate; a plurality
`of wirings arranged on the insulating substrate; connection 15
`pads arranged on unilateral ends of the wirings and respec­
`tively connected with the wirings; pixel electrodes, and
`dummy conductive patterns arranged between the ends of
`the connection pads and ends of the pixel electrodes. The
`dummy conductive patterns can occupy 30 area % or more. 20
`In the present invention, the dummy conductive patterns can
`be formed as any of land patterns and line-and-space pat­
`terns. In the present invention, the wirings are constituted of
`a lower conductive material and an upper conductive
`material, and the lower conductive material can be any one 25
`DETAILED DESCRIPTION OF THE
`of aluminum and an aluminum alloy. In the present
`PREFERRED EMBODIMENTS
`invention, the upper conductive material has a passivating
`Hereinbelow, description will be made in detail for the
`potential. The upper conductive material can be any one of
`present invention with reference to embodiments shown in
`molybdenum and a molybdenum alloy.
`the accompanying drawings. However, the present invention
`According to the present invention, provided is a method 30
`is not limited to the embodiments shown in the drawings.
`of manufacturing an array substrate for display, the method
`FIG. 1 is a partially cutaway perspective view showing an
`comprising the steps of: forming a thin film transistor array
`embodiment of a display device using an array substrate for
`including: a plurality of wirings arranged on an insulating
`display of the present invention. As shown in FIG. 1, the
`substrate; and connection pads arranged on unilateral ends
`of the wirings and respectively connected with the wirings; 3S display device of the present invention is constituted by
`forming pixel electrodes; and forming dummy conductive
`sequentially laminating a liquid crystal layer 11, a transpar-
`ent electrode 12 and a glass substrate 13 on an array
`patterns between ends of the connection pads and ends of the
`substrate 10 for display, which is formed on an insulating
`pixel electrodes. In the present invention, it is preferable that
`substrate. Wiring 14 formed on the insulating substrate 10 is
`the dummy conductive patterns be formed so as to occupy
`30 area % or more. In the present invention, the dummy 40 extended to an end (not shown) of the array substrate for
`conductive patterns can be formed as any of land patterns
`display, and is connected with a driving system (not shown)
`and line-and-space patterns. In the present invention, the
`through a connection pad (not shown),
`FIG. 2 is a top plan view of the display device using the
`wirings are constituted of a lower conductive material and
`array substrate 10 for display of the present invention, which
`an upper conductive material, the lower conductive material
`can be any one of aluminum and an aluminum alloy, and the 45 is shown in FIG. 1. In the array substrate 10 for display of
`the present invention, a plurality of thin film transistors 21
`upper conductive material can be any one of molybdenum
`constitute an array. A pixel electrode 22 is connected with
`and a molybdenum alloy. In the present invention, the
`each thin film transistor 21 that controls a potential of the
`wirings are formed by wet etching.
`pixel electrode. In the array substrate 10 for display shown
`Moreover, in the present invention, provided is a display
`device, comprising the array substrate for display mentioned 50 in FIG. 2, what is further shown is that a scan line 23 and a
`signal line 24 are connected with each thin film transistor 21.
`above.
`The respective scan lines 23 are connected with a driver
`In the present invention, the display device used as a
`26 through scan line connection pads 25, and the respective
`liquid crystal display device or an electroluminescence
`signal lines 24 are connected with a driver 28 through signal
`display device can be provided.
`55 line connection pads 27. These scan lines 23 and the signal
`BRIEF DESCRIPTION OF THE DRAWINGS
`lines 24 are formed so as to have the same constitution. As
`For a more complete understanding of the present inven­
`shown in FIG. 11, each of these lines is constituted of the
`tion and the advantages thereof, reference is now made to
`lower conductive material 3 and the upper conductive mate­
`the following description taken in conjunction with the
`rial 4.
`accompanying drawings.
`In the present invention, aluminum can be used for the
`FIG. 1 is a view showing an embodiment of a liquid
`lower conductive material 3 usable as wiring from a view­
`crystal display device using an array substrate for display of
`point of lowering resistance thereof. Moreover, it is prefer­
`the present invention.
`able to use molybdenum (Mo) for the upper conductive
`FIG. 2 is a top plan view of the array substrate for display
`material 4 usable in the present invention from a viewpoint
`of the present invention.
`65 of protecting the aluminum. However in the present
`invention, besides the aluminum, an aluminum alloy can be
`FIG. 3 is an enlarged view showing a dummy conductive
`pattern in the present invention.
`used for the lower conductive material 3. Moreover, for the
`
`

`
`US 6,689,629 B2
`
`6
`5
`specified surface. In the present invention, the term "wiring
`upper conductive material 4, alloys of chromium, tantalum,
`density" refers to an area ratio of an area of portions where
`titanium and molybdenum can be used. Film thickness of the
`the signal lines, the scan lines, the drawing lines, and the
`lower conductive material 3 is not particularly limited, but
`dummy conductive patterns are formed on an area of a
`film thickness of the upper conductive material 4 is prefer­
`ably thick since a current tends to be concentrated thereto as 5 specified region where the dummy conductive patterns are
`the film
`thickness becomes thinner. However, a problem
`formed,
`FIG. 4 is a view showing another embodiment of the
`regarding stress occurs as the thickness becomes thicker.
`dummy conductive pattern 29 of the present invention. In
`Therefore, in the present invention, it is preferable to set the
`the embodiment shown in FIG. 4, the dummy conductive
`film thickness of the upper conductive material 4 in a range
`10 pattern 29 is disposed so that the wiring density thereof,
`of 30 to 100 nm.
`which is specified at 30% or more, is further increased, thus
`The present invention makes it possible to prevent under­
`reducing concentration of electric current to exposed por­
`cut of the lower conductive material 3, which occurs due to
`tions of the upper conductive material to the etchant during
`passivity of the upper conductive material 4. In the present
`the etching. As shown in FIG. 4, the dummy conductive
`invention, the term "passivity" is referred to as a phenom­
`pattern 29 may have any shapes and any patterns. Moreover,
`enon that metal such as molybdenum or a metal alloy such
`any combination of a plural type of the dummy conductive
`as a molybdenum alloy becomes insoluble in an acid or
`patterns 29 can be used.
`alkaline etchant. For example, the term "passivity" is
`FIGS. 5A, 5B and 5C are views showing an embodiment
`referred to as a phenomenon that metal serving as an anode
`of a method of manufacturing the array substrate 10 for
`becomes insoluble in such etchant. In the present invention,
`20 display of the present invention. With reference to FIG. 5,
`specifically as for such passivated metal or a metal alloy,
`description will be made for the method of manufacturing
`metal or a metal alloy with a passivating potential, that is, a
`the array substrate 10 for display of the present invention,
`Flade potential can be mentioned. Note that, in the present
`exemplifying a case where the thin film transistor 21 of a
`invention, the Flade potential is referred to as a potential
`reverse stagger type is formed. First, as shown in FIG. 5A,
`which causes a current density for passivating metal, which
`the lower conductive material 3 using aluminum and the
`is described in the Encyclopedia Chimica (miniature edition 25
`upper conductive material 4 using molybdenum are depos­
`32"^ printing, issued by Kyoritsu Shuppan Co., Ltd., edited
`ited on the transparent or untransparent insulating substrate
`by editorial committee of the Encyclopedia Chimica), vol. 7,
`1, thus forming a film.
`p. 911.
`Next, as shown in FIG. 5B, photoresist 31 is coated on the
`Furthermore, in the embodiment shown in FIG. 2, dummy
`film. The photoresist is exposed and developed by use of a
`conductive patterns 29 are disposed between the pixel 30
`photo mask 32 provided with patterns for forming the
`electrodes 22 and each scan line connection pad 25 and
`dummy conductive patterns 29 in portions where the wiring
`between the pixel electrodes 22 and each signal line con­
`density is lowered between the pixel electrodes and the
`nection pad 27. Thus, the wiring density is increased.
`connection pads, which are not particularly shown.
`Therefore, it is made possible to form good wiring over the
`Subsequently, etching is performed by use of an etchant
`entire surface of the array substrate for display without 35
`such as a solution of phosphoric acid, nitric acid, acetic acid
`causing defects such as undercut and a mouse hole of the
`and mixtures thereof, thus forming the wiring 2 and the
`lower conductive material 3 during etching for the scan lines
`dummy conductive patterns 29. The dummy conductive
`23 and the signal lines 24. Each of these dummy conductive
`patterns 29 are arranged in the portions where the wiring
`patterns 29 can be formed as a two-layers structure with the
`densi ^ low ^ it ^ made
`ible to form wiri
`same materials as those of the scan lines 23 and the signal
`having good tapered shape as shown in FIG. 5C even in
`lines 24 at the same time when the patterning is performed
`regions where the conductive material such as molybdenum
`therefor.
`tends to be passivated. A taper angle can be set in a range of
`FIG. 3 is an enlarged view showing a portion where the
`20 degrees to 70 degrees by adjusting a composition of the
`dummy conductive pattern 29 is formed in the embodiment 45 etchant and etching conditions. It is more preferable to set
`of the array substrate 10 for display of the present invention
`the taper angle in a range of about 20 degrees to about 60
`shown in FIG. 2. FIG. 3 shows the dummy conductive
`degrees.
`pattern 29 formed as a line-and-space pattern between the
`Thereafter, in the present invention, gate insulating films,
`connection pad 25 and an end 30 of the pixel electrode. In
`the gate electrodes, the source electrodes, the drain
`the present invention, the dummy conductive pattern 29 can
`50 electrodes, the pixel electrodes and the like are formed, thus
`be formed as the line-and-space pattern shown in FIG. 3.
`the array substrate 10 for display of the present invention is
`Alternatively, the dummy conductive pattern 29 can be
`manufactured. In the present invention, the dummy conduc­
`formed as a land pattern completely coating a region where
`tive patterns 29 may be removed if necessary. Alternatively,
`the dummy conductive pattern 29 is formed.
`the dummy conductive patterns 29 may be left as they are
`In any case of the patterns, in the present invention, it is 55 without being eliminated,
`preferable that the wiring density of the dummy conductive
`piG. 6 is an electron microscope photograph showing a
`patterns 29 themselves be 30% or more on an area of a
`shape of the wiring 33 shown in FIG. 3, which was obtained
`specified surface from a viewpoint of forming a properly
`when the dummy conductive pattern 29 shown in FIG. 3 was
`tapered shape on the lower conductive material 3 without
`provided and the etching was performed. In this case,
`forming the undercut thereto while dissolving the upper 60 molybdenum was used for the upper conductive material 4,
`conductive material 4 at a required rate.
`anc} aluminum was used for the lower conductive material 3.
`The film thickness of molybdenum is about 50 nm, and wet
`Moreover, when the dummy conductive patterns 29 are
`arranged in the present invention, it is more preferable that
`etching is performed by use of an etchant of a mixed solution
`the dummy conductive patterns 29 be formed between the
`of phosphoric acid, nitric acid and acetic acid. As shown in
`end 30 of the pixel electrode 22 and each connection pads 25 65 FIG. 6, a good tapered shape is formed even in a wiring
`and 27 so that the wiring density including the dummy
`portion where the undercut is formerly apt to occur by
`conductive patterns 29 can be 30% or more on the area of a
`forming the dummy conductive pattern 29.
`
`

`
`US 6,689,629 B2
`
`8
`
`7
`FIG. 7 is a photograph showing a shape of the wiring 34
`What is claimed is:
`1. An array substrate for display, comprising:
`shown in FIG. 4, which was obtained when the dummy
`conductive pattern 29 shown in FIG. 4 was formed and the
`a layer of an insulating substrate, having an area;
`etching was performed under the same conditions as those in
`a thin film
`transistor array formed on the insulating
`FIG. 6. As shown in FIG. 7, even when the density of the 5
`substrate;
`dummy conductive pattern 29 is increased, a good tapered
`a plurality of wiring arranged on the insulating substrate,
`shape is obtained.
`each wiring having a first end, the wiring in commu­
`FIG. 8 is a graph plotting values of the taper angle of the
`nication with at least one of the transistors in the thin
`formed wiring relative to values of the pattern density (area
`film array;
`%) of the wiring including the portions of the dummy 10
`connections pads, each connection pad contacting the first
`conductive patterns 29 on the substrate when the dummy
`end of at most one of the plurality of wirings;
`conductive patterns 29 are arranged. As shown in FIG. 8, the
`pixel electrodes, and
`taper angle of the wiring obtained by the etching is reduced
`dummy conductive patterns, the dummy patterns com­
`as the pattern density of the wiring is increased, and a more
`prising at least about 30% of the area of the insulating
`gentle taper is formed. Therefore, it is understood that the 15
`substrate, the dummy conductive patterns situated
`upper conductive material 4 can impart a sufScient selective
`between the connection pads and the pixel electrodes
`ratio to the etching of the lower conductive material 3 by
`arranging the dummy conductive patterns 29.
`such that the dummy patters are not in contact with any
`of the wiring.
`FIG. 9 is an electron microscope photograph showing, for
`comparison, a shape of wiring obtained when etching is
`2. The array substrate for display according to claim 1
`performed by use of the array substrate 10 for display, which
`wherein at least one of the wirings comprises at least an
`has the same pattern as those shown in FIGS. 3 and 4, but
`upper layer and a lower layer of conductive materials.
`3. The array substrate for display according to claim 2
`without forming the dummy conductive patterns 29 at all. As
`shown in FIG. 9, large undercut occurs in the wiring since
`wherein the lower layer wiring material is selected from the
`the molybdenum used for the upper conductive material 4 is
`group consisting of aluminum and aluminum alloys,
`passivated, and only the etching for the aluminum as the
`4. The array substrate for display according to claim 2
`lower conductive material 3 progresses.
`wherein the upper layer wiring material is selected from the
`group consisting of molybdenum, chromium, tantalum, tita-
`FIG. 10 is an electron microscope photograph showing a
`_
`cross section taken along a cutting plane line A—A of the 30 nium and alloys thereof,
`wiring shown in FIG. 9. As shown in FIG. 10, the etching for
`5- The array substrate for display according to claim 3
`the aluminum used for the lower conductive material 3
`wherein the upper layer wiring material is selected from the
`group consisting of molybdenum, chromium, tantalum, tita­
`progresses more than that for the molybdenum used for the
`nium and alloys thereof.
`upper conductive material 4, resulting in the occurrence of
`6. The array substrate for display according to claim 5
`the great undercut.
`wherein the upper wiring material is selected from the group
`The present invention can be applied not only to the thin
`consisting of molybdenum and alloys thereof.
`film transistor of a reverse stagger type as described above
`7. The array substrate for display according to claim 4
`but also to a thin film transistor of a top gate type including
`wherein the upper layer wiring material is selected such that
`wiring formed of aluminum and any metal other than the
`the upper layer wiring material does not become insoluble in
`aluminum, of which passivating current density is known.
`an acid or alkaline etchant.
`Moreover, although the array device for display of the
`8. The array substrate for display according to claim 5
`present invention can be applied to a liquid crystal display
`wherein the upper layer wiring material is selected such that
`device using a transparent insulating substrate made of such
`the upper layer wiring material does not become insoluble in
`as glass, the array device for display of the present invention
`an acid or alkaline etchant.
`can be also used as an organic or inorganic electrolumines- 45
`9. A meted for forming an array substrate for display,
`cence device, wherein an untransparent insulating substrate
`comprising:
`is used and an array for display is formed on the insulating
`forming a layer of an insulating substrate, having an area;
`substrate.
`forming a thin film transistor array formed on the insu­
`As described above, according to the present invention, it 5Q
`lating substrate, each wiring having a first end, the
`is made possible to provide an array substrate for display, a
`wiring in communication with at least on of the tran­
`method of manufacturing an array substrate for display and
`sistors in the thin film array;
`a display device using the array substrate for display, which
`forming connections pads, each connection pad contact­
`are capable of being etched at a sufficiently high etching rate
`ing the first end of at most one of the plurality of
`and a sufficient selection ratio, and eliminating the under cut 55
`wirings;
`and the lowering of a yield in manufacturing due to the
`forming pixel electrodes, and
`inconvenience such as an interlayer shor