US006689629C1
`(12) EX PARTE REEXAMINATION CERTIFICATE (10404th)
`United States Patent
`US 6,689,629 CI
`(10) Number:
`Tsujimura et al.
`(45) Certificate Issued:
`Nov. 14, 2014
`
`(54) ARRAY SUBSTRATE FOR DISPLAY,
`METHOD OF MANUFACTURING ARRAY
`SUBSTRATE FOR DISPLAY AND DISPLAY
`DEVICE USING THE ARRAY SUBSTRATE
`
`(75)
`
`Inventors: Takatoshi Tsujimura, Fujisawa (JP);
`Atsuya Makita, Sagamihara (JP);
`Toshiaki Arai, Yokohama (JP)
`
`(73) Assignee: AU Optronics Corporation
`
`Reexamination Request:
`No. 90/009,697, Mar. 16, 2010
`
`Reexamination Certificate for:
`Patent No.:
`6,689,629
`Issued:
`Feb. 10, 2004
`Appl. No.:
`10/068,500
`Filed:
`Feb. 5, 2002
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 6, 2001
`
`(JP)
`
`2001-029587
`
`(51) Int. CI.
`H01L 21/00
`(52) U.S. CI.
`USPC
`
`(2006.01)
`
`438/25; 438/149; 438/73; 257/72;
`257/748
`
`(58) Field of Classiflcation Search
`None
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`To view the complete listing of prior art documents cited
`during the proceeding for Reexamination Control Number
`90/009,697, please refer to the USPTO's public Patent
`Application Information Retrieval (PAIR) system under the
`Display References tab.
`
`Primary Examiner — Tuan H Nguyen
`
`ABSTRACT
`(57)
`Disclosed is to provide an array substrate for display, a
`method of manufacturing the array substrate for display and a
`display device using the array substrate for display.
`The present invention is an array substrate for display, which
`includes: a thin film transistor array formed on an insulating
`substrate 1; a plurality of wirings 23 and 24 arranged on the
`insulating substrate 1; connection pads 25 and 27 arranged on
`unilateral ends of the wirings 23 and 24 and respectively
`connected therewith; and pixel electrodes 22, wherein
`dummy conductive patterns 29 are arranged between the ends
`of the connection pads 25 and 27 and ends of the pixel elec­
`trodes 22.
`
`13
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`14
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`10
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`ChinaStar Ex.1001
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`US 6,689,629 CI
`
`1
`EX PARTE
`REEXAMINATION CERTIFICATE
`ISSUED UNDER 35 U.S.C. 307
`
`AS A RESULT OF REEXAMINATION, IT HAS BEEN
`DETERMINED THAT:
`
`15
`
`20
`
`25
`
`THE PATENT IS HEREBY AMENDED AS
`INDICATED BELOW.
`
`Matter enclosed in heavy brackets [ ] appeared in the
`patent, but has been deleted and is no longer a part of the
`patent; matter printed in italics indicates additions made
`to the patent.
`
`5
`
`10
`
`Claims 2, 4, 10, 12 and 13 are cancelled.
`Claims 1, 3, 7, 9, 11 and 14-16 are determined to be
`patentable as amended.
`Claims 5, 6 and 8, dependent on an amended claim, are
`determined to be patentable.
`New claim 17 is added and determined to be patentable.
`
`2
`9. A [meted] method for forming an array substrate for
`display, comprising:
`forming a layer of an insulating substrate[, having an area];
`forming a thin film transistor array [formed] on the insu­
`lating substrate;
`forming a plurality of wirings on the insulating substrate,
`each wiring having a first end, [the] each wiring in
`communication with at least [on of the transistors] one
`transistor in the thin film transistor array, wherein at
`least one of the wirings comprises at least an upper layer
`and a lower layer of conductive materials, and the upper
`layer wiring material is selectedfrom the group consist­
`ing of molybdenum, chromium, tantalum, titanium and
`alloys thereof
`forming a plurality of connections pads, each connection
`pad contacting the first end of at most one of the plurality
`of wirings;
`forming a plurality of pixel electrodes[,]; and
`forming a plurality of dummy conductive patterns on the
`insulating substrate, wherein the plurality of dummy
`conductive patterns [comprising] comprises at least
`about 30% of [the] an area of the insulating substrate[,
`the dummy patterns situated] between the connection
`pads and the pixel electrodes [such that], and the dummy
`[patters] conductive patterns are not in contact with any
`of the [wiring] wirings.
`1. An array substrate for display, comprising:
`11. The method for forming an array substrate for display
`[a layer of] an insulating substrate[, having an area];
`
`rding to claim [10] 9 wherein the lower layer wiring acco
`a thin film transistor array [formed] on the insulating sub­
`materials is selected from the group consisting of aluminum
`strate;
`and aluminum alloys.
`a plurality of [wiring arranged] wirings on the insulating
`14. The method for forming an array substrate for display
`substrate, each wiring having a first end, [the] each wir- 30
`according to claim [13] 9 wherein the upper wiring material is
`ing in communication with at least one [of the transis­
`selected from the group consisting of molybdenum and alloys
`thereof.
`tors] transistor in the thin film transistor array, and at
`least one of the wirings comprising at least an upper
`15. The method for forming an array substrate for display
`according to claim [12] 9 wherein the upper layer wiring
`layer and a lower layer of conductive materials, wherein
`the upper layer wiring material is selected from the 35 material is selected such that the upper layer wiring material
`does not become insoluble in an acid or alkaline etchant.
`group consisting of molybdenum, chromium, tantalum,
`16. The method for forming an array substrate for display
`titanium and alloys thereof
`rding to claim [13] 9 wherein the upper layer wiring
`acco
`a plurality of connections pads, each connection pad con­
`material is selected such that the upper layer wiring material
`tacting the first end of at most one of the plurality of
`40 does not become insoluble in an acid or alkaline etchant.
`wirings;
`17. An array substrate for display, comprising:
`a plurality of pixel electrodes[,]; and
`an insulating substrate;
`a plurality of dummy conductive patterns on the insulating
`an array of thin film transistors on the insulating substrate;
`substrate, wherein the plurality of dummy conductive
`a plurality of wirings on the insulating substrate, each
`patterns [comprising] comprises at least about 30% of
`wiring having a first end, and each wiring directly con­
`[the] an area of the insulating substrate[, the dummy 45
`necting with at least one thin film transistor in the array;
`conductive patterns situated] between the connection
`a plurality of connections pads, each connection pad con­
`pads and the pixel electrodes [such that], andlhs dummy
`tacting the first end of at most one of the plurality of
`[patters] conductive patterns are not in contact with any
`wiring
`of the [wiring] wirings.
`a plurality of pixel electrodes; and
`3. The array substrate for display according to claim [2] 1 50
`a plurality of dummy conductive patterns on the insulating
`wherein the lower layer wiring material is selected from the
`substrate, wherein the plurality of dummy conductive
`group consisting of aluminum and aluminum alloys.
`patterns comprises at least about 30% of an area of the
`7. The array substrate for display according to claim [4] 1
`insulating substrate between the connection pads and
`wherein the upper layer wiring material is selected such that
`the pixel electrodes.
`the upper layer wiring material does not become insoluble in 55
`an acid or alkaline etchant.