IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re patent of Conley:
`
`U.S. Patent No. 7,818,490
`
`Issued: October 19, 2010
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND
`READING OPERATIONS IN A
`NON-VOLATILE MEMORY
`
`Petition for Inter Partes Review
`
`Attorney Docket No.:
`337722-000080.490
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`
`Real Party in Interest: Apple Inc.
`
`DECLARATION OF DR. VIVEK SUBRAMANIAN
`
`APPLE INC.
`EXHIBIT 1003 - PAGE 0001
`
`
`
`In re patent of Conley:
`
`U.S. Patent No. 7,818,490
`
`Issued: October 19, 2010
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND
`READING OPERATIONS IN A
`NON-VOLATILE MEMORY
`
`Petition for Inter Partes Review
`
`Attorney Docket No.:
`337722-000080.490
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`
`Real Party in Interest: Apple Inc.
`
`DECLARATION OF DR. VIVEK SUBRAMANIAN
`
`APPLE INC.
`EXHIBIT 1003 - PAGE 0001
`
`
`
`TABLE OF CONTENTS
`
`Page
`
`Relevant Background and Experience............................................................2
`
`Relevant Technology Background .................................................................3
`
`1.
`
`Overview of Flash Memory .................................................................3
`
`Overview of the ’490 Patent...........................................................................6
`
`Level of Ordinary Skill in the Art ................................................................11
`
`Claim Construction.......................................................................................12
`
`1.
`
`“metablock”........................................................................................12
`
`Challenge #1: Claims 94-97, 102, and 104-105 are Anticipated by
`Wells .............................................................................................................14
`
`2. Wells anticipates claim 94..................................................................16
`
`3. Wells anticipates claim 95..................................................................25
`
`4. Wells anticipates claim 96..................................................................26
`
`5. Wells anticipates claim 97..................................................................26
`
`6. Wells anticipates claim 102................................................................27
`
`7. Wells anticipates claim 104................................................................28
`
`8. Wells anticipates claim 105................................................................29
`
`Challenge #2: Claims 98, 100, and 103 are Rendered Obvious by
`Wells and Niijima.........................................................................................31
`
`Challenge #3 Claims 66, 68, and 70 Are Rendered Obvious by Wells
`and the Knowledge of One of Ordinary Skill in the Art ..............................32
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`F.
`
`G.
`
`H.
`
`- i -
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0002
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`
`
`TABLE OF CONTENTS
`(continued)
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`Page
`
`1.
`
`2.
`
`3.
`
`Claim 66 is rendered obvious by Wells and the knowledge of
`one of ordinary skill in the art ............................................................32
`
`Claim 68 is rendered obvious by Wells and the knowledge of
`one of ordinary skill in the art ............................................................33
`
`Claim 70 is rendered obvious by Wells and the knowledge of
`one of ordinary skill in the art ............................................................34
`
`Challenge #4 (Relative Order of Programming): Claim 67 Is
`Rendered Obvious by Wells, the Knowledge of One of Ordinary Skill
`in the Art, and Niijima..................................................................................34
`
`Challenge #5 (Logical Block Number and Page Offset Claims):
`Claims 69, 99, and 101 are Rendered Obvious by Wells, the
`Knowledge of One of Ordinary Skill in the Art, and the Admitted
`Prior Art or Miyauchi ...................................................................................36
`
`Challenge #6 (Multi-Bit Claims): Claims 71 and 106 are Rendered
`Obvious by Wells, the Knowledge of One of Ordinary Skill in the Art,
`and the Admitted Prior Art or Cappelletti ....................................................40
`
`Challenge #7 (Enclosure Card): Claim 72 is Rendered Obvious by
`Wells, , the Knowledge of One of Ordinary Skill in the Art, and the
`Admitted Prior Art or the PC Card Standard................................................42
`
`Challenge #8 (Metablock): If the Board Rejects Any of Challenges
`#1-7 Based on the “Metablock” Element, Then Such Claims Are
`Rendered Obvious by Wells and the Knowledge of One of Ordinary
`Skill in the Art, Hazen, or Dipert..................................................................44
`
`I.
`
`J.
`
`K.
`
`L.
`
`M.
`
`- ii -
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0003
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`
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`Exhibit Number Description
`
`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`U.S. Patent No. U.S. Patent 7,818,490 (“the ’490
`
`patent”)
`
`File History for U.S. Patent 7,818,490
`
`Declaration of Dr. Vivek Subramanian
`
`(“Subramanian Decl.”)
`
`CV of Dr. Vivek Subramanian
`
`U.S. Patent 5,822,781 (“Wells”)
`
`U.S. Patent No. 5,457,658 (Niijima)
`
`U.S. Patent No. 5,627,783 (“Miyauchi”)
`
`Flash Memories, edited by Cappelletti, et al (1999)
`
`(“Cappelletti”)
`
`PC Card Standard, Volumes 1 and 3 (1999) (“PC
`
`Card Standard”)
`
`PCT WO 99/35650 (“Hazen”)
`
`Designing With Flash Memory, Brian Dipert and
`
`Markus Levy (1994) (“Dipert”)
`
`iii
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0004
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`
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
`
`1.
`
`2.
`
`I, Vivek Subramanian, declare as follows:
`
`I am making this Declaration at the request of Petitioner Apple Inc.
`
`regarding its Petition for Inter Partes Review of U.S. Patent No. 7,818,490 (the
`
`“’490 patent”).
`
`3.
`
`I am being compensated for my work at my standard rate of $550 per
`
`hour. My compensation does not depend on the outcome of this proceeding.
`
`4.
`
`As part of my analysis, I reviewed the following materials:
`
`Exhibit 1001
`
`U.S. Patent No. U.S. Patent 7,818,490
`
`Exhibit 1002
`
`File History for U.S. Patent 7,818,490
`
`Exhibit 1005
`
`U.S. Patent 5,822,781 (“Wells”)
`
`Exhibit 1006
`
`U.S. Patent No. 5,457,658 (Niijima)
`
`Exhibit 1007
`
`U.S. Patent No. 5,627,783 (“Miyauchi”)
`
`Exhibit 1008
`
`Flash Memories, edited by Cappelletti, et al
`
`(1999) (“Cappelletti”)
`
`Exhibit 1009
`
`PC Card Standard, Volumes 1 and 3 (1999)
`
`(“PC Card Standard”)
`
`Exhibit 1010
`
`PCT WO 99/35650 (“Hazen”)
`
`Exhibit 1011
`
`Designing With Flash Memory, Brian
`
`Dipert and Markus Levy (1994) (“Dipert”)
`
`1
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0005
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`
`
`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
`
`A.
`
`5.
`
`Relevant Background and Experience
`
`My background and experience is summarized in my curriculum
`
`vitae, a true and correct copy of which is submitted as Exhibit 1004. Some of the
`
`relevant points are described below, as well.
`
`6.
`
`I received a B.S. in electrical engineering from Louisiana State
`
`University in 1994, an M.S. in electrical engineering from Stanford University in
`
`1996, and a Ph.D. in electrical engineering from Stanford University in 1998.
`
`7.
`
`In 1998, I co-founded Matrix Semiconductor, Inc. to develop high
`
`density memory technology.
`
`8.
`
`I have been teaching in the Electrical Engineering and Computer
`
`Sciences Department at the University of California, Berkeley since 2000. I was
`
`an Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to
`
`2011, and a Professor from 2011 to the present.
`
`9.
`
`I have been an adjunct professor at the Sunchon National University
`
`in Sunchon, Korea since 2009, leading research in printed electronics.
`
`10.
`
`I have been an independent consultant in the semiconductor industry
`
`since 2000, focusing on memory technology, flexible electronics, and RFID
`
`technology.
`
`2
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0006
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`
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`11.
`
`I have published more than 200 technical papers in journals and at
`
`conferences.
`
`12.
`
`I am a named inventor on over 30 U.S. Patents, many of which are in
`
`the field of memory design.
`
`B.
`
`Relevant Technology Background
`
`1.
`
`Overview of Flash Memory
`
`13. A flash memory device contains one or more arrays of non-volatile
`
`memory cells. (Ex. 1001 at 1:29-40). Non-volatile memory cells retain their data
`
`when power is removed. (Id.) However, unlike most types of non-volatile
`
`memory cells (such as ROM and EPROM cells), flash memory cells are
`
`electrically reprogrammable. (Id.). The typical flash memory architecture used to
`
`achieve non-volatility and reprogrammability has several functional limitations.
`
`For example, once a flash memory cell is programmed with data, the cell must be
`
`erased before that cell can be reprogrammed with new data. (Id.). Further, if it
`
`were desired to erase the cells used in flash memory on a cell-by-cell basis,
`
`extensive circuitry would be required to erase such flash memory cells
`
`individually. (Ex. 1001 at 1:41-58). Therefore, instead of erasing individual cells,
`
`the typical flash memory has large groups of cells arranged into erasable blocks, a
`
`block containing the smallest number of cells that can be erased at one time. (Id.).
`
`It is desirable to read or write data in units smaller than the size of a block. (Ex.
`
`3
`
`APPLE INC.
`EXHIBIT 1003 - PAGE 0007
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`
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`1001 at 1:51-58). Therefore, blocks are further partitioned into pages, a page
`
`containing the smallest number of cells that can be read or written at one time.
`
`(Id.). Also, in some flash memories, the pages within each block can only be
`
`programmed in a physically sequential manner. (Ex. 1001 at 7:1-4).
`
`14.
`
`In addition to user data, each page in a flash memory can contain a set
`
`of overhead data fields and flags to store information related to the user data.
`
`(Ex.
`
`1001 at 1:41-58, 5:53-55). For example, each time user data is written to a page, a
`
`logical block number (“LBN”) indicating the data’s logical address can be
`
`recorded in a data field within the page. (Ex. 1001 at 5:49-57, 6:6-25, and 6:44-
`
`57). .
`
`4
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0008
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`(Ex. 1001 at Figure 6).
`
`15.
`
`The block and page architecture of the typical flash memory presents
`
`several challenges when updating user data. In the ideal case, the data in all pages
`
`of a block are modified together and written to the pages of an erased block. (Ex.
`
`1001 at 2:4-8). However, a partial block update is more common, in which the
`
`data in only some pages within a block are updated, while the data in the remaining
`
`pages is unchanged. (Ex. 1001 at 2:8-12). At least two techniques to perform a
`
`partial block update in a flash memory device were well known when the ’490
`
`patent was filed and are acknowledged as prior art by the ’490 patent itself. (Ex.
`
`1001 at 2:14-28). The first technique involves writing the updated data into a new,
`
`erased block. (Id.) The system then copies the unchanged data from the old block
`
`into the new block. (Id.). Finally, the system erases the old block. (Id.). This
`
`technique is inefficient because it requires copying unchanged pages of data to a
`
`different block. (Id.).
`
`16.
`
`The second known partial block update technique also involves
`
`writing the data of the updated pages to a corresponding number of pages in a new
`
`block. (Ex. 1001 at 2:21-28). However, instead of copying the unchanged pages
`
`of data to the new block, the flags of the pages in the original block which are
`
`being updated are modified to indicate that those pages contain superseded data.
`
`(Id.). When reading the data, the updated data from pages of the new block are
`
`5
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0009
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`combined with the unchanged data from the pages of the original block that are not
`
`flagged as superseded. (Id.). While the second technique avoids copying the
`
`unchanged data to the new block, it still requires updating a flag in each
`
`superseded page. (Id.).
`
`C.
`
`17.
`
`Overview of the ’490 Patent
`
`The ’490 patent relates to management and organization of a flash
`
`memory system. It recognizes that typical flash systems can write data to
`
`individual pages but can only erase entire blocks and not individual pages. In the
`
`Admitted Prior Art discussed in the ’490 patent, if the host wrote data to Logical
`
`Addresses (LA) 1, 2, 3, and 4, the data might be stored in pages as follows:
`
`(Ex. 1001 at 5:45-48).
`
`18. At a later time, if the host wished to update one of the pages, such as
`
`LA4, but not all of the pages, the Admitted Prior Art system discussed in the ’490
`
`6
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0010
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`would write the updated page in a new block, copy the unchanged data from the
`
`old block to the new block, and then erase the old block, as shown below:
`
`7
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0011
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`(Ex. 1001 at Figure 4; 5:45-67).
`
`19.
`
`This was inefficient and time-consuming. The ’490 patent recognizes
`
`the limitations of the Admitted Prior Art and offers a solution whereby the old
`
`block is maintained and the updated page is written to a new block. This means
`
`that the old page and updated page both will be associated with the same logical
`
`address (e.g., LA4). The ’490 patent discloses a few different ways to keep track
`
`of which page is the most recent page. For example, the system can include a
`
`timestamp with each page or keep track of the relative order in which each page
`
`was written. The ’490 patent solution is illustrated below:
`
`8
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0012
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`(Ex. 1001 at Figure 8; 8:64-9:5).
`
`20.
`
`The ’490 patent provides an additional improvement. It creates a
`
`“metablock” by selecting one block from each sub-array and treating them as a
`
`unit. For example, the system could perform an erase on the entire metablock at
`
`one time. This is an organizational technique shown below:
`
`9
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0013
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`(Ex. 1001 at Figure 15; 11:53-22:12).
`
`21.
`
`The ’490 patent discloses that when pages are updated within a
`
`metablock, the updated pages can be written to a new block in the same sub-array,
`
`as shown below:
`
`10
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0014
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`
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`(Ex. 1001 at Figure 15, 12:6-12).
`
`22.
`
`The ’490 patent also discloses an embodiment where updates to any
`
`page in the metablock are written to the same update block in one of the sub-
`
`arrays, as shown below:
`
`(Ex. 1001 at Figure 16, 12:27-47).
`
`23. As will discussed below, all of these alleged improvements of the
`
`’490 patent are found in the prior art.
`
`D.
`
`24.
`
`Level of Ordinary Skill in the Art
`
`In my opinion, a person of ordinary skill in the relevant art at the time
`
`of the ’490 patent would have had Master’s Degree or equivalent in electrical
`
`engineering or a related field and two years of experience in memory technology or
`
`the equivalent.
`
`11
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0015
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`
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
`
`E.
`
`Claim Construction
`
`25. My understanding is that in an IPR proceeding, the Board will
`
`construe the claims using the broadest reasonable interpretation standard and that
`
`this standard is different than the one used by Courts in patent litigation.
`
`1.
`
`“metablock”
`
`26.
`
`I understand that, the parties have not construed the term “metablock”
`
`in the Related Litigation, but that they have construed the larger phrase “at least
`
`first and second of the plurality of blocks logically linked together as a metablock.”
`
`My understanding is that based on Patent Owner’s construction of that larger
`
`phrase, its apparent construction of “metablock” is: “two or more blocks
`
`positioned in separate units of one or more memory chips for programming and
`
`reading together in parallel as part of a single operation.” I also understand that
`
`Petitioner contends that “metablock” should be construed as: “set of blocks
`
`associated together such that during operation they are programmed, read, or
`
`erased together as a unit.” I agree with Petitioner’s construction.
`
`27.
`
`Petitioner’s construction is consistent with the claims and
`
`specification, which refer to the metablock as a set of blocks that are grouped
`
`together for an operation, such as a program, read, or erase operation. It is not
`
`necessary that the blocks of a metablock be programmed together and read
`
`together as argued by Patent Owner.
`
`12
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0016
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
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`28.
`
`For example, the Abstract describes metablocks and does not suggest
`
`that programming and reading must happen to each block concurrently: “This
`
`technique is also applied to metablocks that include one block from each of several
`
`different units of a memory array, by directing all page updates to a single unused
`
`block in one of the units.” (Ex. 1001 at Abstract). The metablock is simply an
`
`organizational unit.
`
`29.
`
`The claims also support Petitioner’s view. For example, claim 66
`
`indicates that the blocks of the metablock are erased together, but does not indicate
`
`that the blocks of the metablock are read together or programmed together. (Ex.
`
`1001 at claim 66). Similarly, claim 94 indicates that the blocks of the metablock
`
`are programmed together and erased together (“…memory storage elements are
`
`erasable together and whose pages…are programmable together in parallel…”) but
`
`does not indicate that the read operation must occur from both blocks together:
`
`“reading data of the file from the first and second plurality of pages.” (Ex. 1001 at
`
`claim 94). These claims indicate that a metablock does not need to support parallel
`
`erase operations, parallel programming operations, and parallel erase operations.
`
`Only one of those is required.
`
`30. Moreover, Petitioner’s construction is broader than Patent Owner’s
`
`construction and is a reasonable construction and therefore is more suitable as the
`
`broadest reasonable construction.
`
`13
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0017
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`U.S. Patent No. 7,818,490
`Petition For Inter Partes Review
`
`F.
`
`1.
`
`Challenge #1: Claims 94-97, 102, and 104-105 are Anticipated by
`Wells.
`
`Overview of Wells
`
`31. Wells was filed on October 30, 1992, and issued on October 13, 1998.
`
`(Ex. 1005 at cover page). The earliest potential priority date for the ’490 patent is
`
`January 19, 2001. (Ex. 1001 at cover page) Wells therefore constitutes prior art
`
`against the ’490 patent under 35 U.S.C. Section 102(a), (b), and (e). Wells is
`
`contained within the file history of the ’490 along with over 110 other prior art
`
`references and hundreds of pages of filings from an ITC proceeding involving a
`
`grandparent of the ’490 patent. (Ex. 1005 at pages 1-2). Wells was not discussed
`
`by the Examiner or Applicant during prosecution of the ’490 patent. (Ex. 1002).
`
`32. Wells discloses all of the alleged points of novelty of the ’490 patent.
`
`Wells discloses the use of numerous flash memory chips, with each chip divided
`
`into blocks and each block divided into sectors. (Ex. 1005 at Figures 2-3; 4:40-
`
`62). Wells organizes the chips into pairs and provides an example involving 30
`
`different flash chips divided into pairs, with an exemplary chip pair (item 66)
`
`shown in Figure 2:
`
`14
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0018
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`U.S. Patent No. 7,818,490
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`(Ex. 1005 at Figure 2; 4:41-62). Each chip contains 16 blocks, and each block
`
`contains multiple sectors. (Ex. 1005 at Figure 2). Blocks from each chip pair are
`
`grouped together as a unit. For example, in Figure 2, Block 0 from chip 68 and
`
`Block 0 from chip 70 are treated together as block 80. (Ex. 1005 at Figure 2; 4:57-
`
`67). For convenience, this Petition will refer to this logical grouping of blocks
`
`from a chip pair, such as block 80, as a “Block Pair.” The Block Pair is a
`
`metablock under the claims of the ’490 patent. Each Block Pair can be erased as a
`
`unit, and each block in the Block Pair can be programmed concurrently.
`
`Moreover, when data in a sector within a block is updated, the updated data is
`
`written to a new sector associated with the same logical address as the old sector.
`
`(Ex. 1005 at 4:21-53; 14:66-15:13; 32:63-65).
`
`15
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`APPLE INC.
`EXHIBIT 1003 - PAGE 0019
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`U.S. Patent No. 7,818,490
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`2. Wells anticipates claim 94
`
`33.
`
`The preamble of claim 94 states: “In a re-programmable non-volatile
`
`semiconductor memory system having a plurality of sub-arrays of memory storage
`
`elements in which programming operations may be performed independently, the
`
`sub-arrays individually being divided into a plurality of blocks of memory storage
`
`elements that are erasable together as a unit, the plurality of blocks individually
`
`being divided into a plurality of pages of memory storage elements that are
`
`programmable together, a method of operating the memory system, comprising:”
`
`34.
`
`To the extent this preamble is limiting, Wells discloses the preamble.
`
`Wells discloses a plurality of sub-arrays of memory storage elements in which
`
`programming operations may be performed independently Each memory storage
`
`element is a re-programmable non-volatile semiconductor devices.” (Exhibit 1005
`
`at Abstract, Figures 1-2). For example, Wells provides an example of a system
`
`with 30 flash memory chips, with each chip comprising a sub-array. (Ex. 1005 at
`
`4:40-51). The charge storage elements within individual sub-arrays are
`
`programmable independently in units called “sectors,” where each block comprises
`
`16 sectors. (Figure 2; 4:58-62). The “sector” in Wells is the same as the “page” in
`
`the ’490 patent. Figure 2 also discloses a logical block (such as block 80), which
`
`comprises a block from two sub-arrays. (Figure 2). The logical block is erasable
`
`as a unit. (Ex. 1005 at 32:63-65).
`
`16
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`EXHIBIT 1003 - PAGE 0020
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`U.S. Patent No. 7,818,490
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`35.
`
`The next element of claim 94 states: “linking together blocks within
`
`the plurality of sub-arrays to form a plurality of metablocks whose memory storage
`
`elements are erasable together and whose pages of memory storage elements
`
`within the linked blocks are programmable together in parallel.”
`
`36. Wells discloses this element. The Block Pair shown in Figure 2,
`
`excerpted above, is a logical unit comprising two blocks from different chips that
`
`are logically linked together as a metablock and are positioned in different sub-
`
`arrays. Figure 2 shows two exemplary sub-arrays (High Chip 68 and Low Chip
`
`70). Each of the plurality of blocks is divided into a plurality of pages of flash
`
`cells—which Wells calls a “sector”—that are programmable together. (Ex. 1005
`
`at 4:51-53; 32:63-65). For example, Wells states: “Solid state disk controller 64 is
`
`thus able to treat each chip pair as a single 16 bit-wide memory device. Word-
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`wide input and output gives solid state disk 60 a speed advantage compared to
`
`magnetic drives, which use serial bit stream I/O.” (Ex. 1005 at 4:53-57). This
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`disclosure indicates to one of ordinary skill in the art that each Block Pair will be
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`programmed together, read together, and erased together, as if it were a block in a
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`single device.
`
`37.
`
`The next element of claim 94 states: “programming pages of original
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`data of a file into individual ones of an erased first plurality of pages in a first
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`plurality of blocks forming a first metablock, the pages of original data having
`
`logical addresses associated therewith.”
`
`38. Wells discloses this element. It discloses writing data corresponding
`
`to a sector number (which is a logical address) to a chip pair, block number, and
`
`header pointer to identify the specific sector. (Figures 3-4; 5:1-12). For example,
`
`Wells states:
`
`The data structure of block 80 includes block sector
`translation table 84 and data space 86. Block sector
`translation table 84 stores headers. A header is a block of
`information about one logical sector number and its
`associated data. As used herein a logical sector number
`(LSN) refers to a sector number stored within a BSTT. A
`sector number is a sector identifier received from CPU
`52, which the CPU believes corresponds to a fixed
`physical location. However, as a result of the write policy
`used by solid state disk 60, an LSN does not correspond
`to a fixed physical location. Also as a result of the write
`policy used, several headers and LSNs may correspond to
`a single sector number.
`(Ex. 1005 at 5:1-14).
`
`39. Wells discloses the use of files comprising pages of data with
`
`associate logical addresses. For example, Wells states: “A typical user file stored
`
`on a magnetic disk drive occupies many sectors, randomly located on the surface
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`of the disk drive. A file allocation table (FAT) allows location of each sector of the
`
`file by storing a chain of pointers for the file. Each pointer points to the next sector
`
`of the file.” (Ex. 1005 at 1:22-26). Wells further states: “The next time the same
`
`process attempts to write a sector, the allocation algorithm first examines the last
`
`block allocated to that process. This helps keep related data "files" in contiguous
`
`memory space and helps reduce the possibility of data fragmentation.” (Ex. 1005
`
`at 17:21-26).
`
`40.
`
`The next element of claim 94 states: “thereafter programming one or
`
`more pages of updated data of the file into individual ones of an erased second
`
`plurality of pages in at least a second block, the pages of updated data having
`
`logical addresses associated therewith, wherein the logical addresses associated
`
`with the pages of updated data programmed into the second plurality of pages are
`
`common with those associated with the pages of original data programmed into the
`
`first plurality of pages.”
`
`41. Wells discloses this element. When the data in part of a block is
`
`updated, the system writes the updated version of the data into a new location.
`
`Wells states:
`
`In step 246, microprocessor 92 determines
`whether a previous header with the same LSN should
`be marked dirty. Microprocessor 92 makes this
`determination based upon the information retrieved by
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`the seek of step 238. If a header was located,
`microprocessor 92 proceeds to step 247 to mark that
`header dirty. Afterward, microprocessor 92 advances to
`step 248 to determine whether the previous header was
`marked dirty or whether the task was cached. If the task
`was not cached, microprocessor 92 advances to 250.
`Otherwise, microprocessor 92 branches to step 249.
`Because the mark dirty task was cached, there will be
`two headers with the same LSN at the end of the current
`write. To distinguish the valid data after power-loss, the
`revision number for the LSN associated with the most
`current version is incremented in step 249.
`Microprocessor 92 then proceeds to step 250.
`With step 250, microprocessor 92 begins the process of
`writing the new version of the sector data within FLASH
`array 62. Microprocessor 92 allocates sufficient free
`memory within FLASH array 62 to store the sector of
`data and header. This is an involved process that will be
`described in detail later. Suffice it to say that allocation
`of memory requires locating sufficient memory within
`data space 86 of a block and marking that memory space
`as reserved. Microprocessor 92 then exits to step 252.
`Microprocessor 92 completes the writing of the header in
`steps 252 and 254. First, in step 252, a CRC is generated
`for the header, which excludes the dirty bits and revision
`numbers because they may be changed in the course of
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`events. Afterward, in step 254, the CRC, attribute word
`and LSN are written into BSTT 84. The LSN is set equal
`to SNi.
`Microprocessor 92 finally writes the sector data
`into data space reserved in step 256. An error correction
`code, ECC, is also written with the data.
`The new version of the sector data safely written, in step
`258 microprocessor 92 updates sector header
`translation table 94 so that it points to the most recent
`version of the sector data associated with the sector
`number.
`(Ex. 1005 at 14:66-15:36) (emphasis added). As described above, Wells discloses
`
`the use of files comprising pages of data with associate logical addresses. (Ex.
`
`1005 at 1:22-26, 17:21-26).
`
`42. At least some of the time, the updated data in Wells will be written
`
`into a block outside of the metablock (the first block and second block). For
`
`example, if the metablock is full, the updated data necessarily will be written to a
`
`block other than the first block and second block. In addition, even if the
`
`metablock is not full, the system follows a dynamic block selection process.
`
`Wells discloses at least two algorithms for determining which block should be used
`
`for a write operation (including write operations involving updated data), and
`
`under each approach, a block other than the Block Pair will be chosen 15/16 of the
`
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`time (as there are 16 total Block Pairs), all else being equal. (Ex. 1005 at Figure
`
`11, 17:6-50).
`
`43.
`
`The next element of claim 94 states: “wherein programming the
`
`second plurality of pages additionally allows programming the updated version of
`
`the original data in those of the second plurality of pages of memory storage
`
`elements that have different offset positions within the at least the second block
`
`than the offset positions of the first plurality of pages within the first plurality of
`
`blocks that contain pages of original data with common logical addresses
`
`associated therewith, and.”
`
`44. Wells discloses this element. As described previously, Wells follows
`
`a block selection algorithm. The algorithm ensures that a block is selected that
`
`contains sufficient space for the programming action. (Ex. 1005 at 18:38-41).
`
`Wells discloses that data sectors are programmed sequentially into a chosen block:
`
`“In contrast to BSTT 84, data space 86 grows upward. The first sector of data
`
`written into block 80 is written into the bottom of data space 86. The next sector of
`
`data written into data space 86 is written immediately above the previous sector.
`
`For example, the data associated with LSN2 is located within a lower range of
`
`addresses than the data associated with LSN1.” (Ex. 1005 at 6:30-36). Therefore,
`
`programmed data sectors are “butted up against data for another sector in data
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`space.” (Ex. 1005 at 6:13-14). Further, Wells discloses, with reference to
`
`Figure 12:
`
`Eventually, a block with enough space to store the sector
`of data will be identified and microprocessor 92 will
`reach step 1262. Allocation of memory space for the
`sector of data begins in earnest by identifying the next
`available header in the BSTT 84 of the Most Free
`Block. The appropriate block sector offset for the sector
`is then written into that header in step 1264. Afterward,
`the total amount of free flash in the array, in the Most
`Free Chip and the Most Free Block are decreased by the
`size of the sector. Finally, in step 1266 microprocessor 92
`indicates the chip pair, block and offset to the header now
`associated with the sector of data to be written.
`(Ex. 1005 at 22:13-24).
`
`45.
`
`Thus, in the embodiment of Figure 12, the system identifies the ideal
`
`block for the writing of the new data, and the new data is then written into the next
`
`available location within the block. Wells places no restraint on which sector
`
`should be used for the updated data. In Wells, a block contains 128 KB, and each
`
`sector is 512 bytes, which means that each block contains 250 sectors. Thus, all
`
`else being equal, the updated data will be at a different offset position than the
`
`original data 249/250 of the time.
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`46.
`
`If not expressly or inherently taught in Wells, one of ordinary skill in
`
`the art would immediately understand that this element inevitably would be
`
`practiced by the combined system during normal operations.
`
`47.
`
`The next element of claim 94 states: “thereafter reading data of the
`
`file from the first and second plurality of pages.”
`
`48. Wells discloses this element. Wells describes the read process as
`
`follows:
`
`Briefly described, reading a sector is a three step process.
`First, SHTT 94 is searched for a pointer to the header
`associated with the sector number. Second, the header is
`located and its
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