(19; United States
`(12) Patent Application Publication (10) Pub. No.: US 2003x0048249 A1
`Sekido et al.
`(43) Pub. Date:
`Mar. 13, 2003
`
`US 2()[l3[)(]4824-9A1
`
`(54) DRIVE cmcurr [)EV[CtC FOR DISPLAY
`DEVICE, AND DISPLAY DEVICE USING THE
`SAME
`
`(75)
`
`Inventors: Satoshi Sekido, Kawasaki (JP);
`Yasutake Furukoshi, Kawasaki (JP);
`Syouielii Fukutoku, Kawasaki (JP)
`
`Correspondence Address:
`Patrick G_ Burns’ Esq.
`GREER, BURNS & CRAIN, LTD.
`Suite 2500
`300 South Waeker m.
`Cllicag[’’ 1-L
`
`(73) Asfiigncc: FUJITSU IJMITEI)
`
`(31) Appl‘ NO‘,
`
`l0fl02,264
`
`(23)
`
`Filed:
`
`Man 20, 2002
`
`(30)
`
`Foreign Application Priority [mm
`
`Sep, 12, 2001
`
`(JP) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,, 2[I0'l—276[l9t']
`
`p..bii.;au0n Classification
`
`Int. Cl.’ ..................................................... ..G09G 3,66
`(51)
`(52) U.S. (:1.
`.............................................................. .. 345193
`
`(57)
`
`ABSTRACT
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`A drive circuit device for a display (ILVILL which drives a
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`when a rcar—stage drive circuit device starts receiving, starts
`uulpulliiig oi‘ a propagatioii signal iiieludiiig at least one of
`the clock signal, data signal and control signal
`to the
`rcar—stage drive circuit device. Consequently,
`the power
`consuriiptiori required for supplying these signals and the
`generated amount oi" electromagnetic waves resulting from
`the signal supply can be suppressed,
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`Page 1 of 16
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`

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`Patent Application Publication Mar. 13, 2003 Sheet 1 of 8
`
`US 2003/0048249 A1
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`FIG. 1
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`FIG. 2
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`Page 2 of 16
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`Patent Application Publication Mar. 13, 2003 Sheet 2 of 8
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`Patent Application Publication Mar. 13, 2003 Sheet 3 of 8
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`Patent Application Publication Mar. 13, 2003 Sheet 4 of 8
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`Patent Application Publication Mar. 13, 2003 Sheet 6 of 8
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`US 2003/0048249 A1
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`Page 7 of 16
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`

`
`Patent Application Publication Mar. 13, 2003 Sheet 7 of 8
`
`US 2003/0048249 A1
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`Page 8 of 16
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`

`
`Patent Application Publication Mar. 13, 2003 Sheet 8 of 8
`
`US 2003/0048249 A1
`
`FIG. 9
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`Page 9 of 16
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`

`
`US 2003/0048249 A1
`
`Mar. 13, 2003
`
`DRIVE CIRCUIT DICVICIC FOR DISPLAY DICVICIC,
`AND I)ISl‘I.AY DEVICE USING THE SAME
`
`BACKGROUND O1’ TIII.-' INVIENTION
`
`[0001]
`
`1. Field of the Invention
`
`[0002] The present invention relates generally to a drive
`circuit device for a display device such as a liquid crystal
`display device, and more particularly,
`to a drive circuit
`device that can reduce power consumption and suppress
`occurrence of electromagnetic waves.
`
`[0003]
`
`2. Description of the Related Art
`
`[0004] The liquid crystal display device is now widely
`being used for the monitor screen of a computer, etc.,
`because of its space-saving feature. In recent years, a larger
`type is further being called for, and development of structure
`to meet the requirement is increasingly being made.
`
`liquid
`a
`the liq11id crystal display devices,
`[0005] Of
`crystal display device of an active-matrix type has pixels in
`a matrix arrangement, using active elements, like 'l‘l~'l‘s (tin
`film transistors). This liquid crystal display device has pixel
`electrodes and a common electrode on a liquid crystal
`display panel or substrate, and a liquid crystal layer between
`them. l-‘urther, the liquid crystal display panel has source bus
`lines and gate bus lines, which cross each other, and Tl"l's
`provided at the crossing positions. And, by driving the gate
`bus lines to cause the 'I'l-‘Ts of the pixels located in the row
`direction to a conductive state, and applying voltage corre-
`sponding to the half tone of the pixel to each source bus line,
`the voltage corresponding to the half tone of the pixel is
`applied between the pixel electrode and the common elec-
`trode. As the result of the application of voltage, the liquid
`crystal layer between the pixel electrode and the common
`electrode has a transmission factor corresponding to the
`applied voltage,
`thereby allowing a reproduction of an
`expected half tone to be possible.
`
`In order to perform such display operations, a gate
`[0006]
`driver which sequentially drives the gate bus lines, and a
`source driver which drives the source bus lilies si111ulta—
`neously with the voltage corresponding to the displayed
`data, are connected to the liquid crystal display panel. The
`gate driver and the source driver will be embodied by an
`integrated circuit device, and each of the drivers drives a
`plurality of gate bus lines or a plurality of source bus lines,
`respectively. Therefore, in order to drive many gate bus lines
`and the source bus lines on the display circuit board, a
`plurality of the gate drivers and source drivers must be
`connected to the area around the liquid crystal display panel.
`
`[0007] With the requirement for space saving, the down-
`sizing of the liquid crystal display device seems to be the
`current trend, but, on the other hand, to meet the request for
`larger size ofthe monitor screen, a space for packing the gate
`driver and the source driver is becoming limited. With this
`limitation, signal lines for the data signal, clock signal or
`control signal to be supplied to the plurality of the source
`drivers and the gate drivers are formed on an LCD panel, on
`which Tl-"I" source bus lines and gate bus lines for the liquid
`crystal display panel are installed.
`
`[0008] Unlike a printed circuit board, the signal lines to be
`formed on the liquid crystal display panel has relatively
`higher resistance and capacitance compared with a printed
`
`circuit board, and cannot be covered with a ground wiring
`layer. For this reason, when pulse signal with high frequency
`is applied to these signal lines, a lot of power is consumed
`to drive these signal
`lines, and a strong electromagnetic
`wave will be sent out along with the driving. Especially,
`along the upsizing of the screen, the number of the driver [cs
`will be increased, and further, the signal lines for propagat-
`ing the data signal, clock signal, or control signal becomes
`longer, so that the power consumption and occurrence of
`electromagnetic wave is considerably increased.
`
`SUMMARY OF Tl-Il:i INVENTION
`
`It is therefore the object of the present invention to
`[0009]
`provide a drive circuit device for a display device that can
`suppress power consumption and occurrence of electromag-
`netic waves, and a display device using the same.
`
`In order to attain the above objects, an aspect ofthe
`[0010]
`invention provides a drive circuit device for
`a
`present
`display device which drives a plurality of source bus lines
`provided on a display panel, the drive circuit device com-
`prising: a driver unit that receives a clock signal, a data
`signal and a control signal, and sequentially fetches the data
`signal, and generates drive signals for the source bus lines in
`accordance to the fetched data signal; and a gate unit that,
`after elapse of specified time from the reception of the driver
`u11it, and at a timing when a rear-stage drive circuit device
`starts receiving, starts outputting of a propagation signal
`including at least one of the clock signal, data signal and
`control signal to the rear-stage drive circuit device.
`
`In order to achieve the above objects, another
`[0011]
`aspect of the present
`invention provides a drive circuit
`device for a display device which sequentially drives a
`plurality of gate bus lines provided on a display panel, the
`drive circuit device comprising: a driver unit that receives a
`clock signal and a control signal, and sequentially generates
`a drive signal for the gate bus lines, in synchronism with the
`clock signal; and a gate unit that, after elapse of specified
`time from the reception of the driver unit. and at a timing
`when a rear-stage drive circuit device starts receiving, starts
`outputting of a propagation signal including at least one of
`the clock signal and control signal to the rear-stage drive
`circuit device.
`
`[0012] According to the present invention, a drive circuit
`device on a front stage receives the clock signal, data signal
`and control signal for generating the drive signal, and output
`at least one signal of these signals at a timing when a drive
`circuit device on a rear stage starts receiving these signals.
`Therefore, when a plurality of drive circuit devices are
`provided in serial on a display panel, and a clock signal, data
`signal, control signal, etc. are to be sequentially received by
`the plurality of the drive circuit devices, these signals will
`not be supplied to any drive circuit device on a rear stage of
`the drive circuit device which is currently receiving signals.
`Consequently, the power consumption required for supply-
`ing thesc signals and the generated amount of electromag-
`netic waves resulting from the signal supply can be sup-
`pressed, compared with the case of supplying these signals
`to all drive circuit devices.
`
`in the display
`In a more preferred embodiment,
`[0013]
`device, a plurality of the drive circuit devices are connected
`in serial, and the drive circuit devices are connected to a
`display panel. liven if the display panel becomes larger, and
`
`Page 10 of 16
`
`

`
`US 2003/0048249 Al
`
`Mar. 13, 2003
`
`the power
`the number of drive circuit devices increases,
`consumption and generated amount of electromagnetic
`waves can be suppressed, because propagating signals, like
`a clock signal, will only be supplied to the drive circuit
`devices, from t.he initial stage through the necessary stage
`according to the drive circuit devices as described above.
`
`BRIEF Dl:LSCRIl"I"ION OF THE DRAVVINGS
`
`[0014: FIG. I shows a configuration of a liquid crystal
`display device in the embodiment of the present invention;
`
`[0015] FIG. 2 shows an enlarged view of the joint section
`between a drive circuit device circuit board 2 and a display
`panel 1;
`
`[0016] FIG. 3 shows a conliguration of a drive circuit
`device and a display panel in the embodiment of the present
`invention;
`
`[001’?': FIG. 4 is an operation—timing chart of the drive
`circuit device shown in FIG. 3;
`
`[0018] FIG. 5 shows a configuration of a source side drive
`circuit device;
`
`[0019' FIG. 6 shows a configuration of at data register in
`the source side drive circuit device;
`
`[0020] FIG. 7 is an operation-timing chart of the source
`side drive circuit device;
`
`[002l: FIG. 8 shows a configuration of a gate side drive
`circ1.1it device; and
`
`[0022: FIG. 9 is an operation flowchart of the gate side
`drive circuit device.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`l_i.mbodiments of the present invention will now be
`[0023]
`described with reference to the drawings. It is however to be
`understood that the protective scope of the present invention
`is not limited to the embodiments shown below, but that it
`covers up to the invention defined by claims and its equiva-
`lents.
`
`[0024] FIG. 1 shows a configuration of a liquid crystal
`display device in the embodiment. A display panel "I has a
`TI-‘"1" substrate forming 'I'Ii'ls, a common electrode substrate
`forming a comnion electrode, and a liquid crystal layer to be
`provided between them. Out of these components, a con-
`figuration of the 'I"l~"I" substrate is shown in FIG- "I. That is
`to say, on the display panel 1, pixel clectrodes3 are arranged
`in a matrix pattern, and corresponding to this matrix arrange-
`ment, a plurality of gate bus lines 5 and a plurality of source
`bus lines 6, crossing the gate bus lines, are provided, and
`further, 'l‘I~"ls 4 are provided at the intersections respectively.
`And, when the gate bits line Sis driven, the TFT4 connected
`to the gate bus line and located in the row direction will be
`brought into conduction, and the voltage applied to each of
`the source bus lines 6 will be supplied to the pixel electrode
`3. As the result of this operation, the voltage corresponding
`to the display data will be applied to the liquid crystal layer
`between the common electrode, though not noted in the
`drawing, and the respective pixel electrodes 3, and the liquid
`crystal
`layer can demonstrate an expected transmission
`factor.
`
`[0025] To the peripheral area ofthe display panel 1, circuit
`boards 2A and 2B, mounting a drive circuit device 7A or 7B,
`respectively, to drive the source bus lines 6, are connected.
`Moreover, a printed circuit board 8 mounting an input signal
`supply circuit to supply a clock signal, data signal, control
`signal or other signals to the drive circuit devices 7A and 7B
`is connected to the peripheral area of the display panel "I.
`And, the clock signal, data signal, control signal or other
`signals outputted from the printed circuit board 8 are sup-
`plied to the drive circuit device circuit board 2A on the initial
`stage, through an input wiring 9 on the display panel 1, and
`further are supplied to a drive circuit device 7A on the initial
`stage, through wiring of the drive circuit device circuit board
`2A.
`
`[0026] Moreover, the drive circuit device 7A on the initial
`stage supplies the clock signal, data signal and control signal
`to the drive circuit device circuit board 213 on the next stage,
`through a connection wiring 10 on the display panel 1, and
`a drive circuit device 7B on the circuit board 2B receives
`
`the second drive circuit device 7T3
`these signals. And,
`supplies the clock signal, data signal and control signal to
`drive circuit devices on the following stages, though not
`shown in the drawing.
`
`[0027] As described above, the propagation signals, like
`the clock signal, data signal, control signal, or other signals
`outpulted from the printed circuit board 8 of the input signal
`supply circuit are supplied to the plurality ofthe drive circuit
`devices 7A and 7B connected in tandem, through the con-
`nection wiring 10 on the display panel '1.
`[0028] Each of the drive circuit devices 7A and 7B gen-
`erates drive signals for the source bus lines, corresponding
`to the data signal and control signal inputted synchronizing
`with the clock signal. And, in the timing after all the drive
`circuit devices 7A and 7B sequentially input the correspond-
`ing data signal, the drive circuit devices 71\ and ‘TB drive the
`corresponding source bus lines 6 simultaneously. Synchro-
`nizing with this drive, a drive circuit device on the gate side,
`which is not shown in the drawing, drives one of the gate bus
`lines 5, and the voltage applied to the respective source bus
`lines 6 is applied to the pixel electrodes 3 through the 'l'I"'l'
`4.
`
`[0029] FIG. 2 shows an enlarged view of the joint section
`between the drive circuit device circuit board 2 and the
`display panel substrate 1. On the surface of the display panel
`"I, a connection wiring 'l0A is provided, and wirings II on
`the circuit board 2 mounting a drive circuit IC7 and the
`connection wiring 10A are connected at
`the joint section
`shown in the diagonally shaded area. The connection wir-
`ings l0A are formed so that the wiring width becomes wider
`and wider toward the outer side, so that delay of the signal
`transmittal of each wiring can be equal.
`[0030] On the other hand, the plurality of gate bus lines 5
`are sequentially driven by a drive circuit device on the gate
`side, which is not shown in the drawing, synchronizing with
`the timing of a horizontal synchronization signal. The drive
`circuit device on the gate side is also mounted on a circuit
`board same as shown in FIGS. 1 and 2, and the circuit board
`is connected to the peripheral area around the display panel
`1. Moreover, a gate clock signal and control signal that
`should be supplied to the drive circuit device on the gate side
`are propagated and supplied to a plurality of gate side drive
`circuit device circuit boards, through connection wirings
`provided on the display panel 1.
`
`Page 11 of 16
`
`

`
`US 2003/0048249 A1
`
`Mar. 13, 2003
`
`[0031] FIG. 3 shows a configuration of a drive circuit
`device and a display panel in an embodiment of the present
`invention. The configuration shown in FlG.3 can be applied
`to both of a source side drive circu it device and a gate side
`drive circuit device. As described above, to a display panel
`1, like a liquid crystal panel, a drive circuit device circuit
`board 2 mounting a drive circuit device 7 is connected. In
`FIG. 3, the drive circuit device 7 and the circuit board 2
`mounting the same are shown without distinguishing
`between them. And, three drive circuit devices 7A, "H3 and
`7C are connected through the connection wiring 10 on the
`display panel '1.
`[0032]
`In FIG. 3, a clock signal, data signal and control
`signal to be supplied to the individual drive circuit device 7
`are shown all
`together as a propagation signal Sa. This
`propagation signal Sa is a signal that changes during the
`same horizontal synchronization period (or vertical synchro-
`nization period), and is sequentially inputted to a drive
`circuit device TA on an initial stage, a drive circuit device TB
`on a next stage, and a drive circuit device 7C on a third stage.
`Also, a timing signal Sb is supplied to the plurality of the
`drive circuit devices 7 in parallel, and controls the specilied
`operation timing for the plurality of the drive circuit devices
`7. The timing signal Sb controls not only the operation
`timing, but also may control the operation itself. liurther, a
`cascade signal CCD is a signal to control the timing when
`the individual drive circuit devices 7A, 7B and 7C start
`inputting of the propagation signal Sa, and the drive circuit
`device on the front stage supplies the cascade signal CCD to
`the drive circuit device on the rear stage to control the timing
`for the drive circuit device on the rear stage to start inputting.
`
`[0033] The propagation signal Sa is inpntterl by the drive
`circuit device 7/\ on the initial stage, and then, inputted by
`the drive circuit device TB on the next stage, and funher
`inputted by the drive circuit device 7C on the third stage.
`The input start timing of the propagation signal Sa at the
`respective drive circuit devices 7A, 7T3 and 7C is controlled
`by the cascade signal CCD. Therefore,
`the propagation
`signal Sa is not required to be supplied to the drive circuit
`devices 7B and 7C on the following stages, while the drive
`circuit device 7A on the initial stage is inputting the signal
`Sa. Moreover, it is not necessary to supply the propagation
`signal Sa to the drive circuit devices 7C on the third stage
`and the following stages, while the drive circuit device 7|}
`on the second stage is inputting the signal Sa.
`[0034] Accordingly, the individual drive circuit devices
`7A, 7B and 7C have driver circuits 20A, 2013 and 20C to
`input the propagation signal Sa and drive the source bus
`lines or the gate bus lines, and gate circuits 22A, 22B and
`22C to control the propagation of the propagation signal Sa
`to the rear stage. And, the gate circuits begin the propagation
`of the propagation signal 8a to the circuit on the rear stage,
`responding to gate control signals GCON I, 2 and 3. And,
`the gate control signals have almost the same timing as the
`timing of the cascade signals CCD 2, 3 and 4 to be supplied
`to the drive circuit devices on the next stage, respectively, or
`slightly earlier timing than that. Therefore,
`the cascade
`signals CCD 2, 3 and 4 can he used instead of the gate
`control signals GCON 1, 2 and 3.
`In other words,
`the
`propagation start of the gate circuits 22A, 22B and 22C can
`be controlled by the cascade signals CCD 2, 3 and 4.
`
`to the drive circuit device 7A on the
`[0035] Therefore,
`initial stage, a propagation signal Sal
`is supplied and
`
`inputted, however, the propagation of the propagation signal
`Sal to the rear stage is initially stopped by the gate circuit
`22/\. And at the timing when the drive circuit device 7]} on
`the next stage starts inputting of the propagation signal, the
`gate circuit 22A is opened, and a propagation signal Sa2 is
`propagated to the drive circuit device 7B on the next stage.
`A propagation signal Sa3 to the drive circuit device 7(T on
`the third stage is the same as the propagation signal Sa2.
`
`[0036] FIG. 4 shows an operation—timing chart of the
`drive circuit device shown in FIG. 3.
`In FIG. 4,
`the
`propagation signal Sa, the cascade signal CCD, the gate
`control signal G(I()N, and the timing signal Sh are shown.
`The propagation signal Sa is sequentially inputted to the
`plurality of the drive circuit devices 7, during horizontal
`synchronization period (or vertical synchronization period),
`to be used for generating a drive signal. As an example olithe
`propagation signal Sa, FIG. 4 shows that the data signals D0
`through Dn, I)n+'l through D2n, and D2n+1 through D3n are
`individually inputted to the drive circuit devices 7A, 7B and
`7C. The data signal can be a clock signal or a specified
`control signal.
`
`[0037] Apropagation signal Sal outputted from an input
`signal supply circuit, which is not shown in the drawing, is
`fetched into the driver circuit 20A, responding to a first
`cascade signal CCD1 to be supplied to the drive circuit
`device 7A on the initial stage. The propagation signal Sal
`means, as described later, a dot clock signal, data signal and
`its control signal, in the case of the source side drive circuit
`device, or a gate clock signal and its control signal in the
`case of the gate side drive circuit device.
`
`[0038] While the drive circuit device TA on the initial
`stage is inputting this propagation signal Sal, the gate circuit
`22/\ remains in the closed state, so, propagation to the drive
`circuit devices 7B and 7C on the rear stages will not be
`performed. Thereliore,
`the propagation signal Sal which
`sequentially changes will only be propagated up to the drive
`circuit device 7/\ on the initial stage, so, the input signal
`supply circuit 8 will not drive the connection wiring 10 to
`the drive circuit devices on the rear st ages.
`
`[0039] Next, when the input of the propagation signal Sal
`by the drive circuit device "IA on the initial stage finishes, the
`supply of propagation signal Sa2 to the drive circuit device
`713 on the next stage starts. That is to say, the gate circuit
`22/\ opens, responding to the gate control signal GCONI
`generated by the driver circuit 20A on the initial stage, and
`the propagation of the propagation signal Sa2 to the next
`stage starts. liurther, responding to the cascade signal CCD2
`generated by the driver circuit 20A on the initial stage, a
`driver Circuit 2013 in the drive circuit device 7B on the next
`
`stage starts inputting of the propagation signal Sa2. There-
`fore, the gate control signal GCUNI controls the start—up of
`the propagation of the propagation signal 3a to the rear
`stage, and the cascade signal CCD] controls the start-up of
`the input of the propagation signal by the drive circuit device
`on the rear stage. Therefore, the gate control signal GCONI
`has almost the same timing
`the timing of the cascade
`signal CCD], so, the gate control signal can be replaced with
`the cascade signal.
`
`In FIG. 4, a timing signal Sb occurs once during
`[0040]
`the horizontal synchronization period (or vertical synchro-
`nization period), and controls the predetermined operation
`timing of the driver circuit.
`
`Page 12 of 16
`
`

`
`US 2003/0048249 A1
`
`Mar. 13, 2003
`
`[0041] FIG. 5 shows a configuration of a source side drive
`circuit device. Further, FIG. 6 shows a configuration of a
`data register in the source side drive circuit device. And,
`FIG. 7 shows an operation-timing chart of the source side
`drive circuit device.
`
`I11 FIG. 5, a drive circuit device circuit board 2A
`[0042]
`and a drive circuit device 7Aon the initial stage, and a drive
`circuit device circuit board 2B and a drive circuit device 7B
`on the next stage are shown. Like FIG. 3, the drive circuit
`device and its mounting circuit board are shown without
`distingushing between them. And, these drive circuit board
`circuit boards 2A and 2B are connected to a liquid crystal
`display panel 1.
`
`In the case of the source side drive circuit device,
`[0043]
`as a propagation signal Sa that changes during a horizontal
`synchronization period, and to he inputted sequentially by
`individual drive circuit devices, there are a clock signal
`ICLK, display data signals RD, GD, RD, and their invert
`control signal DINV. Also, as a signal St) to he inputted
`simultaneously to all drive circuit devices, there are a latch
`pulse LP,
`a phase control signal PC‘
`to control a drive
`polarity, and a standard voltage VR. And, to the source side
`drive circuit device, a cascade signal CCD to control the
`input start of a data signal is inputted.
`
`[0044] The drive circuit device 7A on the initial stage has
`a shift register 30A, which starts inputting ofa clock ICLKI
`responding to a cascade signal CCD1, and shifts output
`signals S30 synchroniiting with the clock l(‘l_K'l; a data
`register 32A, which inputs and holds display data signals
`RD, GD, BD and a data invert control signal DINV, respond-
`ing to the output signal 830 of the shift register 30A; and a
`latch circuit 34A, which responding to a latch pulse LP,
`latches the data signals that are inverted or are not inverted
`from the display data signals RD, (ii) and BI) inputted and
`held by the data register 32A, corresponding to the data
`invert control signal DINV.
`
`[0045] Moreover, a drive control circuit device 7A has a
`level shift circuit 36/\, that reverses the phases of the data
`signal latched by the latch circuit 34A for even numbered
`source bus lines and odd numbered source bus lines, corre-
`sponding to the phase control signal PC, and a DEA converter
`and output circuit 38A, that converts digital outputs of the
`level shift circuit 36A into analog outputs, and outputs the
`analog drive signals to the source bus lines SB.
`
`[0046] Also, the drive control circuit device TA has a first
`gate circuit G1 to propagate the clock. signal ICLK1, that is
`the propagation signal Sal, to the following stage, and a
`second gate circuit G2 to propagate the display data RD,
`GD, Bl), and the data invert signal IJINV to the following
`stage. A gate control signal GCONI to control
`the gate
`circuits is generated by a gate control circuit 40A. The gate
`control circuit 40A inputs and shifts the clock ICIK1,
`responding to the cascade signal CCDI, and generates the
`gate control signal GCONI,
`in the timing when a drive
`circuit device on the next stage starts inputting the propa-
`gation signal Sa2. The lirst and the second gate circuits G1
`and (32 open, responding to the gate control signal (iC()N1,
`and start propagating of the propagation signal Sa2 and the
`clock ICLK2 to the drive circuit device on the next stage.
`
`register 32B, a latch circuit 3413, a level circuit 363, a DEA
`converterfoutput circuit 38B, a gate control circuit 40l'i, and
`further a lirst and a second gate circuits (31 and (32. And, the
`drive circuit device 7A on the initial stage and the drive
`circuit device 7]} on the next stage are connected through
`connection wirings 10 on a display panel 1.
`
`[0048] As shown in FIG. 6, the data register 32 has first
`flip—flops 42 to sequentially latch display data signals RD,
`GD and BD, synchronizing with shift outputs S30 to be
`sequentially outputted from the shift register 30, synchro-
`nizing with the clock ICLK, second flip—flops 44 to sequen-
`tially latch a data invert control signal [)IN\*', and EUR. gates
`46 to output an XOR (an exclusive OR) of the data invert
`control signal and the display data. Each of the display data
`signals RD, GD and BD is a digital signal of 8 bits;
`therefore, the first flip-flops 42 latch digital signals of 24
`bits. Also, the data invert control signal DINV is a control
`signal of "I bit to be supplied, corresponding to the 24 hits
`display data signals.
`
`[0049] With the display data signals RD, GD and RD
`being digtal signals of 24 bits, 24 signal lines must be driven
`to II, I. levels, synchronizing with the clock I(f[.K. So,
`information on whether the supplied display data signals
`RD, GD and BD of 24 bits should be inverted or not,
`comparing the display data signal of the previous pixel and
`the display data signal of the next pixel, will be generated as
`the data invert control signal DINV. By the utilization of the
`data invert control signal DINV, the number of bits of the
`display data signals which change from H level to I. level,
`or front L level to H level can be reduced to less than a half
`of 24 bits.
`
`[0050] For instance, in case of displaying data in white for
`the previous pixel, corresponding to the highest tone level,
`the display data signal of 24 bits is all II level, and if the
`pixel next to that is for display in black, corresponding to the
`lowest tone level, the display data signal of 24 hits is all I.
`level. Consequently, the display data signals of 24 bits must
`change from the II level to the I. level simultaneously.
`'l'herefore, by driving only the data invert control signal
`DINV to the II level to show inversion of display data
`signals, leaving all the display data signal on II level without
`changing, the power to drive the display data signal lines can
`be suppressed.
`
`the latched display data
`[0051] By the EOR gate 46,
`signals are inverted by the data invert control signal DINV
`of H level that indicates invert, and the latched display data
`signals are not inverted by the data invert control signal
`|)[NV of I. level that indicates non-invert.
`
`[0052] Then, the following shows description of operation
`of the source side drive circuit device, with reference to the
`opcration—titning chart shown in FIG. 7. The drive circuit
`device 7A on the initial stage inputs the clock ICI.Kl,
`responding to the cascade signal CCD1, and the shift register
`30A sequent