~GEOTEXT
`.JJJ Translations
`
`translations@geotext .com
`www.geotext.com
`
`STATE OF NEW YORK
`
`COONTY OF NEW YORK
`
`ss
`
`CERTiFICATION
`
`This is to certify thatlhe attached translation is, to the best afmy knowledge and belief, a true
`
`and accurate translation from Japanese into English of the attached Unexamined Patent
`
`App lication No. H08-30S322.
`
`Mirna Turina, Project Manager
`Geotext Translations, Inc.
`
`Sworn to and subscribed be ore me
`
`-/').
`thiS~~ ~ 20
`
`lYNDA GREEN
`NOTARY PUBliC-STATE OF NEW YO
`NO.01GR620540
`RI(
`J
`QUo/lfied In Ne
`My Commission E W York County
`xplres May J I, 20 J 1
`
`NelN York
`t: +1.212.631.7432
`
`London
`t : +44.20 .7553.4100
`
`Washington, D .C
`t: + 1 .202 .828 .1 267
`
`Paris
`t: +33.142.68.51.47
`
`Chicago
`\ : +1.312 .2 42 .3756
`
`Stockholm
`t: +46.8.463 .11.8 7
`
`SHARP EXHIBIT 1002
`San Francisco
`Houston
`t: +1 .713 .353.3909
`t: +1 .415.576.9500
`
`Fran kfurt
`Hong Kong
`t: +49.69.7593.8434
`t: +852.2159.9143
`Page 1 of 40
`
`

`

`(19)
`
`JAPANESE PATENT OFFICE (JP)
`Unexamined Patent Gazette (A)
`(12)
`Unexam ined Patent Application (Kokai) No . H08-305322
`(11)
`(43)
`Disclosure Date: November 22, J 996
`
`(51)
`
`Int. C1.6:
`
`Classification
`Symbols
`
`Internal Office
`Registration
`Nos.:
`
`FI
`
`Tech.
`D isplay
`Location
`
`G09G 3/36
`G02F 1/133 50S
`550
`H04N 5/66 102
`
`G09G 3/3 6
`G02F 11133 50S
`550
`H04N 5/66 102B
`Request for Examination: Not requested
`
`Number of Claims: 6
`OL (Total of 19 pages)
`
`(21) Application No.:
`(22) FiHng Date:
`
`Patent App. No. H07· 112129
`May 10, 1995
`
`(71) Applicant:
`
`Osaka C ity, Osaka
`(72) [nventor:
`
`Osaka C ity, Osaka
`(72) foveo lar:
`
`Osaka C ity, Osaka
`(72) In ventor:
`
`000005049
`Sharp Corp.
`22-22 Nagaike-cho, Abeno-ku,
`
`Osamu Sasaki
`Sharp Corp.
`22-22 Nagaike-cbo, Abeno-ku,
`
`Yutaka Yoneda
`Sharp Corp.
`22-22 Nagaikc-cho, Abeno-ku,
`
`Manabu Matsuura
`Sharp Corp.
`22-22 Nagaike-cho, Abeno-ku,
`
`[Title of the Invention] Disp lay
`
`(54)
`Device
`[Abst"ct]
`(57)
`[Constitution] After the same data signals
`from a data signal line 12 are supplied to
`three data sibrnal lines 16 to 18 via buffer
`ci rcuits 13 to 15, they are supplied to
`sampling switches 19 to 23 of a sampl ing
`ho ld circuit 11. The data signals sampled by
`the sampling hold circuit 11 are supplied to
`source bus lines 5 ....
`[Effect] Because it is possible to correctly
`sample data signals wilh little corruption or
`no ise, high-resolution display w ith limited
`decrease in the horizontal resolution and
`decrease in the display quality becomes
`possible.
`
`Osaka C ity, Osaka
`(74 ) Agent:
`
`Kenzo I-lara, Patent Attorney
`
`2
`
`\
`
`sp
`
`10
`I
`
`5
`
`Page 2 of 40
`
`

`

`[Claims]
`[Claim I] A display device provided with a plurality of
`data signal lines by which data signals are respectively
`supplied,
`a plurality of sampling circuits by which the data
`signals supplied from the plurality of data signal lines are
`respectively sampled,
`respectively
`lines
`a plurality of data bus
`connected to the plurality of sampling circuits,
`·a plurality of pixel units that are both connected
`to the plurality of data bus lines and arranged in matrix
`fonn, and
`a drive circuit induding the sampling circuits and
`that drives the data bus lines, wherein
`at least two of the plurality of data signal lines
`have the same data signals supplied and are connected to
`different sampling circuits via respectively different buffer
`circuits.
`[Claim 2J The display device according to claim 1,
`wherein Gf the plurality of sampling circuits, the sampling
`circuits
`for which
`the
`timing of the sampling
`is
`synchronized are both connected to respectively different
`data signal lines and have no time overlap of the ON time
`of the respective sampling circuits.
`[Claim 3] The display device according to claim I or 2,
`wherein the buffer circuits are formed on the same
`substrate as the sampling circuits.
`[Claim 4] A display device provided with a plurality of
`data signal lines by which data signals are respectively
`supplied,
`a plurality of sampling circuits by which the data
`signals supplied from the plurality of data signal lines are
`respectively sampled,
`respectively
`lines
`a plurality of data bus
`connected to the plurality of sampling circu its,
`a plurality of pixel units that are both connected
`to tile plurality of data bus lines and arranged in matrix
`fonn, and
`a drive circuit that includes the sampling circuits
`and that drives the data bus lines, wherein
`the data signal line is divided into a plurality in
`the horizontal direction of the display, and each divided
`signal
`line
`is connected
`to sampling circuits via
`respectively different buffer circuits.
`[Claim 5] A display device provided with a plurality of
`data signal lines by which data signals are respectively
`supplicd,
`a plurality of sampling circuits by which the data
`signals supplied from the plurality of data signal lines are
`respectively sampled,
`lines
`a plurality of data bus
`connected to the plurality of sampling circuits,
`a plurality of pixel units that are both connected
`to the plurality of data bus lines and arranged in matrix
`form, and
`
`respectively
`
`(2)
`
`Unexamined Patent Publication H08-305322
`
`a drive circuit that includes the sampling circuits
`and that drives the data bus lines, wherein
`of the plurality of pixel units, respectively
`different data bus lines are connected to the plurality of
`pixel units adjacent in the column direction, and the same
`sampling circuits are connected via the buffer circuits to
`these data bus lines.
`[Claim 6] The display device according to claim 1,2,3,4
`or 5, wherein the drive circuit and the image display unit
`comprising the plurality of pixel units are
`fotTI1ed
`monolithically on the same substrate.
`[Detailed Description of the Invention]
`L0001] [Field of Industrial Use] The present invention
`relates to a display device such as a liquid crystal display
`device or the like.
`L0002] [Prior Art] Conventionally, display devices, for
`example, as shown in FIG. 12, liquid crystal display
`devices (hereafter callcd LCD) havc bccn constituted by a
`display unit 101 having a plurality of pixel units 104 ... ,
`and a source driver 102 and a gate driver 103 as a drive
`circuit for driving each pixel unit 104.
`is respectively
`L0003] Each of the pixel units 104..
`arranged at a place at which a plurality of source bus lines
`105 ... connected to the source driver 102 and a plurality
`of gate bus lines 106. connected to the gate driver J03
`intersect orthogonally. Thus, the arrangement of the pixel
`units 104 ... is in a matrix form in the display unit 101.
`[0004J Also, a pixel unit 104 is constituted by a pixel
`transistor 107 fonned from TfT (thin film transistors),
`pixel capacity 108 and additional capacity 109; the gate
`tenninals ofpixc1 transistor 107 are connected to gate bus
`line 106, source tenrunals are connected to source bus line
`105, and drain tenninals arc connected to pixel capacity
`108 and additional capacity 109.
`[0005] Source driver 102 is constituted by shift register
`110, and sampling switches 111 formed from transistors,
`sampling capacitors. 112, data signal lines 113 and the
`like; sampling hold circuit 114 is fonned from the above
`sampling switches Ill, sampling capacitors 112, data
`signal lines 113, and source bus lines lOS.
`[0006] Start pulses (SP) and drive clocks (CK, ICK) input
`to the shift register 110, and the input SP are sequentially
`shifted according to the CK and ICK and output to
`sampling hold circuit 114.
`[0007] Gate driver 103 has a shift register JJ5 and
`sequentially outputs scan signals to each gate bus lines
`106 ....
`[0008] Funhermore, when the above display unit 101,
`source driver 102, and gate driver 103 are formed
`monolithically on the same substrate, there are cases when
`only display unit 101 is fonned on the insulated substrate.
`[0009J Hcre we will describe the operation of the disp lace
`device with the constitution noted above. First, the SP
`input to the shift register 110 of the source driver 102
`
`Page 3 of 40
`
`

`

`is sequentially shifted by CK i1nd IC K and output to
`sampling hold circuit J 14, and become the sampling
`pulses for sampling hold circuit 114. Then, sampling
`switc11 II I goes to an ON state by means of the input
`sampling pulse, and the data signal of data s ignal line 113
`at the point in time that this sampling pulse is input is
`sampled.
`[0010] Then, the data signal sampled by the sampling
`pulse is held in sampling capacitor 112 and output to
`source bus line 105 as a source bus line signaL
`[0011] Meanwhile, the output of each digit of shift
`register 115 of gate driver 103 is output as scan signals
`(gate bus line signals) sequentially to gate bus lines
`106 ... ; pixel transistors 107 connected to selected gate
`bus lines 106 tum ON, and the source bus line signals at
`that point in time are sequentially written as image data to
`pixel capacity 108 and additional capacity 109.
`[0012] Then, by driving tbe liquid crystal corresponding
`to each pixel unit 104, the desired display is achieved.
`[0013] Therefore, with the LCD of the constitution noted
`above, as described above, source driver 102 uses the
`panel sample hold method by which image data is held on
`the display unit 101 side. With an LCD having this kind
`of source drivcr 102, when tbe number of pixel units 104
`in the horizontal scan direction becomes high, the image
`data write time is different for pixel unit 104 connected to
`the least significant digit of the shift register 110 and the
`pixel wut 104 cOllllected to the most significant digit.
`Because of this, it is possible to make the image data
`write time longer with !.he pixel units 104 connected to
`the upper digits of the shift register I 10, but there is the
`problem that it is not possible to have sufficient image
`data write time with the pixel units 104 connected to the
`lower digits.
`[0014 J [n light of that, to solve the problems noted above,
`we propose an LCD that uses a driver sample hold
`method source driver by which image data is held on the
`source driver side.
`[0015] In the following, we will describe an LCD that
`uses the source driver of the driver sample hold method
`noted above. Furthennore, this LCD, with the exception
`of the source driver, has the same display unit 101 and
`gate driver 103 as that of the LCD shown in FIG. 12;
`therefore, in this description, we will describe only Ihe
`source driver of the driver sample hold method.
`[0016] The source driver of the driver sample hold
`method noted above has a constitution in which the
`output side of sampling hold circuit 114 of source driver
`102 shown in FIG. 12 is connected to a transfer circuit
`120 fomled from transfer switch 116, hold capacitor 117,
`butTer circuit 118, and transfer signal line 119.
`
`(3)
`
`Unexamined Patent Publication H08-305322
`
`[0017] In other words, at the time point that data of one
`scan lrne has been sampled by sampling hold circuit t 14,
`a transfer signal is output from transfer signal Ime 119 by
`transfer circuit 120, transfer switch 116 goes to an ON
`state, and after the data held in sampling capacitor 112 of
`sampling hold circuit 114 has been simultaneously
`transferred to hold capacitor 117, sampling of the next
`scan period is performed.
`[00181 In other words, during the period that data of the
`next one scan line is being sampled, the sampling data of
`the previous scan line held in hold capacitor 117 is
`continuously applied as source bus line signals to source
`bus lines 105 (FIG. 12) via the butTer circuit 118.
`[00 19] In this way, by using the source driver of the
`driver sample hold method, even when there is a large
`number of pixel units 104 in the horizontal scan direction,
`it is possible to obtain sufficient write time for the image
`data to the respective pixel units 104 .. .. By doing this, it
`is possible to make the image data write time almost the
`same for the pixel unit 104 connected to the least
`sib'1lificant digit of the shift register 110 and the pixel unit
`104 connected to the most sign ificant digit.
`formed
`is
`[0020] Furthermore, when
`Ihe LCD
`tn()nolith ieally by a driver on the insulated substrate, the
`speed at which the shift register fonned using p-SiTFT
`operates stably is about several MHz, and with the shift
`register inside the source driver of dle LCD with a large
`in
`the horizontal direction which
`nwnber of pixels
`requires high speed operation, a problem occurs of
`having the shift register operating speed be insufficient.
`[0021] In light of that, to reduce the operating speed of
`the shift register, for example, as shown in FIG . 14, we
`propose a source driver for whjch a plurality of systems,
`in this case four systems of shift registers 131 to 134, are
`provided, and by having the respective shift registers 131
`to 134 operate at CK I to CK4, ICK I to /CK4 of ditTerent
`phases, each level6fshift register 13110 134 is operated
`at low speed with the overall shift speed remaining as is.
`[0022J With the source driver having the four systems of
`shift registers 131 to 134 noted above, as sllOwn in FIG.
`15, Ihe start pulses SP are sequentially shifted by CK I .to
`CK4 and ICKI to ICK4 and sampling pulses SM PI to
`SMP8 are output. F urthennore, the width of SMP I to
`SMP8, which are the output of the four systems of shift
`registers 131 to 134, is four times thi1t of when the shift
`register has one system, but the phase skew of SMP 1 to
`SMP8 is the same as when the shift register has one
`system.
`[0023]
`[Problems the lnvention Attempts to Solve] However,
`with the source driver having the four systems of shift
`registers 131 to 134 noted above, as shown in FIG. 15,
`each sampling pulse
`
`Page 4 of 40
`
`

`

`SMPI to SMPS is in a mutually overlapping form. Because
`of this, when seen at a given moment, there are alw!lys eight
`11 I... ON.
`In other words,
`sampling
`transistors
`the
`capacitance of eight sampling capacitors 112 ... has become
`the load via sampling transistors III for data signal line 113
`or for the data ~ignal output circuit. Furthennore, there is
`wiring resistance on data signal lines 113 and ON resistance
`on sampling transistors II I, and therefore the response of
`the data signals with each sampling capacitor 112
`deteriorates with operation of a time constant of the RC
`integrating circuit, and the wavefonn becomes corrupted
`compared with the original data signal.
`[0024] With sampling of data signals done based on this
`kind of corrupted wavefonn, the band infonnation that the
`data signal originally had is lost, so the display has low
`horizontal resolution. Furthennore, for the scan sib,'TJals as
`well (not illustrated), depending on the constitution, two
`adjacent outputs of the gate shift register are overlapping,
`and for the pixel part as well, the same kind of problem
`occurs as with the sampling unit of the source driver noted
`above.
`[0025] To prevent this kind of problem, we propose a
`display device for which a video signal line is arranged for
`each shift register 131 to 134. In this case, for example, the
`Nth (SMP I) fall of the sampling pulse shown in FIG. 15 and
`the N +8th (SMP9) rise have the same timing, but in
`actuality, due to signal wavefonn corruption or delay, a
`phenomenon occurs of the N +Sth sampling transistor
`the Nth sampling
`turning ON before
`simultaneously
`transistor III goes completely OFF.
`[0026J When this kind of phenomenon occurs, as described
`above, even if the video signal line is divided into a plurality
`of palts, the sampling data of the Nth sampling hold circuit
`114 of the source driver is affected not only by Ihe N +4
`sampling signal, but also by the N +8!h sampling data, and an
`adverse effect is given to the display as a ghost phenomenon
`or noise.
`[0027] Furthennore, the phenomenon described above can
`also occur in the same manner with the display unit. Because
`of this, for example, the present applicant,
`in Patent
`Application No. H05·300537. proposed a display device for
`which the same video signal line is branched into a plurality
`of parts external to
`the drive circuit. In
`this way, by
`branching thc same video sjgnalline into a plurality of parts
`external to the drive circuit, having a plurality of sampling
`circuits connected to one video signal
`linc tuming on
`simultaneously is eliminated, and as a result, corruption of
`the signal in each video signal line is reduced, and the
`resolution of the display device is improved.
`[0028] However, even when the same video signal line is
`simply divided into a plurality of parts, when divided into a
`plurality of parts on the same substrate as the panel, by
`means of contact resistance with a flexible substrate or the
`like, wiring resistance, and also output impedance of the
`
`(4)
`
`Unexamined Patent Publication HOS·305322
`
`video signal supply source, it is possible to increase the time
`it is not possible
`to
`totally
`inhibit
`the
`constant, but
`occurrence of ghosts. Also, even when the same video signal
`line is simply divided into a plurality outside the panel. by
`means of the aforementioned contact resistance with a
`flexihle substrate or the like, wiring re~istance , and also
`output impedance of the video signal supply source, it is
`possible to increase the time constant, but it is not possible
`to totally inhibit the occurrence of ghosts.
`[0029) Also, when we look at sampling circuits connecterl to
`the same data signal lines constituting the source driver,
`there is OFF resistance in the sampling transistor; however,
`when it is not possible to make the OFF resistance of the
`sampling transistor sufficiently large, the problem occurs of
`the sampling data written to thc sampling capacitor going
`through the OFF resistance of the transistors and the data
`signal lines and having crosstalk with each other.
`[0030] The present invention was created in light of the
`problem points notcd above, and its objective is to provide a
`display device that reduces data signal corruption or data
`signal noise due
`to adjacent
`transistors being ON
`simultaneously and that reduces crosstalk due to insufficient
`or decreased transistor OFF characteristics, thus preventing a
`ghost phenomenon and also being able to realize high
`resolution display for which a decrease
`in horizontal
`resolution and a decrease in display quality due to crosstalk
`are inhibited.
`[0031]
`LMeans for Solving the Problems] The display device of
`claim I is equipped with a plurality of data signal lines by
`which data signals aTe respectively supplied, a plurality of
`sampling circuits by which the data signals supplied from the
`plural.ity of data signal lines are · respectively sampled, a
`plurality of data bus lines respectively connected to the
`plurality of sampling circuits, a plurality of pixel units
`connected to the plurality of data bus lines and arranged in
`matrix form, and a drive circuit including the sampling
`circuits for driving the data bus lines, wherein at least two of
`the plurality of data signal lines have the same data signals
`suppli ed, and are connected to different sampling circuits via
`respectively different buffer circuits.
`[0032] The display device of claim 2 is the display device
`according to claim I, wherein of the plurality of sampling
`circuits, thc sampling circuits for which the timing of the
`sampling is synchronized are connected to respectively
`different data signal lines, and there is no time overlap of the
`ON time of the re:;pective sampling circuits.
`[0033] The display device of claim 3 is the display device
`according to claim I or 2, wherein the buffer circuits are
`fonned on the same substrate as the sampling circuits.
`[0034J The display device of claim 4 is equipped· with a
`plurality of data signal lines by which data signals are
`respectively supplied, a plurality of sampling circuits by
`which the data signals supplied from the plurality of data
`
`Page 5 of 40
`
`

`

`signal lines are respectively sampled, a plurality of data bus
`lines respectively connected to the plurality of sampling
`circuits, a plurality of pixel units connected to the plurality of
`data bus lines and arranged in matrix fonn, and a drive circuit
`including the sampling circuits for driving the data bus lines,
`wherein the data signal line is divided into a plurality in the
`horizontal direction of the display, and each divided signal
`line
`is connected to sampling circuits via respectively
`different buffer circuits.
`[0035] The display device of claim 5 is equipped with a
`plurality of data signal lines by which data signals are
`respectively supplied, a plurality of sampling circuits by
`which the data signals supplied from the plurality of data
`signal lines are respectively sampled, a plurality of data bus
`lines respectively connected to the plurality of sampling
`circuits, a plurality of pixel units connected to the plurality of
`data bus lines and arranged in matrix form, and a drive circuit
`including the sampling circuits for driving the data bus lines,
`wherein of the plurality of pixel units, respectively different
`data bus lines arc connected to the plurality of pixel units
`adjacent in the column direction, and the same sampling
`circuits are connected via the buffer circuits to these data bus
`lines.
`[00361 The display device of claim 6 is the display device
`according to claim 1,2, 3,4 or 5, wherein the drive circuit
`and the image display unit consisting of a plurality of pixel
`units are fonned monolithically on the same substrate.
`[0037]
`[Operation] With the constitution of claim 1, by means of at
`least two of the plurality of data signal lines having the same
`data signals supplied, and being connected to different
`sampling circuits via respectively different buffer circuits, it
`is possible to have sparse electrical connections of adjacent
`sampling circuits by which the same data signals are
`supplied.
`[0038] By doing this, cven whcn adjacent sampling circuiL~
`for which the same data signals are supplied are in an ON
`state simultaneously, the other adjacent sampling circuits to
`which the same data signals are supplied arc not affectcd by
`noise that occurs at this time. In other words, incorrect data
`signals due to the noise noted above are not sampled.
`[0039] Also, since adjacent sampl ing circuits arc not
`connected to the same data signal line, it is possible to reduce
`the load of one data signal line, so it is possible to reduce
`data signal corruption.
`[0040] Therefore, with adjacent sampling circuits, there is no
`erroneous sampling due to data signal corruption, and there is
`no effect when mutually turning ON and OFF, so correct data
`signals are always sampled. Because it is possible to supply
`the sampled data signals to the data bus line, it is possible to
`reduce thc crosstalk due to ON and OFF characteristic
`defects of sampling signals with the pixel units. Thus, it is
`possible to have a high-resolution display in which a decrease
`in display quality due 10 crosstalk is inhibited.
`
`(5)
`
`Unexamined Patent Publication H08-305322
`
`[0041] With the constitution of claim 2, sampling circuits for
`which the sampling timing is synchronized are connected to
`respectively different data signal lines, and by means of the
`ON period of the
`respective
`sampling circuits not
`overlapping, it is possible to reduce the noise due to other
`adjacent sampling circuits going to an ON state at the
`moment that another single sampling circuit goes to an OFF
`state.
`[0042] With the constitution of claim 3, by means of the
`buffer circuits connected to the sampling circuits being
`fonned on the same substrate as the sampling circuits, it is
`possible to suppress degradation of data signals caused by
`such things as wiring resistance and contact resistance of the
`flexible substrate or the like that connects the buffer circuits
`and the sampling circuits. It is also possible to suppress an
`increase in connection tenninals for connecting the buffer
`circuits and the sampling circuits and possible to improve
`reliability with mounting.
`[0043] With the constitution of claim 4, the data signal lines
`are divided into a plurality in the display horizontal direction
`and each divided signal line is connected to sampling circuits
`via respectively different buffering circuits, so it is possible
`to reduce the load on the data signal line. By doing this, it is
`possible to reduce the resistance and capacitance of the data
`signal lines, so degradation of the data signals on the data
`signal line is further reduced, and it is possible to reduce
`noise during sampling.
`l0044] With the constitution of claim 5, of the plurality of
`pixel units, respectively different data bus lines are connected
`to the plurality of pixel units adjacent
`in
`the column
`direction, and· by the same sampling circuits being connectcd
`via the buffer circuits to these data bus lines, it is possible to
`inhibit intcrference of ·pixel units adjacent in the column
`direction. By doing this, it is possible to reduce crosstalk
`betw·een pixel units with each other, and possible to improve
`display quality.
`L0045] With the constitution of claim 6, by means of an
`image display unit constituted from a plurality of pixel units
`being formed monol ithically on the same substrate as the
`image display unit, it is possible to increase the pixel
`transistor drive force accompanying an increase in screen
`size, to reduce mounting costs of the drive Ie, and the like.
`[0046]
`[Embodiments]
`[Embodiment 1] Following is a description of an embodiment
`of the present invention based on FIG. I through FIG. 3. in
`this embodiment, we will describe a liquid crystal d.isplay
`device (hereafter called LCD) as the display device, and the
`same is also true for the other embodiments described later.
`[0047] As shown in FIG. 2, the LCD of this embodiment is
`constituted from a display unit I having a plurality of pixel
`units 4 arranged in a matrix fonn, and a source driver 2 and a
`gate driver 3 as the drive circuit for driving each pixel unit 4.
`[0048] On display unit 1, the following are arranged: a
`
`Page 6 of 40
`
`

`

`plurality of source lines 5 ... connected to the source driver
`2, and a plurality of gate bus lines 6 ... connected to the gate
`driver 3, arranged so as to intersect orthogonally, and pixel
`units 4 arranged at the intersecting parts of the source bus
`lines 5 and the gate bus lines 6. In other words, display unit
`I drives pixel units 4 by data signals such as video signals or
`the like from source driver 2 and scan signals from gate
`driver 3, and the desired image is displayed by changing the
`liquid crystal orientation state of a liquid crystal layer (not
`illustrated).
`[0049] The aforementioned pixel units 4 are constituted by a
`pixel transistor 7 consisting of a TFT (Th in film transistor),
`a pixel capacity 8, and an additional capacity 9; the gate
`terminals of the pixel transistors 7 are connected to gate bus
`lines 6, the source terminals to source bus lines 5, and the
`drain terminals to pixel capacity 8 and additional capacity 9.
`In other words, when pixel transistors 7 are turned ON by
`the scan signal, the source bus line signals (video signals)
`from source bus line 5 are written to pixel capacity 8 and
`additional capacity 9.
`l0050] The following are provided on source driver 2: a
`source shift register 10, and a sampling hold circuit II for
`sampling data signals from a data signal line 12 by sampling
`pulses from source shift. register 10. The aforementioned
`data signal line 12 is branched into three within source
`driver 2 and connects to three data signal lines 16 to 18 via
`buffer circuits 13 to 15. Furthennore, in this embodiment,
`the aforementioned buffer circuits 13 to 15 are provided
`inside source driver 2, but the invention is not limited to this,
`and these can also be provided extemal1y. In other words,
`instead of bcing branched on the inside of source driver 2,
`data signal line 12 can also be branched outside source
`driver 2.
`[0051] Start pulses (SP) and drive clocks (CK, /CK) are
`input to the aforementioned source shift register 10, and the
`input SP are sequentially shifted according to the CK and
`/CK and output as sampling pulses to sampling hold circuit
`11.
`[0052] As shown in FlO. I, data signals from data signal line
`12 are supplied to sampling hold circuit II from three data
`signa! lines 16 to 18 connected via buffer circuits 13 to IS,
`and the aforementioned data signals are sampled according
`to sampling pulses from the aforementioned source shift
`register 10. In other words, the same data sjgnal is branched
`into
`three, and
`the
`respective
`signals are sampled
`individually.
`[0053] The aforementioned sampling hold circuit 11 has
`sampling switches 19
`to 23
`formed
`from TFT
`for
`sequentially sampl ing data signals according to sampling
`pulses of source shift register 10, and hold capacitors 24 to
`28 for holding the sampled data. One sampling circuit is
`constituted from one sampling switch and onc sampling
`capacitor connected to that.
`
`(6)
`
`Unexamined Patent Publication H08-305322
`
`from the aforementioned source
`[00541 Output lines lOa ..
`shift register 10 are respectively connected to the gate
`terminals of the aforementioned sampling switches 19 to 23,
`and data signal lines 16 to 18 branched from one data signal
`line 12 are respectively connected to the source terminal. In
`other words, data signal line 16 is connected to the source
`terminal of sampling switch 19, data signal line 17 is
`connected to the source terminal of sampling switch 20, data
`signal
`line 18
`is connected to the source terminal of
`sampling switch 21 , and data signal line 16
`is again
`connected to the source terminal of sampling switch 19, and
`fo llowing, data signal
`lines 16
`to 18 are repeatedly
`connected in sequence.
`[0055 ] As described above, sampling switches 19 to 23 are
`connected so that sampling switches connected to the same
`data signal line, for example the sampling switch 19 and the
`sampling switch 22 connected to the data signal line 16, do
`not go to an ON state simultaneously. In other words, there
`are sparse mutual electrical connections of sampling
`switches 19t023 .
`10056] Here, we will explain the operation of the LCD of the
`constitution noted above while referring to the operation
`timing chart of FIG. 3.
`100571 First, for one scan period, the SP input to source
`shift register 10 of source driver 2 are sequentially shifted by
`CK, /CK and output to sampling hold circuit II, and these
`become the sampling pulses of sampling hold circuit II.
`Then, each sampling switch 19 to 23 is set to an ON state by
`the input sampling pulses, and the data signals of data signal
`lines 16 to 18 are sampled at the point in time that these
`sampling pulses are input.
`[0058] Then, each data signal sampled by the sampling
`pulses is output to the source bus lines 5 as the source bus
`line signals held by the hold capacitors 24 to 28.
`rOO 59] Meanwhile, the output of each row in gate driver 3
`is output sequentially to gate bus lines 6 as scan signals (gate
`bus line signals), pixel .transistor 7 connected to selected gate
`bus lines 6..
`is turned on, and at that point in time, the
`source bus line signals from the aforementioned source bus
`line 5 of one scan period are sequentially written as image
`data to pixel capacity 8 and additional capacity 9.
`[0060] Then, (he desired display is created by driving
`liqu id crystal corresponding to each pixel unit 4.
`r006 J] In the next scan period, source bus line signals for
`which the vo ltage polarity is inverted are written as image
`data to pixel capacity 8 and additional capacity 9. In this
`way, each timc the scan period switches, the voltage polarity
`of the source bus line signal is reversed and this is written as
`image data to pixel capacity 8 and additional capacity 9,
`and each time, the desired display is created by driving the
`liquid crystal corresponding to each pixel unit 4.
`
`Page 7 of 40
`
`

`

`the
`in FIG. J, with
`[0062] Therefore, as shown
`aforementioned source driver 2, when the SP are input, the
`phase is skewed by ~ only by the input timing of CK and
`ICK, and sampling pulses SMP I to SMP5 are output. By
`doing this, each sampling pulse SMPI to SMP5 has a time
`overlap, so !WO adjacent sampling switches are always in
`an ON state.
`[0063] However, in this embodiment, the aforementioned
`sampling switches 19 to 23 have sparse mutual electric
`In other words,
`connections.
`two adjacent sampling
`switches are not connect