4») IEEE JOURNAL OF
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`o
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`.OLIDSTATE
`IRCUITS
`3" CEMBER 1992
`VOLUME 27
`
`NUMBER 12
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`{T1131727.:}
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`5.1.1. {-1
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`leMRlFSUSSNailm-41200)
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`puoucmou OF 11115113155 sow-STATE crucurrs COUNCIL
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`1 l
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`SPECIAL ISSUE 0N ANALOG AND SIGNAL PROCESSING CIRCUITS
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`............................... ......n. P. Colbeckandk. R. Spencer
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`I659
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`1.1110110 ......................................
`1
`l \L PAPERS
`I662
`11 11 650MHz Folding ADC ................................... . .............1.11m Wilma and R. J. 111111 1!: Planck:
`l661
`l: h 5Memphis Two-Step CMOS AID Converter.................
`B Ramvlandfl. A. Wooley
`l679
`'1 1 ilulDomain Calibration of Multlntep Analog-tonigital Cont/errata"... .......
`........ 5.41 La: and 8.6.5011;
`Overanmpling Convener for Strain Gauge Trunsducenr.. .. ...
`... ... ...D. A. Ker-1h «MD. 5. lefl 1689
`I .‘--/1111 BlCMOS Sample-”andHold Circuit With a Cmtant-lmpetlnnee. Slew/«Enhanced Sampling Gale.... ..........
`............................................... ...M H. Wakayanm. H. Tom'mm. T Tim». and l’ Yuthlda‘ N197 .
`1111MHz 100118 Operational Amplllier with Multipth Nested Miller Compensation Structure... ...........-....1
`‘-
`.................................................. R U.”.E.1chauzier.l.. P T Kcrlrlaort. andJ. H. ”111751113
`I709
`1:
`‘Cumpact Bipolar Class-AB Output Stage Using I~V Power Supply .............................. .. .....“.F I. M T1111: NIB
`.4;
`‘1 Hnghly Eificient CMOS Linc Driver with 80-113 Linearity for lSDN U-lnterfaoe Applications...
`.
`............................................................ H Khmmmabadl. J. Amidjar. andT. R. Peri-rm l723
`l
`' \ Inherently Linear and Compact MOST-Only Current Division Technique ............K Bull undo. I. G M. Get-Ian
`I730
`l55-MHz Clock Recovery Delay- and Plumlnclted Loop ........................... T ”.112de F. Ballade!!! ”36
`51 Bipolar Phase and Frequency Detector [C M Clock Extraction up to 8 Gbls
`.......................................... ..............A..Ponbdckn 0.1011an andH.U.ScIirelh¢r
`. 1(in Integrated Pilate-locked Loop Using AlGaAsK‘iaAs Heterojunction Bipollr Transistors
`............................................. A. W. Butllmrld. K. W. Martin. A K. Oki. andK W. Kalmmhi
`i
`('19 lC's for Clock and Data Regeneration1n Gigabit[21-81:ch Optical-Fiber Receivers
`....................
`.................................................................... ..........s K (5an am”. A 11111211
`1 (' Hz Si Bipolar Amplifier and Mixer IL“: for Coherent Optical Systems
`..... . ....................................
`................ T. Grimm. C Kurlota. Y Kamishl. 0.11m». T. Scuba. M Urhlrowwa. andM. Fujiwara
`“811ml" Chip Set for ID(lb/s Optical Receiver ..... . . ..
`............... T Sumki. M Soda, T Moritawa. II. Term. C. (browns Fajita. II. Takemura.andT. Toalrlm I?!“
`1.11 OH; I.4 Regenerating Demultiplexer with Bit-Rotation Control and 6.l-GH1 Autolatching Phnae~Aligtter lC‘s
`_
`lliung AlGuAs/GuAa HBT Technology... ............. ...... .................. .. ............
`..........................
`.M. Bagheri. K.-C. Wang. M-C. F 011mg. R. B. NuhlingJ’. M. Asked. 0114A. Chm 1781
`’
`3 1nW l.O-GHI. SiliconECL Dual-Modulus Pnescaler lC............................................. ....
`.
`...........................................
`M M14010. I! Starr/11'. M. Ogawa. K Sara. and”. Ichitmwr
`51 Bipolar 280R: Dynamic Frequency Divider ............................................................... .. .
`..................... M. Karim. G Uemura. M. Olmclu'. C. 0mm. H Takemara T. Morikmm. andT.TaKI11'm l799
`'l \\t)—Chlp l .S-GBd Serial Link Interface
`lllOS ,
`............................ R. C. Walker. C. L. Smut. J.-T. Wu. 8. L111. C.-S Yen. T. Ramakoud P. T. Perrwu')
`1 Experimental S-Gh/a l6 :1 l6 Si—Bipolar Outspoint Switch.. ............. .... ...... H.J.Slu'n and M. J. lmdiaro l8|2
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`l747
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`1752 .
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`1175
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`(Commit continued on bad mien
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`SAMSUNG EX. 1008.— 1/12 "
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`IEIEE JOURNAL OF SOLID-STATE CIRCUITS. VOL 27. NO.
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`l2. DECEMBER I992
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`Polysilicon TFT Circuit Design and Performance
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`Alan G. Lewis, Senior Member. IEEE, David D. Lee, Member, IEEE, and Richard H. Bruce, Member, IEEE
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`.-—-._——-.._.J.-——-—-—-—~__-g-a--q-_—
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`Abstmcr—Polysilicon thin-film technology is becoming in-
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`creasingly attractive for active-matrix liquid-crystal displays
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`(AMLCD’s) and other large-area electronic devices, primarily
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`because polysilicon thin-film transistors (TFT’s) can be used to
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`build integrated drive and interface circuitry on large-area
`substrates. Both n- and p-channel polysilicon TFT’s can be fab-
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`ricated, allowing CMOS circuit techniques to be used. How-
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`ever, TFT characteristics are poor in comparison to conven-
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`tional single-crystal MOSFET'S, and relatively coarse design
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`area glass plates {more than 30 cm X 30 cm}, and these limi-
`tations present a number of challenges for circuit design. This
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`paper examines these issues and describes the performance of
`a range of digital and analog circuit elements built using poly-
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`silicon TFT’s. Digital circuit speeds in excess of 20 MHz are
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`reported, along with operational amplifiers with over 80 dB of
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`gain and more than l-MHz unity-gain frequency. Several poly-
`silicon TFT switched-capacitor circuits are also reported and
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`shown to have adequate linearity, output swing, and settling
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`time to form integrated data line drivers on an AMLCD.
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`I.
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`INTRODUCTION
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`NTEREST in circuits built using polysilicon thin-film
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`transistors {TFT‘s} has recently increased for several
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`reasons. Although the inferior performance of these de-
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`vices in comparison to conventional single-crystal MOS—
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`FET’s is well documented [l]—[41, they have the impor-
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`tant advantage of being compatible with fabrication on
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`large-area glass or quartz substrates (more than 30 cm X
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`30 cm). This makes TFT’s usable in applications where
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`the physical size of the circuit must be large, for example
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`if the circuit
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`(AMLCD) [41—[6], a page-width optical scanner ['3'], 18]
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`or a page-width print head [9]. Although there have been
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`many reports of particular devices incorporating polysil-
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`icon TFT's and TFT circuits [4]—[8], there has been little
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`work published so far concentrating specifically on the
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`underlying design issues and performance capabilities of
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`polysilicon TFT circuits. This paper, like the ISSCC pres-
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`entations on which it expands [2], [10],
`is intended to-
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`focus on these subjects. The work described here does not
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`deal with a complete large-area polysilicon TFT elec—
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`tronic device, but rather examines the performance of a
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`range of basic circuit elements, some of which are already
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`used in applications, and some of which show promise for
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`increased functionality on large-area substrates in the fu-
`ture.
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`Manuscript received May 26, 1992'. revised August 20, 1992.
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`The authols are with Xerox Palo Allo Research Center, Palo Alto. CA
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`94304.
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`IEEE Log Number 9204 ISO.
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`The most common, and the most important, application
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`of polysilicon TFT’s remains AMLCD’s. As the various
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`circuit elements are discussed in this paper,
`therefore,
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`their performance will be compared with AMLCD driving
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`requirements. In order to do this, typical drive circuits for
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`AMLCD‘s are briefly reviewed in Section IV. It should
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`be noted, however, that there are other applications for
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`these devices, and more are likely to present themselves
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`as the technology matures and TFT circuit performance
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`improves.
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`ll. POLYSILICON THIN-FILM TECHNOLOGY
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`the main features of polysilicon thin-
`In this section,
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`film technologies are reviewed. Fig.
`1 shows cross sec—
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`tions of n— and p—channel polysilicon TFT’s along with an
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`integrated capacitor. The TFT‘s themselves are very sim-
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`ilar to single-crystal silicon-on-insulator (SOI) MOS—
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`F-ET's, except that the active silicon layer is polycrystal—
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`line instead of monocrystalline. Polysilicon technology
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`also has several of the advantages of 801, including ex-
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`cellent interdevice isolation and negligible parasitic ca-
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`pacitance. The capacitor is formed between the gate and
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`active polysilicon layers by the addition of a single im-
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`plant to dope the active polysilicon layer under the gate.
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`The structure is similar in layout to a polysilicon—to—dif—
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`capacitance associated with either electrode. Both plates
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`of the capacitor can be sufficiently heavily doped that the
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`series resistance remains low, and the capacitance does
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`not vary significantly over the bias ranges typically found
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`nology, differentiated by the annealing process used to
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`crystallize the active polysilicon layer and the maximum
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`processing temperature used [3], [l l]. High-temperature
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`technologies typically use furnace annealing, and at least
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`one high~temperature process step (often during the gate
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`dielectric formation), and this restricts the choice of sub-
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`strate material to quartz. Furnace annealed low-tempera—
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`ture technologies use a similar process to the high—tem—
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`perature technologies, but keep the maximum processing
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`temperature less than about 600°C in order to allow the
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`use of lower cost glass substrates. A third technology
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`variant uses laser annealing to achieve recrystallization
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`and is also compatible with low-cost glass substrates. The
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`laser annealed polysilicon TFT’s have been shown to of-
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`fer the bcst performance, although the technology is not
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`DOW-92008250330 (9 $992 [BEE
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`SAMSUNG EX. 1008 - 3/12
`
`SAMSUNG EX. 1008 - 3/12
`
`

`

`l834
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27, NO. 12. DECEMBER I992
`
`Capacitor
`polysilicon
`9'“
`
`
`Bottom
`Top
`
`NMOS TFT
`
`PMOS TFT
`
`
`
`
`p+
`l1+
`n+
`
`
`
`active polysilicon island
`Quartz substrate
`
`
`Fig. l. Polysilicon TFT‘s with integrated capacitor.
`
`yet mature and poor consistency and uniformity remain
`significant problems. High-temperature quartz-based
`technologies are relatively mature, offer good TFT per—
`formance, and are used for small viewfinder or projection
`displays. Low-temperature glass-based technologies offer
`low cost, although the TFT performance is not usually as
`good as can be achieved with high-temperature technol-
`ogies [12].
`The results reported in this paper were obtained using
`relatively conventional high- and low-temperature fur—
`nace recrystallized polysilicon thin—film devices fabri-
`cated at Xerox PARC. The experimental circuits were
`fabricated on quartz wafers, although the process condi-
`tions and design rules are the same as those used with
`large-area substrates. The device performance achieved is
`comparable with the best reported for similar technologies
`by other authors [1],
`[4]—[8],
`[11]. Although, as dis-
`cussed below, the TFT characteristics are inferior to con-
`
`ventional single—crystal MOSFET‘s, useful circuit per-
`formance can still be achieved. As
`laser annealed
`
`technologies mature, even greater circuit functionality is
`likely to become possible.
`The circuits reported below were all designed using
`layout rules that are relatively coarse in comparison with
`those used in single-crystal technologies. There are sev-
`eral reasons for this. First, of course, are the photolitho-
`graphic and processing restrictions imposed by the need
`to fabricate the TFT’s on very large-area substrates. Sec-
`ond, short-channel effects are relatively severe in polysil-
`icon TFT’s, particularly at high drain voltages [13].
`Third, most large-area devices are constrained to operate
`at supply voltages of at least 15 V; an AMLCD pixel, for
`example, typically requires a total voltage swing of about
`10 V to encompass both drive polarities [14], and‘ with
`sufficient headroom to achieve this using polysilicon TFT
`drivers means a supply voltage of about 15 V.
`
`111. POLYSILICON TFT CHARACTERISTICS
`
`Fig. 2 shows simple l—V characteristics for n- and
`p-channel TFT’s fabricated using the high-temperature
`process; devices fabricated with the low-temperature
`technology are qualitatively similar although the drive
`currents are lower. The poor saturation arises through a
`similar mechanism to that responsible for the kink effect
`in 801 MOSFET’s [15], that is, channel avalanche mul-
`tiplication occurring in the high-field region near the drain
`combined with the floating body of the device. However,
`
`
`
` Drain bias
`
`(2!)
`
`(b)
`
`Fig. 2. High-temperature polysilicon TFT characteristics (W = 50 pm, L
`= 10 pm). (a) NMOS. (b) PMOS.
`
`in polysilicon TFT’s there is an additional mechanism re
`lated to the high trap state density that exaggerates the
`effect of avalanche multiplication still further [16]. Since
`the poor saturation characteristics are not
`related to
`punchthrough or other breakdown effects,
`the off-state
`current is not affected. The impact on digital circuits is
`only minor, and the extra drain current even increases
`switching speeds slightly. However,
`the low output
`impedance presents a greater problem for analog circuit
`design where high impedances are needed to achieve good
`voltage gain.
`The main weakness of polysilicon TFT‘s in comparison
`with single-crystal devices is their relatively low drive
`current, particularly in low-temperature devices. This can
`be seen from Fig. 2, and is further illustrated in Fig. 3
`where the effective channel mobility is plotted as a func-
`tion of normalized gate bias for both an n-channel poly-
`silicon TFT and a conventional 2-p.m gate length MOS—
`FET.
`In each case the gate bias is normalized by the
`typical operating voltage for circuits built using the de-
`vices, 5 V for the MOSFET and 15 V for the polysilicon
`TFT. The peak MOSFET mobility is observed at a gate
`bias a little above threshold, and the degradation at higher
`gate bias is caused by increased surface scattering as the
`channel inversion layer is compressed by the increasing
`gate field. The TFT mobility is about an order of magni—
`tude lower, and increases steadily as the gate drive rises
`until it saturates at a gate voltage of about 10 V; both the
`lower effective channel mobility and the gate bias de-
`pendence are due to the high trap state density in the de-
`vice channel. The low drive current of the polysilicon
`TFT’s has a significant effect on digital circuit speed, but
`in the analog case the effect is even more severe since
`transistors in amplifiers are typically biased with a low
`V05 to keep VDSAT low, and as Fig. 3 shows, under such
`conditions the effective TFT mobility is well below its
`peak value.
`Another important device characteristic, particularly for
`analog circuit applications, is the noise performance. and
`in this respect polysilicon TFT’s are again markedly in-
`ferior to single-crystal devices. Typical noise figures for
`polysilicon TFT’s are about an order of magnitude higher
`than for conventional MOSFET’s; at low frequencies (less
`than about 100 kHz) flicker noise dominates and shows
`roughly the same channel size dependence seen with
`MOSFET’S. At higher frequencies. thermal noise domi-
`nates. The noise performance of polysilicon TFT’s has
`
`SAMSUNG EX. 1008 - 4/12
`
`

`

`LEWIS t! al.: POLYSlLICON TFT CIRCUIT DESIGN AND PERFORMANCE
`
`I 835
`
`Effective channel mobility (cmzv'1s")
`500
`
`tion, good noise immunity, and the difficulty in fabricat-
`ing depletion-mode NMOS devices to act as loads.
`
`$00
`
`‘00
`
`300
`
`200
`
`100
`
`MOSFET (Von: SV)
`
`IV. DRIVE REQUIREMENTS FOR AMLCD‘s
`
`This section reviews the main driving requirements for
`AMLCD’s. These displays represent the major applica-
`tion area for polysilicon TFT’s, and their drive require-
`ments will be used to add perspective to the measured
`performance described below. Fig. 4 shows the main cir-
`cuit elements of an AMLCD along with typical drive
`waveforms. The active matrix is composed of orthogonal
`scan and data lines, and a single pixel is formed at each
`intersection. Each pixel contains a TFT and a capacitor.
`The capacitor is formed by a pair of transparent electrodes
`sandwiching the liquid-crystal material. Plane polarizers
`are placed on each side of the cell so that incoming light
`is first polarized, then passes through the liquid crystal,
`and finally leaves via the second polarizer. The voltage
`applied to the capacitor controls the orientation of the liq-
`uid—crystal molecules, and this in turn controls the twist
`in the plane of polarization of the light traveling through
`the cell. In this way. the transmission oflight through the
`entire module (liquid-crystal cell and polarizers) can be
`controlled [14]. When a scan line goes high, each TFT
`along that line is turned on and the voltages present on
`the data lines are transferred in parallel into all the pixels
`along that line, setting the required transmission pattern.
`When the scan line goes low again, the TFT is turned off,
`the charge remains on the pixel capacitance, and the pixel
`voltage remains fixed until it is rewritten during the next
`frame. The liquid-crystal capacitance is strongly voltage
`dependent and may not be large enough to store the pixel
`voltage until
`the next frame (charge can leak off both
`through the TFT and the liquid-crystal material), and in
`practice an additional storage capacitor is often added to
`the pixel to improve the storage time and linearity.
`Conventional amorphous-silicon TFT AMLCD‘s use
`single-crystal
`integrated circuits to generate the drive
`waveforms illustrated in Fig. 4. A full-color 640 X 480—
`pixel display requires about a dozen chips, and several
`thousand individual connections must be made between
`the active matrix substrate and the driver IC’s. The driver
`
`[C‘s and the very large number of connections contribute
`significantly to the cost of the display. and also play an
`important role in determining long-tenn reliability. The
`use of polysilicon TFT’s allows the driver circuits to be
`fabricated simultaneously with the active matrix on the
`same glass substrate, eliminating the need for external
`driver chips and greatly reducing the number of external
`connections needed to operate the display. In addition,
`integrated drivers allow much denser displays to be built,
`offering the possibility of physically small but high-pixel-
`count light valves for projection applications [18].
`The function of the scan drivers is to generate the scan
`pattern, turning each scan line on in turn. This is usually
`accomplished by a simple shift register and buffers to drive
`the capacitive load presented by the scan lines. As Fig. 4
`
`SAMSUNG EX. 1008 — 5/12
`
`Fig. 3. Polysilicon TFT and single crystal MOSFET channel mobility. VD;
`= 0.1 V. n-channel.
`
`Vas/ Von
`
`TABLE I
`TECHNOLOGY COMPARISON
`
`Low-temperature High-temperature Conventional
`poly-Si TFT
`poly—Si TFT
`MOSFET
`
`NMOS: V, (V)
`[1(ch .
`v '
`~ s
`
`')
`
`PMOS: V, (V)
`,1 (cm’ '
`V‘I ' 5")
`
`2
`40
`
`—8
`20
`
`z
`mo
`
`'3
`so
`
`0.7
`500
`
`-0.7
`200
`
`Operating voltage (V)
`Feature size (pm)
`Substrate
`
`18
`5
`LA glass
`
`IS
`S
`LA quartz
`
`5
`l
`Si wafer
`
`been discussed elsewhere [10], [17], and is not consid-
`ered further here, except to note that since the frequency
`dependence is qualitatively similar to that obtained with
`conventional MOSFET‘s,
`the same switched-capacitor
`techniques used to suppress low-frequency noise in these
`devices are expected to be equally effective with TFT’s.
`Table I summarizes some of the main characteristics of
`
`polysilicon TFT's and compares them with typical values
`for conventional single-crystal MOSFET’s. Data are
`shown for both low- and high-temperature processed
`TFT’s. The low-temperature NMOS TFT’s have lower
`channel mobility, and hence lower drive current, than their
`high-temperature counterparts, but otherwise are similar.
`However, the difference between low- and high-temper-
`ature p-channel TFT’s is more marked. Not only is the
`channel mobility lower in the low-temperature device, but
`the threshold voltage is also much more negative, so that
`the drive current available from a
`low-temperature
`p-channel TFT is more than an order of magnitude lower
`than that available from a high-temperature device [12].
`Despite the weak p-channel TFT's in the low-temperature
`technology, CMOS circuits are still often used for several
`reasons, including design simplicity, low power dissipa-
`
`

`

`l836
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO.
`
`[2. DECEMBER I992
`
`
`
`W Datadrivers /%
`
`V‘V‘V‘V‘V‘V‘V‘V‘V‘V‘V‘V
`
`
`km...
`Shift register}5“" circuit
`(b)
`(a)
`Fig. 4. AMLCD driving. (a) Main circuit elements of AMLCD. (b) Typ—
`ical drive waveforms.
`
`tqu= 355:5 (480 lines)
`16us (1024 lines)
`
`indicates, the total voltage swing needed on the gate lines
`is around 15 V; the scan frequency depends on the display
`size and video format, and is about 30 kHz for a progres-
`sive scan 480-line display and about 60 kHz with l024
`lines. The scan line buffer rise and fall times usually need
`to be around 1 us, although this depends somewhat on the
`display design and resolution. The capacitive load pre-
`sented by a scan line can be very large, ranging from about
`50 pF for a small projection display to as much as 500 pF
`for a large direct-view high—resolution display, and
`achieving fast enough transition times when driving such
`loads often requires very large buffers.
`The data driver circuits are often even more challeng-
`ing. They must perform serial-to-parallel conversion and
`drive the appropriate analog voltages onto the data lines.
`The voltage applied to the liquid-crystal cells must have
`a time—average value close to zero to prevent deterioration
`of the display, and to achieve this the voltage applied to
`each pixel is reversed every frame. The data driver volt-
`age swing must be large enough to accommodate both
`drive polarities, normally requiring a total swing of about
`10 V. The output settling time for the data drivers must
`be fast enough that once the data lines have reached their
`final values there is still time to transfer the signals into
`the pixels. In the case of polysilicon pixel TFT’s, this
`transfer takes only a few microseconds [12], giving target
`settling times of about 30 as for a 480-line display and
`about 12 as with l024 lines. The data-line capacitance is
`usually smaller than the scan-line capacitance, usually be-
`tween about 20 pF for a small projection display and about
`100 pF for a high-resolution direct-view display.
`Fig. 5 illustrates two common data driver architectures.
`In the second [4], [6] (Fig. 5 (b)), analog video data are
`distributed along a common input line, which is linked
`via pass gates to the matrix data lines. The shift register
`turns each pass gate on in turn, and the analog input volt-
`age present at that moment is transferred to the data line,
`where it remains stored on the data-line capacitance once
`the pass gate turns off. The rate at which data can be sam-
`pled from the analog input depends on the speed of the
`shift register generating the sample signals, and the speed
`
`
`
`»
`
`digital
`data in
`
`l'l
`
`matrix data lines
`
`(a)
`
` Shift register
`
` - .'
`
`matrix data lines
`
`0?)
`
`Fig. 5. AMLCD data driver architectures.
`
`with which the data line can be charged via the pass gate;
`usually the latter limitation is the most severe. Normally,
`a separate analog input line is used for each color (red,
`green, blue), and on a large display several sets of input
`lines may be employed, each serving only a fraction of
`the data lines, in order to achieve the necessary data band-
`width. In the first architecture [5] (Fig. 5(a)). serial dig-
`ital data are fe