CERTIFICATION OF TRANSLATION
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`
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`I, Shunsuke Obinata, hereby certify that I am well versed in both Japanese and English
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`languages, that I have over 30 years of experience in translating Japanese technical
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`documents into English, and vice versa, and that the following translation of the patent
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`document JPH_1990214818Horii into English is accurate and complete to the best of my
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`knowledge and ability.
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`January 31, 2015
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`Shunsuke Obinata
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`i
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`SAMSUNG EX. 1007
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`(1) Japanese Patent Application Publication H2-214818
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`(19) Japanese Patent
`Office (JP)
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`(11) Patent Application Publication No.
`(12) Japanese Patent Application
`Publication (A)
`H2-214818
`(43) Publication date: August 27, 1990
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`(51) Int. Cl5
`G 02 F 1/133
`H 01 L 29/784
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`
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`Identification
`Code
`550
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`Filing Number
`8708-2H
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`8624-5F H 01 L 29/78 311 E
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`
`
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` Request for Examination: Not yet requested, Number of claims: 5 (Total of 13 pages)
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`(54) Title of the Invention: Liquid Crystal Device and
`Method for Driving the Device
`(21) Application No.: H01-35067
`(22) Filing date: February 16, 1989
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`
`(72) Inventor: HORII, Juichi
` Central Research Institute, Hitachi Ltd.,
` 1-280 Higashi Koigakubo, Kokubunji, Tokyo
`(72) Inventor: KANEKO, Yoshiyuki
` Central Research Institute, Hitachi Ltd.,
` 1-280 Higashi Koigakubo, Kokubunji, Tokyo
`(72) Inventor: KOIKE, Norio
` Central Research Institute, Hitachi Ltd.,
` 1-280 Higashi Koigakubo, Kokubunji, Tokyo
`(71) Applicant: Hitachi, Ltd.
` 4-6, Kanda Surugadai, Chiyoda-ku, Tokyo
`(74) Agent: NAKAMURA, Junnosuke, patent agent
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`SPECIFICATION
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`1. Title of the Invention: LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR
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`DRIVING THE DEVICE
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`
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`2. Claims
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`1. In a liquid crystal display device, comprising:
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`
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`a first substrate on which multiple gate lines lined up in a row direction, multiple data lines
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`lined up in a column direction in an orthogonal manner, and multiple thin film transistors that are
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`(2) Japanese Patent Application Publication H2-214818
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`formed at the intersections of the rows, each of the intersections being formed as a pixel, are
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`formed, and
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`a second substrate on which a transparent conductor is provided, wherein liquid crystal is
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`is sealed between the two substrates; a liquid crystal display device wherein the above multiple
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`gate lines are divided into groups of k lines (where k is a positive integer not less than two), each
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`of the k data lines of each of the columns being connected to the corresponding one of pixels
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`connected respectively to the k gate lines making up each of the groups; and comprising
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` means for applying the same drive pulse to the above divided k gate lines.
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`2. In the liquid crystal display device according to Claim 1,
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`
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`a liquid crystal display device wherein the drive pulse applied to the k gate lines making up
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`the group is supplied from k gate scan circuits independently of each other or one another.
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`3. In the liquid crystal display device according to Claim 1 or 2, a liquid crystal display device
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`further comprising: k scan circuits for driving the data lines, or k line memories in a data scan
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`circuit for driving the data lines, wherein image signal is written into the pixels of k rows
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`connected respectively to the k gate lines driven independently of each other or one another and
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`simultaneously.
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`4. In a liquid crystal display device, comprising: a first substrate on which multiple gate lines lined
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`up in a row direction, multiple data lines lined up in a column direction in an orthogonal manner,
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`and multiple thin film transistors that are formed at the intersections of the rows are provided,
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`each of the intersections being formed as a pixel, and
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`a second substrate on which a transparent conductor is formed, wherein liquid crystal is
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`sealed between the two substrates; a driving method for liquid crystal display device, wherein
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`the above multiple gate lines are driven simultaneously k gate lines at a time (where k is
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`an integer that is not less than two), and wherein the operation of the k pixels that are driven
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`simultaneously by column is controlled by the respectively connected data lines.
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`5. In the driving method of Claim 4, a driving method for liquid crystal display device wherein
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`(3) Japanese Patent Application Publication H2-214818
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`a pair of odd-numbered gate lines (G1, G3) is driven simultaneously, and
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`after the completion of writing, every other pair of numbered gate lines (G5, G7) and then
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`the next pair (G9, G11), ..., are driven simultaneously and sequentially to conduct the write process
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`to form a first field; wherein next, a pair of even-numbered gate lines (G2, G4) is driven
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`simultaneously, and wherein driving operation in the same manner is performed to form a second
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`field, thereby performing interlacing scan.
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`3. Detailed Description of the Invention
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`[Field of Industrial Application]
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`
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`The present invention relates to an active-matrix liquid crystal display device and a method
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`for driving the device, and more particularly to a liquid crystal display device and a method for
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`driving the device suited for achieving good image quality.
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`[Conventional Technology]
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`An active-matrix liquid crystal display device is disclosed in, for example, Japanese Patent
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`Application Publication No. S54-018886.
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`Fig. 2 is a circuit diagram of an example of an active-matrix liquid crystal display device.
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`In Fig. 2, the reference numerals 21 and 22 denote a liquid crystal cell and a charge storage
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`capacitor, respectively. The numeral 23 denotes a thin film transistor (hereinafter abbreviated as
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`TFT) connected to one of the two electrodes of the liquid crystal cell 21. These components make
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`up each pixel. The numeral 24 denotes multiple data lines, the number of which is n, collectively.
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`Each of the data lines D1 to Dn is connected as a common data line to the TFTs of the
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`corresponding column in the active matrix. The numeral 25 denotes multiple gate lines, the
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`number of which is m, collectively. Each of the gate lines G1 to Gm is connected as a common
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`scanning line to the TFTs of the corresponding row in the active matrix. The numeral 26 denotes a
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`driver circuit that applies scanning pulses to the gate lines G1 to Gm sequentially (hereinafter
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`referred to as "gate driver"). The numeral 27 denotes a scanning circuit that applies image signals
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`for the horizontal scan to the data lines D1 to Dn in parallel (hereinafter referred to as "data driver").
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`The numeral 28 denotes a transparent common electrode that is connected on a common basis to
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`the other electrode of the liquid crystal cell which is formed on the substrate facing across the
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`substrate on which the TFT is formed and the liquid crystal.
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`Next, the drive operation of an active-matrix liquid crystal display device will now be
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`explained.
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`Fig. 3 is a schematic view of an example drive waveforms.
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`In Fig. 3, in synchronization with the applying of a pulse VGi to the i-th gate line Gi,
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`providing the voltage Von necessary to turn on the TFT, an image signal voltage VSj is applied to
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`the j-th data line Dj. As a result, a charge is stored at the liquid crystal capacitance and the storage
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`capacitance of a pixel Cij, and the writing of an image signal is performed. The writing is
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`completed during a time period when the gate voltage is VON, that is, during t1 ~ t1 + ∆t. The
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`voltage of the pixel Cij is retained at VSj until the next writing of a signal at time t1 + T, that is,
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`after the lapse of one field cycle T, and the gate voltage remains at VOFF.
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`In line-sequential scan, all of the TFTs connected to the i-th gate line Gi are turned on at
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`the same time, and signal writing is performed in the same manner as above. At the time of the
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`completion of signal writing for the i-th row, a pulse VGi+1 is applied to the i+1-th gate line Gi+1.
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`As a result, all of the TFTs connected to the i+1-th gate line Gi+1 are turned on at the same time,
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`and signal writing is performed in the same manner as above.
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`Through sequential gate voltage application, TFTs are turned on sequentially, and pixels
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`are driven by this line-sequential scan.
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`[Problems to be Solved by the Invention]
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`
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`In principle, an active-matrix liquid crystal display device is driven as described above. In
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`actual driving, however, a gate voltage pulse propagation delay must be taken into consideration.
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`Fig. 4 is a waveform chart of a gate pulse and a delayed gate pulse.
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`As illustrated in Fig. 4, even when a gate pulse applied to a gate line has a rectangular
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`(5) Japanese Patent Application Publication H2-214818
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`waveform, due to a delay caused by gate-line capacitance or wiring resistance, waveform
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`deformation occurs with a rising delay tr and a falling delay tf near an edge that is the opposite of a
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`gate-driver-side edge. Therefore, in Fig. 4, an effective writing time period is ∆t - tr, which is
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`shorter than ∆t. For this reason, it is not possible to perform image signal writing fully.
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`
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`The problem described above is especially critical when polysilicon (poly-Si) is used as the
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`material of gate lines. Since polysilicon, which is advantageous for forming elements, has greater
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`resistance than that of metal, the propagation delay described above is greater, meaning that the
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`effective writing time period is shorter. This makes it difficult to use polysilicon as the material of
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`gate lines, resulting in an increase in the number of manufacturing steps and cost.
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`
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`An object of the present invention is to provide an active-matrix liquid crystal display
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`device that is less susceptible to the effects of the gate pulse delay described above, and a method
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`for driving the device.
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`[Means for Solving the Problems]
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`To achieve the above object, the present invention is configured as described in the Claims.
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`In prior art, a drive pulse is applied to one gate line at a time for sequential scan of multiple
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`gate lines. In contrast, in the present invention, a drive pulse is applied to multiple (k) gate lines
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`simultaneously. This achieves an approximately k-times increase in TFT ON time.
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`The fundamental structure of the present invention is described in Claim 1, which
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`corresponds to, for example, an embodiment of Fig. 1 described later.
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`Claim 2 corresponds to, for example, embodiments of Figs. 6 and 13 described later.
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`Claim 3 corresponds to, for example, an embodiment of Fig. 7 described later.
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`A driving method according to the present invention is recited in Claim 4, which
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`corresponds to, for example, an embodiment of Figs. 1 and 5 described later.
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`An interlace scan driving method is recited in Claim 5, which corresponds to, for example,
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`an embodiment of Fig. 12 described later.
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`[Operation of the Invention]
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`(6) Japanese Patent Application Publication H2-214818
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`
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`In the present invention, a gate pulse is applied to first, second, ..., k-th row gate lines
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`simultaneously to put TFTs of k rows into an ON state. Through data lines, writing into first,
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`second, ..., k-th pixels is performed. After the completion of writing for the rows, a pulse is
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`applied to the next k rows. Because of simultaneous signal writing for the k rows, it is possible to
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`allocate time that is k times as long as that of prior art to writing operation. Therefore, in the
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`present invention, time that can be utilized for signal writing is k∆t - tr. Consequently, it is
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`possible to solve the prior-art problems arising from shortened writing time due to a propagation
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`delay.
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`[Embodiments]
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`Embodiment 1
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`Fig. 1 is a circuit diagram that illustrates the basic structure of an active-matrix liquid
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`crystal display device according to an embodiment of the present invention. This embodiment
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`shows an example in which the number of gate lines that are driven at the same time is two (k = 2).
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`In Fig. 1, the reference numerals denote the following components, respectively: 11 ---
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`matrix-array liquid crystal cells; 12 --- charge storage capacitors; 13 --- TFTs connected to one
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`respective electrodes of the respective liquid crystal cells 11; 14 --- data lines D1 to D2n common-
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`connected to the data electrodes of the TFTs; 15 --- gate lines G1 to Gm common-connected to the
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`gate electrodes of the TFTs; 16 --- a gate driver for applying scanning pulses to the gate lines
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`sequentially; 17 --- a data driver providing a function for applying image signals to the data lines
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`in parallel; and 18 --- a transparent common electrode provided on a counter substrate, with liquid
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`crystal sandwiched in a sealed manner between a TFT substrate and said counter substrate.
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`In Fig. 1, the data electrodes of TFTs connected to odd-numbered gate lines G1, G3, ..., Gm-1
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`are connected to odd-numbered data lines D1, D3, ..., D2n-1, and the data electrodes of TFTs
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`connected to even-numbered gate lines G2, G4, ..., Gm are connected to even-numbered data lines
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`D2, D4, ..., D2n. Therefore, the number of data lines connected to one column is two, which is
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`twice as many as that of the circuit illustrated in Fig. 2.
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`(7) Japanese Patent Application Publication H2-214818
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`
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`In the present embodiment, in the interest of simplicity of explanation, it is assumed that
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`the number of gate lines that are driven at the same time is two (k = 2). However, k may be any
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`integer is not less than two. In the present invention, the number of data lines needed is k times as
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`great as that of a prior-art structure. For example, if k = 2, the number of data lines needed is
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`twice as great as that of a prior-art structure; three times if k = 3.
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`
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`In the present embodiment, a gate pulse is applied to two gate lines G1 and G2, which are
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`arranged next to each other, at the same time, thereby putting the TFTs connected to these two gate
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`lines into an ON state at the same time. Writing into pixels of the first row (which corresponds to
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`G1) is performed through the odd-numbered data lines D1, D3, ..., D2n-1, and writing into pixels of
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`the second row (which corresponds to G2) is performed through the even-numbered data lines D2,
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`D4, ..., D2n.
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`After the completion of writing for the first and second rows in this way, a gate pulse is
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`applied to gate lines G3 and G4. In like manner, a gate pulse is applied sequentially to paired gate
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`lines, G5 and G6, G7 and G8, ....
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`
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`Since signal writing is performed simultaneously for one paired row at a time, that is, for
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`paired rows sequentially, it is possible allocate time that is twice as long as that of a prior-art
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`structure to each writing. This means the doubling of theoretical gate pulse application time.
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`
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`Fig. 5 is a set of diagrams illustrating a driver circuit and drive signal waveforms according
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`to the embodiment illustrated in Fig. 1, wherein (a) is a block diagram of the driver circuit of the
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`active-matrix liquid crystal display device illustrated in Fig. 1, (b) is a timing chart of drive signals,
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`and (c) is a voltage waveform chart of a gate pulse and a delayed gate pulse.
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`First, in Fig. 5 (a), the liquid crystal panel 51 is made up of many liquid crystal pixels
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`arranged in a matrix array illustrated in Fig. 1. The numeral 52 denotes a gate driver (which
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`corresponds to 16 in Fig. 1) for driving the liquid crystal panel 51. If two gate lines are driven at
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`the same time, shift registers whose number is one half of the number of gate lines are enough for
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`making up the gate driver 52. In general, shift registers whose number is 1/k of the number of gate
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`lines are enough for making up the gate driver 52 when k gate lines are driven at the same time. In
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`the present embodiment, for example, dual-phase clock pulses φ2,
` are used for pulse-shift
`operation of the shift registers to output a scanning pulse SH for each gate line. The numeral 53
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`denotes a data driver (which corresponds to 17 in Fig. 1) that is made up of shift registers, line
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`switches, line memories, and the like. The numeral 54 denotes a video signal input, and the
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`numeral 55 denotes a sync signal control unit.
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`Operation will now be explained with reference to the timing chart of Fig. 5 (b).
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`, by which shift registers are
`For example, upon input of dual-phase clock pulses φ1,
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`driven, and a vertical sync pulse SV, image signals for two rows are stored into line memories
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`inside the data driver 53. Triggered by a line switch pulse SL, the first one of the two-row image
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`signals stored in the line memories is output to the odd-numbered data lines D1, D3, ..., D2n-1; the
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`other, that is, for the second row, is output to the even-numbered data lines D2, D4, ..., D2n. In this
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`way, image signals for two rows are written into pixels at the same time through two data lines
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`D2n-1 and D2n. By this means, it is possible to utilize writing time for two rows, that is, 2∆t.
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`
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`A gate pulse and a delayed gate pulse in the operation described above are illustrated in Fig.
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`5 (c).
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`
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`As illustrated in this drawing, a gate pulse writing time period of the present embodiment
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`is 2∆t. Therefore, an effective writing time period, which can be utilized actually, is 2∆t - tr, which
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`is longer than the effective writing time period of prior-art non-paired writing by ∆t. Therefore, it
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`is possible to solve the problems arising from shortened writing time due to a gate pulse
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`propagation delay.
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`In the embodiment illustrated in Figs. 1 and 5, a case where the number of lines driven at
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`the same time for writing is two is shown. The number may be increased to three, four, ..., k. By
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`this means, it is possible to make writing time approximately k times as long as that of prior art (k ⋅
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`∆t).
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`Embodiment 2
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`(9) Japanese Patent Application Publication H2-214818
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`
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`Fig. 6 is a set of diagrams of a second embodiment of the present invention, wherein (a) is
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`a block diagram of an active-matrix liquid crystal display device, and (b) is its driving voltage
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`waveform chart. In the present embodiment, a gate driver for outputting a gate pulse for driving
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`odd-numbered gate lines is provided separately from a gate driver for outputting a gate pulse for
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`driving even-numbered gate lines.
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`In Fig. 6, the numeral 61 denotes liquid crystal pixels each of which is made up of a liquid
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`crystal cell, a charge storage capacitor, a TFT, and a pixel electrode. The numeral 62 denotes a
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`data driver. The numerals 63 and 64 denote gate drivers that drive writing target gate lines
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`independently at the same time. The gate driver 63 drives odd-numbered gate lines. The gate
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`driver 64 drives even-numbered gate lines.
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`
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`As illustrated in Fig. 6 (b), the circuit described above is driven by means of a set of drive
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`pulses including line memory switch pulse SL1 and SL2, dual-phase clock pulses φ21,
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` and
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`, and gate pulses SH1 and SH2. The gate driver 63 outputs a signal for driving the gate
`φ22,
`line of the first row, and, at the same time, the gate driver 64 outputs a signal for driving the gate
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`line of the second row. Subsequently, the gate lines are driven in the same manner as above.
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`The present embodiment, too, produces the same effects as those of Embodiment 1; that is,
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`it is possible to solve the problems arising from shortened writing time due to a gate pulse
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`propagation delay.
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`
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`In the above explanation, the gate drivers 63 and 64 output gate pulses at the same time;
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`that is, operation that is conceptually the same as that of Fig. 1 is performed. However, in the
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`circuit illustrated in Fig. 6, the odd-numbered pixels and the even-numbered pixels can be
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`controlled completely independently of each other. Therefore, the concept of the present
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`embodiment is effective even when applied to other kind of control, for example, interlace control
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`described later with reference to Figs. 12 and 13.
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`
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`In the present embodiment, a case where k = 2 is taken as an example. Needless to say,
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`however, k gate drivers may be provided for independently driving k gate lines at the same time.
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`(10) Japanese Patent Application Publication H2-214818
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`Embodiment 3
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`Fig. 7 is a block diagram of an active-matrix liquid crystal display device according to a
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`third embodiment of the present invention.
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`
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`In the present embodiment, in the embodiment described above with reference to Fig. 6, a
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`data driver for driving pixels connected to odd-numbered gate lines is provided separately from a
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`data driver for driving pixels connected to even-numbered gate lines.
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`
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`In Fig. 7, the numeral 71 denotes liquid crystal pixels that are the same as those of the
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`foregoing embodiments. The numerals 74 and 75 denote gate drivers (which correspond to 63 and
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`64 of Fig. 6, respectively). Two data drivers, 72 and 73, include line memories for image signal
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`storage, shift registers, and the like, and are connected independently of each other, that is, one to
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`odd-numbered data lines corresponding to odd-numbered gate lines scanned by one of the two gate
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`drivers, 74 and 75, and the other to even-numbered data lines corresponding to even-numbered
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`gate lines scanned by the other gate driver. The data drivers 72 and 73 apply data signals for
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`writing when pulses are applied to two gate lines respectively by the gate drivers 74 and 75. The
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`number of data drivers may be k when the number of gate lines that are scanned at the same time
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`is k. For a simpler explanation, a case where k = 2 is shown here.
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`
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`With the above configuration, it is possible to perform simultaneous image signal writing,
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`with scanning via gate lines by the gate drivers 74 and 75, by reading image signals for one pair of
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`scanning lines at a time, that is, for paired rows sequentially, from a memory in which image
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`signals constituting a frame picture for display on one external screen are stored.
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`
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`It is also possible to perform signal writing by exclusively providing independent k line
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`memory units, such that the shift registers constituting the above data drivers are provided in k
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`registers on a common basis.
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`Embodiment 4
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`Fig. 8 is a signal waveform chart of an Embodiment 4 of the present invention.
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`In the circuit illustrated in Fig. 7, it is possible to shift the entire writing timing by t0 by
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`(11) Japanese Patent Application Publication H2-214818
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`delaying the rising of the line switch pulse SL2 by t0 from the rising of the line switch pulse SL1.
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`Since the delay time t0 can be set arbitrarily, it is possible to improve flickering, etc., on the screen
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`as compared with simultaneous writing.
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`Embodiment 5
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`A fifth embodiment of the present invention is illustrated in Fig. 9.
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`In the present embodiment, gate-line driver connection is paired for modification of the
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`embodiment illustrated in Fig. 1 so that a single output of a gate driver can be used for driving two
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`gate lines at the same time. In this embodiment, gate-line driver connection is grouped for two
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`gate lines. Gate-line driver connection may be grouped for k gate lines for simultaneous k driving.
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`
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`In Fig. 9, the numeral 91 denotes liquid crystal pixels that are the same as those of the
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`foregoing embodiments. The numeral 92 denotes a data driver (which corresponds to 17 in Fig. 1),
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`and the numeral 93 denotes a gate driver.
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`Embodiment 6
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`A sixth embodiment of the present invention is illustrated in Fig. 10.
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`In the foregoing embodiments, a case where k = 2 is described for a simpler explanation.
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`However, k may be 3, 4, 5, ... as described earlier. The embodiment illustrated in Fig. 10 shows a
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`case where k = 4, as one example.
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`The numeral 101 denotes pixels. The numerals 102 and 103 denote a data driver and a
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`gate driver, respectively. D1, D2, D3, ..., D4n denote data lines. The number of data lines needed in
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`this embodiment is four times as great as that of Fig. 4.
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`
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`Fig. 11 is a planar view that illustrates a specific configuration of the elements of the
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`embodiment illustrated in Fig. 10.
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`The layout of liquid crystal pixels, TFTs, gate lines g1 to g9, and data lines is illustrated in
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`this planar view. A so-called triangular layout is shown, in which green pixels G, blue pixels B,
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`and red pixels R for color display are arranged in a "triangularly" staggered manner.
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`
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`Each black circle in this drawing denotes a TFT.
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`(12) Japanese Patent Application Publication H2-214818
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`The gate lines are grouped into , , and . In each of the groups, the constituent gate
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`lines of the group (e.g., g1 to g4) are driven at the same time.
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`Embodiment 7
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`A seventh embodiment of the present invention is illustrated in Fig. 12.
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`In the foregoing explanation of the operation of the present invention, interlace scan was
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`not discussed. In the present and subsequent embodiments, interlace scan is taken into
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`consideration.
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`In Fig. 12, a gate pulse is applied to a pair of odd-numbered gate lines (G1, G3)
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`simultaneously. After the completion of writing, a gate pulse is applied to every other pair of odd-
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`numbered gate lines (G5, G7) simultaneously, and then to the next (G9, G11), ..., simultaneously to
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`form a first field by this sequential paired every-other-line application. Next, a gate pulse is
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`applied to a pair of even-numbered gate lines (G2, G4) simultaneously. A second field can be
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`formed in the same manner as above. By this means, it is possible to perform interlace scan.
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`In the present embodiment, pixels connected to the 1st, 2nd, 5th, 6th, 9th, 10th, ... gate
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`lines are connected to the same data lines, and pixels connected to the 3rd, 4th, 7th, 8th, 11th,
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`12th, ... gate lines are connected to the same data lines.
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`Embodiment 8
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`An eighth embodiment of the present invention is illustrated in Fig. 13.
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`In the present embodiment, in the circuit illustrated in Fig. 12, two gate drivers 123 and
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`124 are provided so that odd-numbered gate lines G1, G3, G5, ..., G2n-1 and even-numbered gate
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`lines G2, G4, G6, ..., G2n can be driven independently of each other. With these two gate drivers, it
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`is possible to form first and second fields independently of each other.
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`If the dual-data-driver configuration of the circuit illustrated in Fig. 7 is additionally
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`adopted, when first and second fields are formed, it is possible to form a picture by sequential gate
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`pulse application from the top simultaneously for these two fields. By this means, it is possible to
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`form two fields simultaneously in the length of time required to form one field, thereby doubling
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`(13) Japanese Patent Application Publication H2-214818
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`writing time.
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`Embodiment 9
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`A ninth embodiment of the present invention is illustrated in Fig. 14.
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`Though the method of gate pulse application is the same as that of Fig. 12, in the present
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`embodiment, a switch 134 is provided separately from a gate register 133. Switching is performed
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`for a pair of gate lines (G1, G2) by means of the switch 134 for each field, followed by switching
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`for gate-line pairs (G3, G4), (G5, G6), ... in the same way. With this switching, shift registers whose
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`number is one half of the number of gate lines are enough for making up the gate driver 133. It is
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`possible to reduce the number of shift registers needed for making up the gate driver 133 to 1/k of
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`the number of gate lines when k gate lines are driven at the same time.
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`[Effects of the Invention]
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`With the present invention, in an active-matrix liquid crystal display device, it is possible
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`to significantly increase writing time as compared with prior art. Therefore, it is possible to solve
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`problems arising from shortened signal writing time due to a gate pulse propagation delay caused
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`by high resistance or parasitic capacitance of gate wiring. Therefore, the invention provides the
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`excellent benefit of achieving favorable and stable image quality.
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`Because of a significant increase in the length of effective writing time, the invention
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`makes it possible to use polysilicon as the material of gate lines, which has been difficult in the
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`past, resulting in a reductions in the number of manufacturing steps and cost.
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`The number of data lines needed in the invention is larger than that of prior art. However,
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`as the size of a liquid crystal display device increases, and as higher definition/resolution is
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`demanded on the market, the number of gate lines increases, which makes the length of writing
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`time per gate line insufficient. In such a case, the invention produces remarkable effects, even
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`though a larger number of data lines are necessary. The invention is especially effective when
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`applied to large-screen high-definition/resolution active-matrix liquid crystal display devices,
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`which require an increase in the number of gate lines, an increase in interconnect resistance, etc.
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`(14) Japanese Patent Application Publication H2-214818
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`4. Brief Description of the Drawings
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`Fig. 1 is a circuit diagram of an active-matrix panel according to an exemplary
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`embodiment of the invention;
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`Fig. 2 is a circuit diagram of an active-matrix panel according to an example of prior art;
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`Fig. 3 is a signal waveform diagram of a prior-art panel driving method;
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`Fig. 4 is a signal waveform diagram for explaining a propagation delay;
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`Fig. 5 is a set of diagrams illustrating a driver circuit and drive signal waveforms according
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`to the embodiment of the invention;
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`Fig. 6 is a set of block and signal-waveform diagrams of a second embodiment of the
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`present invention;
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`Fig. 7 is a block diagram of a third embodiment of the invention;
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`Fig. 8 is a signal waveform diagram of a fourth embodiment of the invention;
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`Fig. 9 is a block diagram of a fifth embodiment of the invention;
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`Fig. 10 is a block diagram of a sixth embodiment of the invention;
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`Fig. 11 is a plan view that illustrates a specific example of the display elements of the
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`invention;
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`Fig. 12 is a block diagram of a seventh embodiment of the invention;
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`Fig. 13 is a block diagram of an eighth embodiment of the invention; and
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`Fig. 14 is a block diagram of a ninth embodiment of the invention.
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`<Explanation of Codes>
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`11, 21 liquid crystal cell
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`12, 22 charge storage capacitor
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`13, 23 TFT
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`14, 24 data line
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`15, 25 gate line
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`(15) Japanese Patent Application Publication H2-214818
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`16, 26, 52 gate driver
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`17, 27, 53 data driver
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`51 liquid crystal panel
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`54 image signal input
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`55 sync signal control unit
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`Agent: Patent Attorney, Junnosuke NAKAMURA
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`(16) Japanese Patent Application Publication H2-214818
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`FIG. 2
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`FIG. 1
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`(17) Japanese Patent Application Publication H2-214818
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`FIG. 5
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`FIG. 3
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`FIG. 4
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`(18) Japanese Patent Application Publication H2-214818
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`FIG. 6 (b)
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`FIG. 8
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`FIG. 5 (c)
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`(19) Japanese Patent Application Publication H2-214818
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`FIG. 8
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`FIG. 6 (a)
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`(20) Japanese Patent Application Publication H2-214818
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`FIG. 9
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`FIG. 10
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`FIG. 7
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`(21) Japanese Patent Application Publication H2-214818
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`(22) Japanese Patent Application Publication H2-214818
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`FIG. 12
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`FIG. 13
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`FIG. 11
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`(23) Japanese Patent Application Publication H2-214818
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`FIG. 14
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