United States Patent [19]
`Takeuchi et ai.
`
`[54] SEMICONDUCTOR MEMORY DEVICE
`HAVING A PLURALITY OF MEMORY CELL
`TRANSISTORS ARRANGED TO
`CONSTITUTE MEMORY CELL ARRAYS
`
`[75]
`
`Inventors: Yuji Takeuchi, Kawasaki; Toshiharu
`Watanabe, Yokohama; Seiichi
`Aritome, Yokohama; Hiroshi
`Watanabe, Yokohama; Kazuhiro
`Shimizu, Yokohama, all of Japan
`
`[73] Assignee: Kabushiki Kaisha Toshiba, Kawasaki,
`Japan
`
`[21] Appl. No.: 09/008,627
`
`[22] Filed:
`
`Jan. 16, 1998
`
`[30]
`
`Foreign Application Priority Data
`
`Jan. 20, 1997
`
`[JP]
`
`Japan .................................... 9-007262
`
`[51]
`
`Int. CI? ....................... HOiL 29/708; ROIL 21/336;
`G11C 16/04
`[52] U.S. CI. ...................... 257/315; 365/185.17; 438/258
`[58] Field of Search ....................... 257/315; 365/185.17;
`438/258
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,031,011
`5,554,867
`5,568,421
`5,680,347
`5,682,350
`5,698,879
`
`........................ 257/319
`7/1991 Aritome et al.
`9/1996 Ajika et al. ............................. 257/314
`10/1996 Aritome ............................. 365/185.17
`10/1997 Takeuchi et al. .................... 365/185.7
`10/1997 Lee et al. ........................... 365/185.17
`12/1997 Aritome et al.
`........................ 257/315
`
`FOREIGN PATENT DOCUMENTS
`
`3-283662 12/1991
`
`Japan.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006157056A
`[11] Patent Number:
`[45] Date of Patent:
`
`6,157,056
`Dec. 5, 2000
`
`5 -3326
`7-202143
`
`1/1993
`8/1995
`
`Japan.
`Japan.
`
`Primary Examiner-Olik Chaudhuri
`Assistant Examiner-Howard Weiss
`Attorney, Agent, or Firm-Banner & Witcoff, Ltd.
`
`[57]
`
`ABSTRACT
`
`The semiconductor memory device comprises first and
`second memory cell rows each constructed by connecting a
`plurality of memory cell transistors, and third and fourth
`memory cell rows which are provided to be respectively
`adjacent to the first and second memory cell rows, such that
`element separation regions are respectively provided
`between adjacent memory cell rows. First and second tran(cid:173)
`sistors are connected between a drain or a source of the first
`memory cell row and a drain or a source of the second
`memory cell row. Gate electrodes of the first and third
`transistors are connected by a first gate line, and gate
`electrodes of the second and fourth transistors are connected
`by a second gate line. The first and second transistors are
`connected to a data line by a first contact. The third and
`fourth transistors are connected to a data line by a second
`contact. A first spacing element is connected between the
`first and second transistors and a second spacing element is
`connected between the third and fourth transistors, so that
`the distance between the first and second contacts is wid(cid:173)
`ened. The first contact is provided between the first transistor
`and the first spacing element. The second contact is provided
`between the fourth transistor and the second spacing ele(cid:173)
`ment. The first spacing element is connected through the
`third gate line to the second spacing element.
`
`20 Claims, 31 Drawing Sheets
`
`1
`
`12
`
`f - -
`
`- -
`
`11
`j=:::
`L_'"'--L........
`
`125
`
`-"'"- -
`
`12C
`
`126
`
`L
`m
`
`SHARP EXHIBIT 1005
`
`Page 1 of 44
`
`

`

`u.s. Patent
`
`US. Patent
`
`Dec. 5,2000
`Dec. 5, 2000
`
`Sheet 1 of 31
`Sheet 1 0f 31
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`6,157,056
`6,157,056
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`FIG.5
`(PRIOR ART)
`
`Page 3 of 44
`
`

`

`u.s. Patent
`US. Patent
`
`Dec. 5,2000
`Dec. 5,2000
`
`Sheet 3 0f 31
`Sheet 3 of 31
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`6,157,056
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`Page 4 of 44
`
`Page 4 of 44
`
`

`

`u.s. Patent
`
`Dec. 5,2000
`
`Sheet 4 of 31
`
`6,157,056
`
`C01
`
`FIG. 7 (PR lOR ART)
`
`C02
`
`FIG. 8 (PRIOR ART)
`
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`DL2
`
`DL3
`
`51
`
`FIG.9
`(PRIOR ART)
`
`Page 5 of 44
`
`

`

`u.s. Patent
`
`Dec. 5,2000
`
`Sheet 5 of 31
`
`6,157,056
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`
`Page 7 of 44
`
`

`

`u.s. Patent
`
`Dec. 5,2000
`
`Sheet 7 of 31
`
`6,157,056
`
`1
`
`FIG. 12
`
`F 16.13
`
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`
`DL2
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`FIG.14
`
`Page 8 of 44
`
`

`

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`Page 9 of 44
`
`

`

`U.S. Patent
`
`Dec. 5,2000
`
`Sheet 9 of 31
`
`6,157,056
`
`FIG. 168
`
`FIG.16C
`
`3
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`3
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`
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`
`FIG.178
`DL3
`
`DL1
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`
`FIG. 17C
`
`Page 10 of 44
`
`

`

`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 10 of 31
`
`6,157,056
`
`FIG.18
`
`BATCH-
`ERASURE
`FLOATING
`DL1
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`FIG.39
`
`Page 11 of 44
`
`

`

`SGll SG33
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`FIG.19
`
`Page 12 of 44
`
`

`

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`
`Page 13 of 44
`
`

`

`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 13 of 31
`
`6,157,056
`
`51
`
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`
`FIG.21
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`FIG.23
`
`Page 14 of 44
`
`

`

`CG1
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`
`Page 15 of 44
`
`

`

`u.s. Patent
`US. Patent
`
`Dec. 5,2000
`Dec. 5, 2000
`
`Sheet 15 0f 31
`Sheet 15 of 31
`
`6,157,056
`6,157,056
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`u.s. Patent
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`Dec. 5, 2000
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`Sheet 16 of 31
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`Page 17 of 44
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`u.s. Patent
`US. Patent
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`Dec. 5,2000
`Dec. 5, 2000
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`Sheet 17 0f 31
`Sheet 17 of 31
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`Page 18 of 44
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`u.s. Patent
`US. Patent
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`Dec. 5,2000
`Dec. 5, 2000
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`Sheet 18 0f 31
`Sheet 18 of 31
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`Page 19 of 44
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`Page 19 of 44
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`

`

`u.s. Patent
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`Dec. 5, 2000
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`Sheet 19 of 31
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`6,157,056
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`Page 20 of 44
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`

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`u.s. Patent
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`Dec. 5, 2000
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`Sheet 20 of 31
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`Page 21 of 44
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`

`u.s. Patent
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`Dec. 5, 2000
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`Sheet 21 of 31
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`6,157,056
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`

`

`u.s. Patent
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`Dec. 5, 2000
`
`Sheet 25 of 31
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`6,157,056
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`Page 26 of 44
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`Page 27 of 44
`
`

`

`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 27 of 31
`
`6,157,056
`
`BATCH-
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`Page 28 of 44
`
`

`

`u.s. Patent
`
`US. Patent
`
`Dec. 5, 2000
`Dec. 5, 2000
`
`Sheet 28 of 31
`Sheet 28 0f 31
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`6,157,056
`6,157,056
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`Page 29 of 44
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`
`
`
`

`

`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 29 of 31
`
`6,157,056
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`Page 30 of 44
`
`

`

`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 30 of 31
`
`6,157,056
`
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`1
`1
`
`SLl
`
`:
`1
`
`SL2
`
`SL3
`
`SL4
`
`1
`1
`1
`1
`1
`I
`1
`1
`1
`
`I
`L _______________________________________ ~
`
`)
`
`MC2
`
`FIG.50
`
`BL
`
`"
`
`MC4
`
`BL
`
`1
`
`:
`
`Page 31 of 44
`
`

`

`u.s. Patent
`
`Dec. 5, 2000
`
`Sheet 31 of 31
`
`6,157,056
`
`,oJ' MEMORY CELL ARRAY
`r---------------- L - - - - - - - - - - - - - - - - - - ___ ,
`I
`I
`
`3-
`
`- - ----;-+-__...--+---i~------i-_+_~...-+_...;._+_--
`
`I
`I
`I
`I
`----.-------~------~--------+-----SL
`I
`1~
`i
`12,,-
`i SGS1 -~---M-C l--i---ft----
`+-
`-
`MC
`1 \ \
`I
`-
`____ J_
`- ----~-
`I CG1
`I
`I
`I
`: CG2
`I
`I
`: CG3 ----4-+-~~-+-+----~+-__..._4_4_+---
`I
`I
`I
`I CG4 ----~r-~_r_r~----~--~~~+_--
`I
`I
`I
`I
`I
`I
`I
`
`SGD1 --~----r---------~---+--
`121r-"
`12A
`SGD3-~-&-~----~r--~-
`122
`SGD2 -'--&-~--------tir--~-
`CG5 ----T---~~~r---_r---+_+_T~--
`
`CG6 ----~-+_+_~--~~~~~~-
`
`I
`I
`I
`I
`I
`I
`I
`____ ,-.1
`)
`
`CG7
`
`--
`
`CG8
`
`--
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`L
`L
`-----~ ,
`SGS2 12_~_tt---M-C-2__i-12-~___1~----M-C-4~-
`I
`I
`I
`----~------~----~~------+-----SL I
`I
`I
`I
`BL
`BL
`L-------------- ________________________ J
`I
`FIG.51
`
`Page 32 of 44
`
`

`

`6,157,056
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`HAVING A PLURALITY OF MEMORY CELL
`TRANSISTORS ARRANGED TO
`CONSTITUTE MEMORY CELL ARRAYS
`
`BACKGROUND OF THE INVENTION
`
`2
`narrowed, and then, data line contacts CD1, CD2, and CD3
`as well as data lines DL1, DL2, and DL3 are arranged to be
`close to each other, so that processing has become more
`difficult and causes an error in operation. For example,
`5 short-circuiting of wires tends to easily occur due to errors
`in formation of a resist pattern in steps of forming data lines
`DLl, DL2, and DL3 by a photolithography method or in
`etching of a conductive material used for wires.
`In addition, the widths of data lines DLl, DL2, and DL3
`10 to be connected with data line contacts CD1, CD2, and CD3
`are normally designed to be larger than the opening diameter
`of each contact hole. This is performed so as to allow
`dimension errors in alignments, which are caused in a
`photolithography step and an etching step. In this case, the
`15 interval distance between adjacent data lines DL1, DL2, and
`DL3 is much narrower than the interval distance between the
`data line contacts CD1, CD2, and CD3. It is therefore more
`difficult to perform processing so that each of the data lines
`and contacts might not be short-circuited.
`On the same grounds as described above, the width of a
`portion such as a transistor 12 or the like to be connected to
`the data line contacts CDI to CD3 is designed to be larger
`than the opening diameter of each contact hole, in several
`cases. In this case, the interval distance between adjacent
`25 element regions is narrowed, so that formation of an element
`separation region 2 is affected. For example, a punch(cid:173)
`through occurs between adjacent element regions, rendering
`it difficult to obtain a electric separation. In order to avoid
`this situation, the width of the element separation region 2
`30 must be widened, thereby obstructing high integration of
`elements.
`Thus, in accordance with high integration of elements,
`short-circuiting of wires tends to easily occur at data line
`contacts CDI to CD3 or at data lines DLI to DL3, or
`punch-through tends to easily occur between adjacent ele(cid:173)
`ment regions, resulting in a problem that processing steps
`are rendered difficult.
`In this respect, in the prior art, a proposal has been made
`with respect an EEPROM in which the interval distance
`between adjacent data line contacts CDI to CD3 can be
`widened by arranging the lay-out.
`For example, FIGS. 6 to 10 show another example of a
`conventional NAND type EEPROM. FIG. 6 is a plan view
`45 thereof. FIG. 7 is a cross-section cut along a line VII-VII
`in FIG. 6. FIG. 8 is a cross-section cut along a line
`VIII-VIII in FIG. 6. FIG. 9 is a cross-section cut along a
`line IX-IX in FIG. 6. FIG. 10 shows an equivalent circuit
`of FIG. 6.
`Adata line contact CDI is provided at a first memory cell
`row constructed by connecting a plurality of memory cell
`transistors 11 formed on a semiconductor 1. A data line
`contact CD2 is provided at a second memory cell row
`constructed by connecting a plurality of memory cell tran-
`55 sistors 11, formed on the semiconductor substrate 1, so as to
`be adjacent to the first memory cell row with an element
`separation region 2 inserted therebetween. The data line
`contacts CDI and CD2 are arranged to be shifted from each
`other.
`In the figures, the portions corresponding to portions
`shown in FIGS. 1 to 5 are denoted by same references and
`explanation thereof will be omitted here from.
`However, in this method, the distance between gate lines
`SGDI and SGD2 forming a transistor 12 is widened, so that
`65 the periodicity of the array of control gate lines CGl to CG4
`and gate line SGDI to SGD2 which form memory cell
`transistors 11 is disturbed in the vicinity of the data line
`
`The present invention relates to a non-volatile semicon(cid:173)
`ductor memory device having a MOS structure using a
`memory cell having a charge storage layer such as a floating
`gate or the like, and a control gate, and particularly, to a
`semiconductor memory device in which the distance
`between adjacent data line contacts each other is widened so
`that error operations can be avoided.
`Conventionally, in the field of non-volatile semiconductor
`memory devices, an electrically re-writable non-volatile
`semiconductor memory device is known as an EEPROM.
`This kind of EEPROM has a memory cell array in which
`memory cell transistors are arranged at cross points where
`line wires and row wires cross each other. A memory cell 20
`transistor normally has a MOS structure in which a floating
`gate and a control gate are layered on each other.
`Among EEPROMs, a NAND type EEPROM is known as
`a method suitable for high integration.
`FIG. 1 is a plan view showing an example of a conven(cid:173)
`tional NAND type EEPROM. FIG. 2 is a cross-section cut
`along a line II-II in FIG. 1. FIG. 3 is a cross-section cut
`along a line III-III in FIG. 1. FIG. 4 is a cross-section cut
`along a line IV-IV in FIG. 1. In addition, FIG. 5 shows an
`equivalent circuit of FIG. 1.
`In an NAND type EEPROM, a plurality of memory cell
`transistors 11 are connected in series to form a unit NAND
`cell. As shown in FIGS. 1 to 5, the drain side of a NAND cell
`is connected to data lines DL1, DL2, and DL3 through a
`transistor 12, while the source side of the NAND cell is 35
`connected to a source line SL through a transistor 12.
`Normally, data line DL1, DL2, and DL3 are made of a
`semiconductor including metal or impurities at a high
`density, on an inter-layer insulating film 51 covering a
`memory cell transistor 11, and are connected to the transistor 40
`12 in the drain side of the NAND cell.
`By thus providing a plurality of NAND cells, a memory
`cell array is constructed. In the figures, reference 1 denotes
`a semiconductor substrate, and reference 2 denotes an ele(cid:173)
`ment separation region. Reference 3 denotes a gate insulat(cid:173)
`ing film, and reference 4 denotes a source-drain diffusion
`layer. Reference 5 denotes a floating gate. Reference 6
`denotes a selection gate. Reference 7 denotes a control gate.
`References SGDI and SGD2 denote gate lines in the drain
`side. SGSI and SGS2 denote gate lines in the source side. 50
`References CGl to CG8 denote control gate lines.
`Next, steps of forming data line contacts CD1, CD2, and
`CD3 and data lines DLl, DL2, and DL3 will be briefly
`explained below.
`A memory cell transistor 11 is formed on a semiconductor
`substrate 1, and thereafter, the entire substrate is covered
`with an inter-layer insulating film 51. Thereafter, data line
`contacts are patterned by a photolithography method and the
`inter-layer insulating film 51 is etched to open contacts.
`Thereafter, a material to form data lines, e.g., aluminum
`is deposited and patterning is carried out by a photolithog(cid:173)
`raphy method. Data line contacts CD1, CD2, and CD3 and
`data lines DL1, DL2, and DL3 are formed in the steps
`described above.
`However, in accordance with high integration of
`elements, the distance between adjacent NAND cells is
`
`60
`
`Page 33 of 44
`
`

`

`6,157,056
`
`3
`contacts CDI to CD3, resulting in a possibility of affecting
`manufacturing steps. For example, the flatness of an inter(cid:173)
`layer insulating film 51 is degraded in the vicinity of the data
`line contacts CDI to CD3. Since the film thickness of an
`inter-layer insulating film 51 is reduced so that the surface
`of the inter-layer insulating film 51 is recessed, it is difficult
`to perform patterning with use of a photolithography
`method, resulting in a possibility of causing short-circuiting
`of wires between the data lines DLI to DL3 or between data
`lines DLl to DL3 and gate lines SGDI to SGD2.
`In addition, since the interval distance between the gate
`lines SGDI and SGD2 forming transistors 12 is widened, it
`is difficult to selectively etch only the inter-layer insulating
`film 51 so that data line contacts CDI to CD3 are formed in
`a self-alignment manner.
`Thus, in conventional data line contacts provided at a
`plurality of memory cell rows disposed to be adjacent to
`each other with an element separation region inserted
`therebetween, the interval distance between adjacent rows is
`so small that short-circuiting of wires easily occurs in
`accordance with high integration of elements, and a problem
`that the flatness of an inter-layer insulating film is degraded
`occurs if the interval distance is widened.
`
`BRIEF SUMMARY OF THE INVENTION
`
`In view of the situation as described above, the present
`invention has an object of providing a semiconductor
`memory device in which the distance between adjacent data
`line contacts can be widened and short-circuiting of wires of
`data line contacts and data lines or punch-through in element
`regions which may cause an error operation can be pre(cid:173)
`vented.
`In order to achieve the above object, according to the
`present invention, there is provided a semiconductor
`memory device comprising: a memory cell array including
`a plurality of memory cell rows and a plurality of transistors
`in which a first memory cell row having a plurality of
`memory cell transistors connected and formed on a semi(cid:173)
`conductor substrate; a first transistor connected to either a
`drain side or a source side of the first memory cell row; a
`second memory cell row having a plurality of memory cell
`transistors connected and formed on the semiconductor
`substrate; a second transistor connected to either a drain side
`or a source side of the second memory cell row; a third
`memory cell row having a plurality of memory cell transis(cid:173)
`tors connected and formed on the semiconductor substrate;
`a third transistor connected to either a drain side or a source
`side of the third memory cell row; a fourth memory cell row
`having a plurality of memory cell transistors connected and 50
`formed on the semiconductor substrate; and a fourth tran(cid:173)
`sistor connected to either a drain side or a source side of the
`third memory cell row, the first and second transistors being
`connected to either a data line or a source line through a first
`contact common to both the first and second transistors, 55
`forming a first memory cell group, the third and fourth
`transistors being connected to either a data line or a source
`line through a second contact common to both the third and
`fourth transistors, forming a second memory cell group, gate
`electrodes of the first and third transistors are connected in 60
`common to a first gate line, gate electrodes of the second and
`fourth transistors being connected in common to a second
`gate line, the first and second memory cell groups being
`separated from each other such that an element separation
`region is inserted between the first and second memory cell 65
`groups, and the first and second gate lines are provided such
`that the gate electrodes of the transistors of every pairs
`
`4
`between which the element separation region is inserted are
`connected with each other; and a third gate line provided at
`a space between the first and second gate lines, the first
`contact being formed between the first and third gate lines,
`5 and the second contact being formed between the second
`and third gate lines.
`In addition, according to the present invention, there is
`provided a semiconductor memory device comprising a
`memory cell array including a plurality of memory cell rows
`10 and a plurality of transistors in which a first memory cell row
`having of a plurality of memory cell transistors connected
`and formed on a semiconductor substrate; a first transistor
`connected to either a drain side or a source side of the first
`memory cell row; a second memory cell row having a
`15 plurality of memory cell transistors connected and formed
`on the semiconductor substrate; a second transistor con(cid:173)
`nected to either a drain side or a source side of the second
`memory cell row; a third memory cell row having a plurality
`of memory cell transistors connected and formed on the
`20 semiconductor substrate; a third transistor connected to
`either a drain side or a source side of the third memory cell
`row; a fourth memory cell row having a plurality of memory
`cell transistors connected and formed on the semiconductor
`substrate; and a fourth transistor connected to either a drain
`25 side or a source side of the third memory cell row, the
`memory cell rows and the transistors constituting a memory
`cell array in which the first and second transistors are
`connected to either a data line or a source line through a first
`contact common to both the first and second transistors,
`30 forming a first memory cell group, the third and fourth
`transistors being connected to either a data line or a source
`line through a second contact common to both the third and
`fourth transistors, forming a second memory cell group, gate
`electrodes of the first and third transistors being connected
`35 in common to a first gate line, gate electrodes of the second
`and fourth transistors being connected in common to a
`second gate line, the first and second memory cell groups
`being separated from each other such that an element
`separation region is inserted between the first and second
`40 memory cell groups, and the first and second gate lines are
`provided such that the gate electrodes of the transistors of
`every pairs between which the element separation region is
`inserted are connected with each other; a first spacing
`element connected between the first contact and the second
`45 transistor; and a second spacing element connected between
`the second contact and the third transistor.
`Further, according to the present invention, there is pro(cid:173)
`vided a semiconductor memory device comprising: a first
`memory cell row having a plurality of memory cell transis(cid:173)
`tors connected and formed on a semiconductor substrate; a
`first transistor connected to either a drain side or a source
`side of the first memory cell row; a second memory cell row
`having a plurality of memory cell transistors connected and
`formed on the semiconductor substrate; a second transi