Ill 11111 11111R! 141.11990911111 111113 11111 liii
`IIIII!1)111191,1f191)111111111111111111111111111
`111111111111111111111111111
`11111 11111111
`[11] Patent Number: 5,479,639
`5,479,639
`[11] Patent Number:
`[45] Date of Patent: Dec. 26, 1995
`[45] Date of Patent:
`Dec. 26, 1995
`
`United States Patent [19]
`United States Patent [19]
`Ewertz et al.
`Ewertz et al.
`
`[54] COMPUTER SYSTEM WITH A PAGED
`[54] COMPUTER SYSTEM WITH A PAGED
`NON-VOLATILE MEMORY
`NON-VOLATILE MEMORY
`
`[75] Inventors: James H. Ewertz; Orville H.
`Inventors: James H. Ewertz; Orville H.
`[75]
`Christeson, both of Portland; Douglas
`Christeson, both of Portland; Douglas
`L. Gabel, Aloha; Sean T. Murphy,
`L. Gabel, Aloha; Sean T. Murphy,
`Portland, all of Oreg.
`Portland, all of Oreg.
`
`[73] Assignee: Intel Corporation, Santa Clara, Calif.
`[73] Assignee: Intel Corporation, Santa Clara, Calif.
`
`[21] Appi. No.: 279,692
`[21] Appl. No.: 279,692
`[22] Filed: Aug. 26, 1994
`[22] Filed:
`Aug. 26, 1994
`
`Related U.S. Application Data
`Related U.S. Application Data
`
`OTHER PUBLICATIONS
`OTHER PUBLICATIONS
`Markus A. Levy, "Designing with Flash Memory", Circuit
`Markus A. Levy, "Designing with Flash Memory", Circuit
`Cellar Ink, Dec. 1990, pp. 50-58.
`Cellar Ink, Dec. 1990, pp. 50-58.
`Jerry Jex, "Flash Memory BIOS For PC and Notebook
`Jerry Jex, "Flash Memory BIOS For PC and Notebook
`Computers", IEEE, 1990, pp. 692-695.
`Computers", IEEE, 1990, pp. 692-695.
`Waite, et al., "Soul of CP/M", Howard W Sams and Co.,
`Waite, et al., "Soul of CP/M", Howard W Sams and Co.,
`1983, pp. 2-7, 177-182 and 279-322.
`1983, pp. 2-7, 177-182 and 279-322.
`(List continued on next page.)
`(List continued on next page.)
`Primary Examiner—Tod R. Swann
`Primary Examiner—Tod R. Swann
`Assistant Examiner—Hiep T. Nguyen
`Assistant Examiner—Hiep T. Nguyen
`Attorney, Agent, or Finn—Blakely, Sokoloff, Taylor & Zaf-
`Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor & Zaf-
`man
`man
`[57] ABSTRACT
`ABSTRACT
`[57]
`A computer system wherein a paging technique is used to
`A computer system wherein a paging technique is used to
`expand the useable non-volatile memory capacity beyond a
`expand the useable non-volatile memory capacity beyond a
`fixed address space limitation. The computer system of the
`fixed address space limitation. The computer system of the
`preferred embodiment includes a flash memory component
`preferred embodiment includes a flash memory component
`for storing non-volatile code and data including a system
`for storing non-volatile code and data including a system
`BIOS in the upper 128K of memory. The useful BIOS
`BIOS in the upper 128K of memory. The useful BIOS
`memory space is effectively increased while maintaining the
`memory space is effectively increased while maintaining the
`address boundary of the upper 128K region. The address
`address boundary of the upper 128K region. The address
`space of the non-volatile memory device is logically sepa-
`space of the non-volatile memory device is logically sepa-
`rated into distinct pages of memory (Pages 1-4). Using the
`rated into distinct pages of memory (Pages 1-4). Using the
`apparatus and techniques of the present invention, Page 1,
`apparatus and techniques of the present invention, Page 1,
`Page 3 and Page 4 may be individually swapped into the
`Page 3 and Page 4 may be individually swapped into the
`address space originally occupied by Page 1 (the swappable
`address space originally occupied by Page 1 (the swappable
`page area). In the preferred embodiment, Page 2 is held
`page area). In the preferred embodiment, Page 2 is held
`static and thus is not used as a swap area. Each of the
`static and thus is not used as a swap area. Each of the
`swappable pages, Page 1, Page 3, and Page 4, contain
`swappable pages, Page 1, Page 3, and Page 4, contain
`processing logic called swapping logic used during the
`processing logic called swapping logic used during the
`swapping or paging operation. The swapping logic operates
`swapping or paging operation. The swapping logic operates
`in conjunction with paging hardware to effect the swapping
`in conjunction with paging hardware to effect the swapping
`of pages into the swappable page area. The high order
`of pages into the swappable page area. The high order
`processor address lines are input by a page decoder. The
`processor address lines are input by a page decoder. The
`page decoder is used to modify the address actually pre-
`page decoder is used to modify the address actually pre-
`sented to the non-volatile memory device. A page register
`sented to the non-volatile memory device. A page register
`provides a means by which the processor may select a page
`provides a means by which the processor may select a page
`in non-volatile memory. In an alternative embodiment of the
`in non-volatile memory. In an alternative embodiment of the
`present invention, several different forms of configuration or
`present invention, several different forms of configuration or
`identification information may be stored in a page of non-
`identification information may be stored in a page of non-
`volatile memory.
`volatile memory.
`
`14 Claims, 11 Drawing Sheets
`14 Claims, 11 Drawing Sheets
`
`[63] Continuation of Ser. No. 137,376, Oct. 14, 1993, Pat. No.
`[63] Continuation of Ser. No. 137,376, Oct. 14, 1993, Pat. No.
`5,371,876, which is a continuation of Ser. No. 698,318, May
`5,371,876, which is a continuation of Ser. No. 698,318, May
`10, 1991, abandoned.
`10, 1991, abandoned.
`[51] Int. C1.6
`[51] Int. C1.6
`[52] U.S. Cl.
`[52] U.S. Cl.
`
`GO6F 12/02
`GO6F 12/02
`395/430; 395/479; 395/413;
`395/430; 395/479; 395/413;
`395/419; 364/DIG. 1
`395/419; 364/DIG. 1
` 364/200 MS File,
`364/200 MS File,
`
`364/900 MS File; 395/400, 425
`364/900 MS File; 395/400, 425
`
`[58] Field of Search
`[58] Field of Search
`
`[56]
`[56]
`
`References Cited
`References Cited
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`U.S. PATENT DOCUMENTS
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`4,153,937
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`5/1979 Poland
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`9/1981 Holtey et al 395/400
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`9/1981 Holtey et al.
`395/400
`4,290,104
`2/1983 Bradley et al. 395/400
`4,374,417
`2/1983 Bradley et al.
`4,374,417
`395/400
`4,441,155
`4/1984 Fletcher et al. 395/400
`4,441,155 4/1984 Fletcher et al.
`395/400
`4,443,847
`4/1984 Bradley et al. 395/425
`4,443,847
`395/425
`4/1984 Bradley et al.
`4,608,632
`8/1986 Kummer 395/425
`4,608,632
`8/1986 Kummer
`395/425
`4,763,333
`8/1988 Byrd 371/66
`4,763,333
`8/1988 Byrd
`371/66
`1/1989 Goss et al 395/700
`4,799,145
`4,799,145
`1/1989 Goss et al.
`395/700
`4,831,522
`5/1989 Henderson et al. 395/425
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`5/1989 Henderson et al.
`395/425
`4,862,349
`4/1989 Foreman et al. 395/700
`4,862,349
`4/1989 Foreman et al.
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`5,034,915
`7/1991 Styrna et al. 395/275
`7/1991 Styrna et al.
`5,034,915
`395/275
`5,053,990 10/1991 Kreifels et al. 395/425
`5,053,990 10/1991 Kreifels et al.
`395/425
`5,117,492
`5/1992 Nash 395/400
`5,117,492
`5/1992 Nash
`395/400
`5,126,808
`6/1992 Montalvo et al. 357/23.5
`5,126,808
`6/1992 Montalvo et al.
`357/23.5
`5,134,580
`7/1992 Bertram et al. 395/650
`5,134,580
`7/1992 Bertram et al.
`395/650
`8/1992 Bealkowski et al. 395/700
`5,136,713
`8/1992 Bealkowski et al.
`5,136,713
`395/700
`5,142,680
`8/1992 Ottman et al 395/700
`5,142,680
`8/1992 Ottman et al.
`395/700
`5,210,875
`5/1993 Bealkowski et al. 395/700
`5,210,875
`395/700
`5/1993 Bealkowski et al.
`
`POO'
`
`tOCAC
`3.4.11Te0 =AC
`
`316
`Ile
`
`106
`
`xe
`
`PAM
`1011.
`Wyse
`MOOVUM »OS ej3
`PLOW. MOM
`&ea
`Mlaelee.rs,/e owe.d hoe
`meet treelicuix,
`owe le.e.liceliel
`te«01
`Untie
`P.6051b letlatli
`111301.111 Mt MIR Me
`vwla
`ILLILAVEDIgILSYSTIM
`p1.1L--- Vv
`
`t
`
`Mt:COMO
`en11:01.1t.
`
`LOGIC
`
`SWAM. LC.
`ftlAMeGLOIIC
`
`32
`
`r2,4
`
`Page 1
`
`IPR2021-01338
`ANCORA EX2015
`
`

`

`5,479,639
`5,479,639
`Page 2
`Page 2
`
`OTHER PUBLICATIONS
`OTHER PUBLICATIONS
`Waite et al., "CP/M Bible", 1983, pp. 5-22 and 100.
`Waite et al., "CP/M Bible", 1983, pp. 5-22 and 100.
`Brett Glass, "The IBM PC BIOS", Byte, Apr. 1989, pp.
`Brett Glass, "The IBM PC BIOS", Byte, Apr. 1989, pp.
`303-310.
`303-310.
`Gus Venditto, "Pipeline", PC Magazine vol. 9, No. 3, Feb.
`Gus Venditto, "Pipeline", PC Magazine vol. 9, No. 3, Feb.
`1990, pp. 1-3.
`1990, pp. 1-3.
`Bill Machrone, "Bill Machrone", PC Magazine, vol. 9, No.
`Bill Machrone, "Bill Machrone", PC Magazine, vol. 9, No.
`
`7, Apr. 1990, pp. 1-2.
`7, Apr. 1990, pp. 1-2.
`Gus Venditto, "Intel's flash memory poised to give laptops
`Gus Venditto, "Intel's flash memory poised to give laptops
`their next great leap", PC Magazine vol. 9, No. 14, Aug.
`their next great leap", PC Magazine vol. 9, No. 14, Aug.
`1990, pp. 1-3.
`1990, pp. 1-3.
`John H. Wharton, "FLASH! memory technology marches
`John H. Wharton, "FLASH! memory technology marches
`on", Microprocessor Report, Aug. 1990, pp. 1-4.
`on", Microprocessor Report, Aug. 1990, pp. 1-4.
`
`Page 2
`
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`

`Waled 'S'a
`
`S66I `9Z .3aU
`
`la JO I paqs
`
`100
`100
`Bus
`Bus
`
`106
`106
`
`Data Storage Device
`Data Storage Device
`
`I
`
`103
`103
`
`Memory
`Memory
`Flash
`Flash
`
`Figure 1
`Figure 1
`
`105
`105
`
`Display Device
`Display Device
`
`1
`I
`
`102
`102
`
`Random Access
`Random Access
`
`Memory
`Memory
`
`104
`104
`
`Input Device
`Input Device
`
`
` I
`
`101
`101
`
`Processor
`Processor
`
`Page 3
`
`IPR2021-01338
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`

`

`U.S. Patent Dec. 26, 1995
`U.S. Patent
`Dec. 26, 1995
`
`Sheet 2 of 11 5,479,639
`5,479,639
`Sheet 2 of 11
`
`FIGURE 2
`FIGURE 2
`
`256
`256
`
`11-.1-i-th
`11-1-1-1-11
`SWAPPING LOGIC
`SWAPPING LOGIC
`
`,........
`
`192
`192
`
`FOOD0h
`F0000h
`EFFFFh
`EFFFFh
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K)
`RESERVED FOR USER (8K)
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`RESERVED FOR SYSTEM (8K) 4
`
`
`
`VIDEO (32K) —
`VIDEO (32K)
`—
`
`128
`128
`
`E000011
`E0000h
`SWAPPING LOGIC —
`SWAPPING LOGIC
`—
`
`—
`
`SWAPPING LOGIC —
`SWAPPING LOGIC
`--•
`
`) PAGE 1
`PAGE 1
`(301)
`(301)
`
`PAGE 2
`PAGE 2
`(302)
`(302)
`
`)PAGE 3
`)PAGE 3
`(303)
`(303)
`
`315
`315
`
`316
`316
`
`306
`306
`
`307
`307
`
`308
`308
`
`309
`309
`
`310
`310
`
`311
`311
`
`312
`312
`
`320
`320
`
`321
`321
`
`) PAGE 4
`PAGE 4
`(304)
`(304)
`
`—.
`'-'
`....
`313
`313
`
`Page 4
`
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`

`

`ivalud 'S'11
`
`H Jo E WIN
`
`MEMORY
`MEMORY
`FLASH
`FLASH
`
`103
`103
`
`00000h - DI-H-Fh (64K)
`00000h - D1-1-1-Th (64K)
`E0000h - Ell-fq-h (64K)
`E0000h - El-t-teh (64K)
`OTHER ADDRESS RANGE (i.e. C0000h - C1-11-1-h)
`OTHER ADDRESS RANGE (i.e. C0000h - C1--H-Fh)
`OTHER ADDRESS RANGE (i.e. D0000h - DFH-q-h)
`OTHER ADDRESS RANGE (i.e. 13000011 - DEH-hh)
`E0000h - El-1H-ii (64K)
`E0000h - EI-11+11 (64K)
`F0000h -11-m+h (64K)
`F0000h -11-ri+h (64K)
`ADDRESS
`ADDRESS
`NON-VOLATILE MEMORY
`NON-VOLATILE MEMORY
`
`00000h - Dil-plii (64K)
`00000h - DI-i-i-i-h (64K)
`N/A
`N/A
`E0000h - El-H-01(64K)
`E0000h - E1-11-1.h (64K)
`N/A
`N/A
`F0000h - 111-11-11 (64K)
`F0000h - 1-11-11.11 (64K)
`4
`4
`F0000h -1.11-trli (64K)
`F0000h - 11-1.11.11 (64K)
`3
`3
`E000011 - Ell-tfh (64K)
`2 (STATIC) E0000h - EN-H-11(64K)
`2 (STATIC)
`F0000h -1-1-1-+Fh (64K)
`F0000h - 1.1-thi-b (64K)
`1
`1
`ADDRESS
`ADDRESS
`PROCESSOR
`PROCESSOR
`
`PAGE
`PAGE
`
`219
`219
`
`FIGURE 3B
`FIGURE 3B
`
`ADDRESS LINES
`ADDRESS LINES
`
`210
`210
`
`218
`218
`
`-7/
`4
`4
`
`PAGE DECODER
`z— PAGE DECODER
`
`217
`217
`
`J
`
`216
`216
`
`211
`211
`
`212
`212
`
`PAGE REGISTER
`PAGE REGISTER
`
`214
`214
`
`FIGURE 3A
`FIGURE 3A
`
`16
`16
`
`4
`
`215
`215
`
`PROCESSOR
`PROCESSOR
`
`101
`101
`
`Page 5
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`Sheet 4 of 11 5,479,639
`U.S. Patent Dec. 26, 1995
`5,479,639
`U.S. Patent
`Sheet 4 of 11
`Dec. 26, 1995
`FIGURE 4
`FIGURE 4
`
`C
`
`PAGE = NEW_PAGE
`101
`
`CT100
`START 100
`PAGE
` = NEW_PAGE
` 101
`V SWITCH_PAGE
` 102
`(D) 103
`
`V
`SWITCH_PAGE
`102
`
`C
`
`END
`103
`
`Page 6
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`U.S. Patent Dec. 26, 1995 Sheet 5 of 11 5,479,639
`5,479,639
`U.S. Patent
`Dec. 26, 1995
`Sheet 5 of 11
`
`FIGURE 5
`FIGURE 5
`
`START)
`START
`500
`(1
`
`SW_SHADOW_OFF
`501
`
`SW_CACHE_OFF
`502
`
`PAGE >
`MAX_PAGE
`503
`
`4
`NO - 506
`NO 506
`
`PAGE_REG = PAGE_REG
`PAGE_REG = PAGE_REG
`AND PAGE_REG_MASK
`AND PAGE_REG MASK
`OR PAGE
`OR PAGE
`507
`507
`
`PAGE_ENTRY_TABLE
`PAGE_ENTRY_TABLE
`(PAGE*2)
`(PAGE*2)
`508
`508
`
`JUMP TO NEW
`PAGE
`509
`
`YES - 504-b
`YES - 504
`
`PAGE = 1
`PAGE = 1
`505
`505
`
`Page 7
`
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`U.S. Patent Dec. 26, 1995 Sheet 6 of 11 5,479,639
`5,479,639
`U.S. Patent
`
`Dec. 26, 1995
`
`Sheet 6 of 11
`
`FIGURE 6
`FIGURE 6
`
`START
`600
`
`IF PAGE
`VALID
`601
`
`YES - 603
`YES - 603
`i v
`
`SW_SWADOW_ON
`SW_SWADOW_ON
`604
`604
`
`SW_CACHE_ON
`SW_CACHE_ON
`605
`605
`
`*
`
`TRUE_ENTRY_POINT
`606
`
`NO - 602
`NO - 602
`
`V
`
`PAGE = error page
`PAGE = error page
`605
`605
`
`SWITCH_PAGE
`SWITCH_PAGE
`
`Page 8
`
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`U.S. Patent Dec. 26, 1995 Sheet 7 of 11 5,479,639
`5,479,639
`U.S. Patent
`Dec. 26, 1995
`Sheet 7 of 11
`
`705
`705 I
`
`FIGURE 7a
`FIGURE 7a
`
`'......„,.....
`
`706
`706
`1
`
`1-1+1-1-11
`1-ttakth
`SWAPPING LOGIC
`SWAPPING LOGIC
` —
`
`11-ti-1-h
`11-1-i-h
`SWAPPING LOGIC
`SWAPPING LOGIC
` —
`
`POST Program
`POST Program
`(701)
`(701)
`
`Page 1
`
`Swappable Page Area
`Swappable Page Area
`(700)
`(700)
`
`EFFFFh
`EFFFFh
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K) I
`1
`RESERVED FOR USER (8K)
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`.
`
`age 2
`age 2
`
`F0000h
`F0000h
`EFFFFh
`EFFFFh
`RECOVERY BIOS (16K)
`RECOVERY BIOS (I6K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K)
`RESERVED FOR USER (8K)
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`VIDEO (32K)
`VIDEO (32K)
`
`VIDEO (32K)
`VIDEO (32K)
`
`E0000h
`E0000h
`SWAPPING LOGIC
`SWAPPING LOGIC
` _
`
`E0000h
`E0000h
`
`Setup
`Setup
`Program
`Program
`(703)
`(703)
`
`Page 3
`Page 3
`
`SWAPPING LOGIC
`SWAPPING LOGIC
` _
`
`L -
`
`Run-Time BIOS
`Run-Time BIOS
`(704)
`(704)
`
`Page 4
`Page 4
`
`I
`
`Page 9
`
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`U.S. Patent
`U.S. Patent
`
`Dec. 26, 1995 Sheet 8 of 11 5,479,639
`5,479,639
`Sheet 8 of 11
`Dec. 26, 1995
`
`705
`705
`
`FIGURE 7b
`FIGURE 7b
`
`706
`706
`
`1.1-.1-1-1-11
`H-H-i-n
`SWAPPING LOGIC _
`SWAPPING LOGIC
`
`H-Evrti
`1'1-1-1-1-h
`SWAPPING LOGIC _
`SWAPPING LOGIC
`
`POST Program
`POST Program
`(701)
`(70] )
`
`Page 1
`Page 1
`
`Swappable Page Area
`Swappable Page Area
`(700)
`(700)
`
`EFH-Fh
`El-i-H-ti
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K)
`RESERVED FOR USER (8K)
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`x
`
`age 2
`agc 2
`
`F0000h
`F0000h
`EFFFFh
`EFF'FFh
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K)
`RESERVED FOR USER (8K)
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`VIDEO (32K)
`VIDEO (32K)
`
`VIDEO (32K)
`VIDEO (32K)
`
`E0000h
`E0000h
`SWAPPING LOGIC
`SWAPPING LOGIC
` _
`
`E0000h
`E0000h
`
`Setup
`Setup
`Program
`Program
`(703)
`(703)
`
`Page 3
`Page 3
`
`SWAPPING LOGIC
`SWAPPING LOGIC
` _
`
`= -
`3
`
`Run-Time BIOS
`Run-Time BIOS
`(704)
`(704)
`
`Page 4
`Page 4
`
`Page 10
`
`IPR2021-01338
`ANCORA EX2015
`
`

`

`U.S. Patent Dec. 26, 1995 Sheet 9 of 11 5,479,639
`5,479,639
`U.S. Patent
`
`Sheet 9 of 11
`
`Dec. 26, 1995
`
`705
`705
`
`FIGURE 7c
`FIGURE 7c
`r
`r•—
`•
`•
`
`OF
`
`706
`706
`
`I-I-H-1-h
`H-1-1-1-b
`SWAPPING LOGIC _
`SWAPPING LOGIC
`
`I-HI-Ph
`1-1-1-±-1-h
`SWAPPING LOGIC _
`SWAPPING LOGIC
`
`POST Program
`POST Program
`(701)
`(701)
`
`Page 1
`Page 1
`
`Swappable Page Area
`Swappable Page Area
`(700)
`(700)
`
`F0000h
`F0000h
`EFFFFh
`EF1-Fi-b
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K)
`RESERVED FOR USER (8K)
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`VIDEO (32K)
`VIDEO (32K)
`
`E0000h
`E0000h
`
`z
`
`E1-1-,1-i-th
`El-i-ki-b
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K) I
`RESERVED FOR USER (8K)
`
`1 age 2:
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`/
`
`I
`I
`
`I
`/
`I I
`I
`1
`I
`
`:
`
`a
`
`VIDEO (32K)
`VIDEO (32K)
`
`E0000h .
`E0000h
`SWAPPING LOGIC
`SWAPPING LOGIC
` —
`
`Setup
`Setup
`Program
`Program
`(703)
`(703)
`
`SWAPPING LOGIC
`SWAPPING LOGIC
` _
`
`Pagep
`
`r
`i
`
`=
`
`Run-Time BIOS
`Run-Time BIOS
`(704)
`(704)
`
`Page 4
`Page 4
`
`Page 11
`
`IPR2021-01338
`ANCORA EX2015
`
`

`

`U.S. Patent Dec. 26, 1995 Sheet 10 of 11 5,479,639
`5,479,639
`U.S. Patent
`Sheet 10 of 11
`
`Dec. 26, 1995
`
`...........
`
`.....
`
`705
`705
`l
`
`FIGURE 7d
`FIGURE 7d
` ,......,
`.----
`
`706
`706
`L
`
` ,
`
`i...
`
`,.,
`.'............,..„
`
`1-.1-t-1-1411
`1.1-i-i-i:h
`SWAPPING LOGIC
`SWAPPING LOGIC
` —
`
`1-1-1-1-Fh
`1+11-1,b
`SWAPPING LOGIC .._
`SWAPPING LOGIC
`
`POST Program
`POST Program
`(701)
`(701)
`
`Page 1
`age 1
`
`Swappable Page Area
`Swappable Page Area
`(700)
`(700)
`
`F0000h
`F0000h
`EI-H-..t.n
`EI-1-},Fh
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K)
`RESERVED FOR USER (8K)
`EA000h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`VIDEO (32K)
`VIDEO (32K)
`
`E0000h
`E0000h
`
`Ell-Hrh
`E1-41.1-h
`RECOVERY BIOS (16K)
`RECOVERY BIOS (16K)
`(Electronically protected from
`(Electronically protected from
`erasure or modification)
`erasure or modification)
`EC000h
`EC000h
`RESERVED FOR USER (8K)
`RESERVED FOR USER (8K)
`EACO0h
`EA000h
`RESERVED FOR SYSTEM (8K)
`RESERVED FOR SYSTEM (8K)
`E8000h
`E8000h
`
`I
`F
`Page
`
`VIDEO (32K)
`VIDEO (32K)
`
`_ E0000h
`E0000h
`SWAPPING LOGIC
`SWAPPING LOGIC
` _
`
`.
`
`Setup
`Setup
`Program
`Program
`(703)
`(703)
`
`SWAPPING LOGIC
`SWAPPING LOGIC
` _
`
`==.
`
`Run-Time BIOS
`Run-Time BIOS
`(704)
`(704)
`
`Page:4
`
`Page 12
`
`IPR2021-01338
`ANCORA EX2015
`
`

`

`U.S. Patent Dec. 26, 1995
`U.S. Patent
`Dec. 26, 1995
`
`Sheet 11 of 11 5,479,639
`5,479,639
`Sheet 11 of 11
`
`FIGURE 8
`FIGURE 8
`
`( START )
`( START
`801
`801
`
`NiF
`COPY FLASH UPDATE ROUTINES
`COPY FLASH UPDATE ROUTINES
`TO RANDOM ACCESS MEMORY
`TO RANDOM ACCESS MEMORY
`802
`802
`
`ERASE
`ERASE
`FLASH
`FLASH
`BLOCK YES - 805
`YES - 805
`BLOCK
`804
`804
`
`SUBFUNCTION =02 OR 82H
`SUBFUNCTION = 02 OR 82H
`CLEAR NON-VOLATILE
`CLEAR NON-VOLATILE
`MEMORY?
`MEMORY?
`803
`803
`
`NO - 806
`NO - 806
`
`SU13FUNCTION =03 OR 8311
`SUBFUNCTION = 03 OR 83H
`WRITE NON-VOLATILE
`WRITE NON-VOLATILE
`MEMORY?
`MEMORY?
`807
`807
`
`YES 809
`YES - 809
`iv
`WRITE SLOT INFORMATION IN FLASH
`WRITE SLOT INFORMATION IN FLASH
`NON-VOLATILE MEMORY
`NON-VOLATILE MEMORY
`808
`808
`
`NO 813
`NO 813
`
`V
`UPDATE FLASH NON-VOLATILE
`UPDATE FLASH NON-VOLATILE
`BOOKKEEPING SECTION
`BOOKKEEPING SECTION
`810
`810
`.4
`4
`wir
`V
`RELEASE FLASH UPDATE ROUTINE
`RELEASE FLASH UPDATE ROUTINE
`RANDOM ACCESS MEMORY
`RANDOM ACCESS MEMORY
`811
`811
`
`( CONTINUE NORMAL )
`CONTINUE NORMAL
`PROCESSING
`PROCESSING
`812
`812
`
`Page 13
`
`IPR2021-01338
`ANCORA EX2015
`
`

`

`1
`1
`COMPUTER SYSTEM WITH A PAGED
`COMPUTER SYSTEM WITH A PAGED
`NON-VOLATILE MEMORY
`NON-VOLATILE MEMORY
`
`5,479,639
`5,479,639
`
`This is a continuation of application Ser. No. 08/137,376,
`This is a continuation of application Ser. No. 08/137,376,
`filed Oct. 14, 1993, now U.S. Pat. No. 5,371,876, which is 5
`filed Oct. 14, 1993, now U.S. Pat. No. 5,371,876, which is
`5
`a continuation of Ser. No. 07/698,318, filed May 19, 1991,
`a continuation of Ser. No. 07/698,318, filed May 19, 1991,
`abandoned.
`abandoned.
`
`FIELD OF THE INVENTION
`FIELD OF THE INVENTION
`The present invention relates to the field of computer
`The present invention relates to the field of computer
`systems. Specifically, the present invention relates to the
`systems. Specifically, the present invention relates to the
`field of computer system architectures incorporating a non-
`field of computer system architectures incorporating a non-
`volatile form of basic operating system processing logic.
`volatile form of basic operating system processing logic.
`
`2
`2
`contain processing logic for initializing and controlling
`contain processing logic for initializing and controlling
`many of the hardware systems and resources of the com-
`many of the hardware systems and resources of the com-
`puter system. With the increased functionality of modem
`puter system. With the increased functionality of modern
`computer systems, the complexity of hardware systems and
`computer systems, the complexity of hardware systems and
`resources increases as does the quantity of BIOS code
`resources increases as does the quantity of BIOS code
`required to support them. Also, because of new technologies
`required to support them. Also, because of new technologies
`and capabilities such as Extended Industry Standard Archi-
`and capabilities such as Extended Industry Standard Archi-
`tecture (EISA) systems, flash memory and multi-language
`tecture (EISA) systems, flash memory and multi-language
`support for international operation of a computer system, it
`support for international operation of a computer system, it
`is becoming increasingly unfeasible to fit all desired BIOS
`10
`10 is becoming increasingly unfeasible to fit all desired BIOS
`features within the 128K boundary of the IBM PC AT
`features within the 128K boundary of the IBM PC AT
`architecture. Other varieties of computer systems typically
`architecture. Other varieties of computer systems typically
`have an established limit for the size of their BIOS. Even
`have an established limit for the size of their BIOS. Even
`though the need for expanding the BIOS boundary is grow-
`though the need for expanding the BIOS boundary is grow-
`ing, the boundary cannot be arbitrarily modified without
`15
`15 ing, the boundary cannot be arbitrarily modified without
`losing compatibility with established standards.
`losing compatibility with established standards.
`Thus, a means for expanding the useable BIOS memory
`Thus, a means for expanding the useable BIOS memory
`space without violating established BIOS address boundary
`space without violating established BIOS address boundary
`standards is needed.
`standards is needed.
`
`20
`20
`
`BACKGROUND OF THE INVENTION
`BACKGROUND OF THE INVENTION
`Many prior art computer systems are typically configured
`Many prior art computer systems are typically configured
`at a minimum with a processor, a random access memory
`at a minimum with a processor, a random access memory
`device, and a read only memory device. Some systems, such
`device, and a read only memory device. Some systems, such
`as a variety of calculators, may operate with only a processor
`as a variety of calculators, may operate with only a processor
`and a read only memory device. Read only memory devices
`and a read only memory device. Read only memory devices
`(ROM) provide a non-volatile form of memory that is not
`(ROM) provide a non-volatile form of memory that is not
`destroyed when power is removed from the computer sys-
`destroyed when power is removed from the computer sys-
`tem.
`tem.
`Prior an computer systems are typically bootstrapped (i.e.
`Prior an computer systems are typically bootstrapped (i.e.
`power up initialized) using the processing logic (i.e. firm-
`power up initialized) using the processing logic (i.e. firm-
`ware) stored within the read only memory device internal to
`ware) stored within the read only memory device internal to
`the computer system. Since the read only memory device is
`the computer system. Since the read only memory device is
`non-volatile, the firmware within ROM is guaranteed to
`non-volatile, the firmware within ROM is guaranteed to
`contain valid data or instructions; thus, the prior an computer
`contain valid data or instructions; thus, the prior an computer
`system can be reliably bootstrapped using firmware within
`system can be reliably bootstrapped using firmware within
`ROM. Many computer systems have successfully used this
`ROM. Many computer systems have successfully used this
`technique. One such system is the IBM Personal Computer
`technique. One such system is the IBM Personal Computer
`(PC) developed by the IBM Corporation of Armonk, N.Y.
`(PC) developed by the IBM Corporation of Armonk, N.Y.
`Prior an versions of the IBM PC use read only memory
`Prior an versions of the IBM PC use read only memory
`devices for storage of firmware or a basic input/output
`devices for storage of firmware or a basic input/output
`system (BIOS) software program. The BIOS is an operating
`system (BIOS) software program. The BIOS is an operating
`system that provides the lowest level of software control
`system that provides the lowest level of software control
`over the hardware and resources of the computer system.
`over the hardware and resources of the computer system.
`ROM storage may also be used for non-volatile retention of
`ROM storage may also be used for non-volatile retention of
`network configuration data or application specific data.
`network configuration data or application specific data.
`ROM devices in the prior art include basic read only
`ROM devices in the prior art include basic read only
`memory devices (ROM), programmable read only memory
`memory devices (ROM), programmable read only memory
`devices (PROM), and erasable programmable read only
`devices (PROM), and erasable programmable read only
`memory devices (EPROM). Battery-backed random access
`memory devices (EPROM). Battery-backed random access
`memory devices such as CMOS RAM devices may also be
`memory devices such as CMOS RAM devices may also be
`used for non-volatile retention of network configuration data
`used for non-volatile retention of network configuration data
`or application specific data in a computer system.
`or application specific data in a computer system.
`Although ROM-based computer systems have been very
`50
`Although ROM-based computer systems have been very 50
`successful in the prior art, a number of problems exist with
`successful in the prior art, a number of problems exist with
`the use of these devices in a computer system. Most com-
`the use of these devices in a computer system. Most com-
`puter systems have a finite address space in which each of
`puter systems have a finite address space in which each of
`the computer system resources must operate. These
`the computer system resources must operate. These
`resources include ROM, random access memory (RAM),
`55
`resources include ROM, random access memory (RAM), 55
`input/output devices, and possibly other processors. ROM
`input/output devices, and possibly other processors. ROM
`devices with a BIOS contained therein are typically con-
`devices with a BIOS contained therein are typically con-
`strained to a specific address range within the addsess space
`strained to a specific address range within the addsess space
`available. In order to maintain compatibility with a particu-
`available. In order to maintain compatibility with a particu-
`lar computer architecture, designers and developers in the
`60
`lar computer architecture, designers and developers in the 60
`computer industry create products in reliance on a particular
`computer industry create products in reliance on a particular
`ROM address standard. For example, the IBM PC AT
`ROM address standard. For example, the IBM PC AT
`architecture mandates that the ROM BIOS and other firm-
`architecture mandates that the ROM BIOS and other firm-
`ware based applications are limited to a 128K address space
`ware based applications are limited to a 128K address space
`at the top of the first megabyte of memory. With this
`• 65
`at the top of the first megabyte of memory. With this 65
`architecture, however, the ROM BIOS cannot exceed 128K
`architecture, however, the ROM BIOS cannot exceed 128K
`of ROM space. Within this ROM space, the BIOS must
`of ROM space. Within this ROM space, the BIOS must
`
`SUMMARY OF THE INVENTION
`SUMMARY OF THE INVENTION
`The present invention is a computer system wherein a
`The present invention is a computer system wherein a
`paging technique is used to expand the useable non-volatile
`25 paging technique is used to expand the useable non-volatile
`25
`memory capacity beyond a fixed address space limitation.
`memory capacity beyond a fixed address space limitation.
`The computer system of the preferred embodiment com-
`The computer system of the preferred embodiment com-
`prises a bus for communicating information, a processor
`prises a bus for communicating information, a processor
`coupled with the bus for processing information, a random
`coupled with the bus for processing information, a random
`access memory device coupled with the bus for storing
`30 access memory device coupled with the bus for storing
`30
`information and instructions for the processor, an input
`information and instructions for the processor, an input
`device such as an alpha numeric input device or a cursor
`device such as an alpha numeric input device or a cursor
`control device coupled to the bus for communicating infor-
`control device coupled to the bus for communicating infor-
`mation and command selections to the processor, a display
`mation and command selections to the processor, a display
`device coupled to the bus for displaying information to a
`35 device coupled to the bus for displaying information to a
`35
`computer user, and a data storage device such as a magnetic
`computer user, and a data storage device such as a magnetic
`disk and disk drive coupled with the bus for storing infor-
`disk and disk drive coupled with the bus for storing infor-
`mation and instructions. In addition, the computer system of
`mation and instructions. In addition, the computer system of
`the preferred embodiment includes a flash memory compo-
`the preferred embodiment includes a flash memory compo-
`nent coupled to the bus for storing non-volatile code and
`40 nent coupled to the bus for storing non-volatile code and
`40
`data. Devices other than flash memory may be used for
`data. Devices other than flash memory may be used for
`storing nonvolatile code and data. Using the present inven-
`storing nonvolatile code and data. Using the present inven-
`tion, a paging technique expands the useable non-volatile
`tion, a paging technique expands the useable non-volatile
`memory capacity beyond a fixed address space limitation.
`memory capacity beyond a fixed address space limitation.
`The flash memory device used in the preferred embodi-
`The flash memory device used in the preferred embodi-
`ment contains four separately erasable/programmable non-
`ment contains four separately erasable/programmable non-
`symmetrical blocks of memory. One of these four blocks
`symmetrical blocks of memory. One of these four blocks
`may be electronically locked to prevent erasure or modifi-
`may be electronically locked to prevent erasure or modifi-
`cation of its contents once it is installed. This configuration
`cation of its contents once it is installed. This configuration
`allows the processing logic of the computer system to update
`allows the processing logic of the computer system to update
`or modify any selected block of memory without affecting
`or modify any selected block of memory without affecting
`the contents of other blocks. One memory block contains a
`the contents of other blocks. One memory block contains a
`normal BIOS. The BIOS comprises processing logic instruc-
`normal BIOS. The BIOS comprises processing logic instruc-
`tions that are executed by the processor.
`tions that are executed by the processor.
`In the preferred embodiment, the BIOS is constrained to
`In the preferred embodiment, the BIOS is constrained to
`the upper 128K of the first Mbyte of the addressable memory
`the upper 128K of the first Mbyte of the addressable memory
`space in the computer system. Because of computer system
`space in the computer sy