UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`LG Electronics, Inc. and LG Electronics U.S.A., Inc.,
`
`Petitioners,
`
`Case No. IPR2021-00581
`
`Patent No. 6,411,941 B1
`
`DECLARATION OF SHAHIN NAZARIAN, PH.D.,
`UNDER 37 C.F.R. § 1.68 IN SUPPORT OF PETITION
`FOR INTER PARTES REVIEW
`
`1
`
`Ex. 1015
`LG Electronics v. Ancora / Page 1 of 17
`
`

`

`I, Shahin Nazarian, Ph.D., do hereby declare as follows:
`
`1.
`
`I am making this Declaration at the request of LG Electronics, Inc.
`
`and LG Electronics U.S.A., Inc. in the matter of the Inter Partes Review of
`
`U.S. 6,411,941 (“the ’941 Patent”).
`
`2.
`
`I am being compensated for my work in this matter at my standard
`
`hourly rate. I am also being reimbursed for reasonable and customary expenses
`
`associated with my work and testimony in this proceeding. My compensation is not
`
`contingent on the outcome of this matter or the specifics of my testimony.
`
`3.
`
`My qualifications and professional experience are described in my
`
`Curriculum Vitae, a copy of which is attached to my declaration as Appendix A.
`
`4.
`
`I have reviewed the declaration of Dr. Andrew Wolfe (“Wolfe Decl.”
`
`(Ex. 1003)), submitted in IPR2020-01609. I agree with Dr. Wolfe’s opinions and
`
`analysis and adopt it as my own. Accordingly, it is my opinion that claims 1–3, 6–
`
`14, and 16 (“the Challenged Claims”) of the ’941 Patent would have been obvious
`
`to a person having ordinary skill in the art (“POSA”) at the time of the alleged
`
`invention.
`
`5.
`
`I declare that all statements made herein of my own knowledge are
`
`true and that all statements made on information and belief are believed to be true,
`
`and that these statements were made with knowledge that willful false statements
`
`2
`
`Ex. 1015
`LG Electronics v. Ancora / Page 2 of 17
`
`

`

`and the like so made are punishable by fine or imprisonment, or both, under
`
`section 1001 of Title 18 of the United States Code.
`
`Dated:______________
`
`_______________________
`Shahin Nazarian, Ph.D.
`
`3
`
`Ex. 1015
`LG Electronics v. Ancora / Page 3 of 17
`
`

`

`SHAHIN NAZARIAN
`(US CITIZEN)
`
`Associate Professor of Engineering Practice
`
`Department of Electrical Engineering, USC
`3740 McClintock Ave., Los Angeles, CA 90089
`shahin.nazarian@usc.edu
`http://sportlab.usc.edu/~shahin/
`Mobile: (626) 200-7893
`
`EDUCATION
`
`Ph.D., Electrical Engineering, University of Southern California, Los Angeles, CA
`Minor: Computer Science
`
`Major GPA: 4.0/4.0
`
`MSCENG, Computer Engineering, University of Southern California
`
`M.Sc., Electrical Engineering – Electronics, University of Tehran (UT), Tehran
`
`Major GPA: 4.0/4.0
`
`B.Sc., Electrical Engineering – Electronics, Tehran Polytechnic, Tehran
`
`WORK EXPERIENCE
`
`1/09 – Present
`
`University of Southern California, Los Angeles, CA
`Associate Professor of Engineering Practice
`- Teaching undergraduate/graduate courses in Computer/Electrical Engineering: EE590: Directed Research,
`EE250: Distributed Systems and Internet of Things, EE599: Special Topics – Software Design and
`Optimization for Electrical Engineers, EE595: Software Design and Optimization, EE580: System
`Verification, EE577A/B: VLSI System Design I/II, EE477: MOS VLSI Design, EE209: Foundations of Digital
`System Design, EE109: Introduction to Embedded Systems, EE101: Logic Design, EE450: Computer
`Networks, EE454: Introduction to System-on-Chip, EE357: Basic Organization of Computer Systems,
`EE355: Software Design for Electrical Engineers, EE352: Computer Organization and Architecture
`- Advising directed research (EE590) students, currently on the topics of machine learning, verification,
`hardware acceleration, low power design and optimization, signal integrity analysis and optimization, green
`technology design, MOS VLSI/CAD, smart grid, near/sub-threshold CMOS, memory design, neuromorphic
`computing
`- Supervising graduate students during their internship who are registered for ENGR596
`- A member of the CENG Ph.D. screening exam committee: designing the written exams (for Computer
`Networks, EE450) and oral exams (for CAD/VLSI courses EE477L, EE577A/EE658/EE680)
`- Designing the placements exams for EE450 (Computer Networks)
`- Writing recommendation letters for undergraduate/graduate USC students for their industrial and academic
`applications, and also helping them with their resume and interview preparation
`- Reviewer for IEEE Trans. on Computer Aided Design (TCAD), IEEE Trans. on Very Large Scale Integration
`(TVLSI), Journal of Lower Power Electronics (JOLPE), and Journal of Circuits, Systems and Signal
`Processing, Design and Test
`- Reviewer for different conferences, including Design Automation Conf., International Conference on
`Computer Aided Design, and Design Automation and Test in Europe, International Symposium on Low
`Power Electronic and Design
`
`1
`
`Ex. 1015
`LG Electronics v. Ancora / Page 4 of 17
`
`

`

`Vervecode Inc., South Pasadena, CA
`Founder and President
`- Providing consulting and testifying expert services.
`- Exploring the endless possibilities in the areas of computer science, engineering,
`and mathematics.
`
`2/16 – Present
`
`Quandary Peak Research, Beverly Hills, CA
`Senior Research Scientist
`- Working as a consulting expert on many cases related to operating systems, power management, firmware,
`computer architecture, wearable
`technologies, memory
`interfaces, security, GPS tracking,
`image
`processing, face recognition, SoC chips, LTE, etc.
`- Providing software analysis
`- Providing witness testimony
`
`2/15 – 8/18
`
`Magma Design Automation, San Jose, CA
`Senior Member of Technical Staff
`- Was involved in various projects in the Signal Integrity and Timer groups, such as multi-model multi corner
`timing analysis, on-chip variation consideration, as well as crosstalk delay and slew correlation issues
`- Was also involved in Current Source Model (CSM)-based timing tool development and also the main
`person to develop the first generation of CSM noise tool in Magma. (Tcl, C++, Hspice, Purifty)
`
`5/06 – 1/09
`
`Magma Design Automation, San Jose, CA
`R&D Design Engineer Intern
`- Designed and developed new crosstalk-aware gate delay modeling techniques (Perl, C, Matlab, Hspice)
`- Designed and developed methodologies to enhance the accuracy of Magma’s static and statistical static
`timing & crosstalk noise analysis tools (Tcl, C++, Hspice)
`
`5/04 – 8/04
`
`Lucent Technologies & Bell Labs Innovations, Holmdel, NJ
`Design Engineer (Intern) in Test Group
`- Developed an IEEE P1500 (SECT - Standard for Embedded Core Test) Wrapper with parallel access for
`Design for Testability (DFT) verification & System-on-Chip (SoC) testing (VHDL). Evaluated IEEE1532
`standard and compared it with 1149.1-based programming methods
`
`6/03 – 8/03
`
`TECHNICAL SKILLS
`
`The following are based on my research and industrial experiences, some of which also appear in my
`publications and/or incorporated into the courses I teach at USC:
`- Design and optimization of algorithms
`- Various machine learning and deep learning algorithms and packages
`- Software analysis: C/C++, Java, Perl, Python, Verilog, VHDL, SystemVerilog, SystemC, Assembly, etc.
`- Software licensing, database management, live streaming
`- SoC (System-on-Chip), NoC (Network-on-Chip), many-core, datacenters, server farms, IoT (Internet of
`Things) modeling and optimization
`- Cloud computing, mobile systems
`- Power (dynamic/leakage), Signal Integrity, power delivery networks, thermal analysis, cooling systems
`- Memory technologies: DDR2/DDR3/DDR4 DRAM, SRAM, Flash, memristors
`- Wearable technologies
`- Safety, security, hardware trojans
`- Interfaces including PCIe, AXI, UART, Ethernet, HDMI, I2C, and RS232
`- Communications networks protocols: routing algorithms, multiplexing and channelization, including OSPF,
`LTE, 802.3/5/11, Bluetooth Low Energy (BLE), socket programming for client-server protocols,
`- VLSI/FPGA/ASIC (spec to GDSII), CAD/EDA flows, 2D and 3D IC fabrication issues
`- System verification, UVM, assertions, Formal Verification/FPV, FPGA prototyping, and AI-aware techniques
`- IC technologies: CMOS, FinFETs, GAAs, superconducting/SFQ logic, memristors
`
`2
`
`Ex. 1015
`LG Electronics v. Ancora / Page 5 of 17
`
`

`

`SOFTWARE SKILLS
`
`Hardware Design/Simulation/Layout/Synthesis Tools:, MAGMA (currently part of Synopsys) timing tools:
`Talus, Tekton, Cadence tools: NCSim Tool Suite, Encounter, Virtuoso, Synopsys tools: DesignCompiler,
`DFTCompiler, TetraMax, PrimeTime, Hspice, TCAD/Sentaurus, Altera tools: Quartus II, SPICE, MAGIC,
`LEDIT, IRSIM, PROTEL (Altium Designer), XILINX ISE design tools.
`
`Software Tools: Cassandra, Kafka.
`
`Software Design and Analysis: SlickEdit, Understand, PowerGrep, BeyondMerge, WinMerge, Notepad++
`
`Programming Languages: C/C++, Python, Perl, TCL, VHDL, VERILOG, SystemVerilog, SystemC, Java,
`various Assembly languages.
`
`Debuggers: GDB, Gprof, Purify, ASAN, Eclipse.
`
`Platforms: Unix, Linux, Windows, OS X, Ubuntu.
`
`DEPOSITION TESTIMONY
`
`(cid:150)
`
`(cid:150)
`
`A Group of Customers (Weeks et al.) v. Google Inc.
`Jurisdiction: US District Court, Northern District of California, San Jose
`Division
`Counsel: Girard Gibbs, LLP, and Chimicles & Tikellis LLP
`(cid:150) Nature of Suit: Defective phones (microphone/audio codec issues)
`Case No. 5:18-cv-00801-NC
`
`Kinglite Holdings, Inc., vs. American Megatrends, et al.
`Jurisdiction: USPTO
`Counsel: Stadheim & Grear
`(cid:150) Nature of Suit: Invalidity of 6 patents
`https://quandarypeak.com/2016/04/nazarian-provides-deposition-
`testimony-in-bios-cases/
`
`(cid:150)
`
`(cid:150)
`
`12/18
`
`3/16 – 5/16
`
`3
`
`Ex. 1015
`LG Electronics v. Ancora / Page 6 of 17
`
`

`

`LITIGATION CONSULTING
`
`(cid:150)
`
`Arbor Global Strategies (ARBOR) LLC v. Xilinx, Inc.; Arbor Global Strategies
`LLC v. Samsung Electronics Co.
`Jurisdiction: US District Court for the Eastern District of Texas
`Counsel: Kramer Levin Naftalis & Frankel LLP (“KRAMER”)
`Services: Representing ARBOR. Consulting regarding die elements, and
`fabrication and layout of processors, related to patents 6,781,226;
`7,126,214; 7,282,951; and R,E42,035
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`
`GlobalFoundries Inc.
`Jurisdiction: Unfiled matter
`Counsel: Mintz
`Services: Representing GlobalFoundries. Investigating various
`technologies including FinFETs and layout formats including gdsII.
`
`(cid:150)
`
`(cid:150)
`
`
`GoPro, Inc. v. SZ DJI Technology Co. Ltd., DJI Europe B.V., & DJI Tech., Inc.
`Jurisdiction: Unfiled matter
`Counsel: Durie Tangri LLP
`Services: Representing GoPro. Studying various camera technologies
`(submersible microphone and heat transfer systems, etc.).
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`
`A Group of Customers (Diaz et al.) v. Nintendo of America, Inc.
`Jurisdiction: Unfiled matter
`Counsel: Chimicles Schwartz Kriner & Donaldson-Smith LLP
`(cid:150) Nature of Suit: Case No. 2:19-cv-01116-TSZ (W.D. Wash.)
`Services: Representing the group of customers. Studying numerous
`technical and research documents on the sources of drifting problems
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`
`Health Discovery Corporation
`Jurisdiction: Unfiled matter
`Services: Representing Health Discovery Corporation. Investigating
`various products, tools and workloads (including OpenCL, RealSense,
`DAAL, sklearn, sikit-learn, MineBench, BWA-ALN, GATK, ABySS, DIDA,
`BLASTp, BLASTn, Halvade, elPrep, MPI-HMMER, QIAGEN, several
`bioinformatics workloads, several processors, etc.) that employ
`machine learning algorithms, including Support vector machine-
`recursive feature elimination (SVM-RFE) and various deep learning
`techniques
`
`(cid:150)
`
`
`A Group of Customers (Weeks et al.) v. Google Inc.
`Jurisdiction: US District Court, Northern District of California, San Jose
`Division
`Counsel: Girard Gibbs, LLP, and Chimicles & Tikellis LLP
`(cid:150) Nature of Suit: Defective phones (microphone/audio codec issues)
`
`(cid:150)
`
`2/20 – Present
`
`8/19 – 11/19
`
`8/19 – Present
`
`8/19 – 12/19
`
`4/19 – Present
`
`10/18 – 3/19
`
`Ex. 1015
`LG Electronics v. Ancora / Page 7 of 17
`
`4
`
`

`

`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`Case No. 5:18-cv-00801-NC
`Services: Representing the group of customers. Studying numerous
`technical and research documents on the sources of microphone
`issues, underfill, stress testing, etc., running lab experiments on Google
`Pixel and Pixel XL phones, drafting expert report
`
`GlobalFoundries
`Jurisdiction: Unfiled matter
`Counsel: Quandary Peak Research
`Services: Building and simulating custom FinFET devices and analyzing
`current and parasitic capacitance and resistance components for
`various cases
`
`Sound View Innovations, LLC, v. Hulu, LLC
`Jurisdiction: US District Court, Central District of California, Western
`Division
`Counsel: Desmarais LLP
`(cid:150) Nature of Suit: Patent Infringement. Case No. 2:17-cv-04146-JAK-PLA
`Services: Represented Sound View Innovations. Source code review
`related to CDN (Content Delivery Network), stream processing, and
`distributed storage
`
`Synopsys v. Ubiquiti Networks
`Jurisdiction: Northern District of California
`Counsel: Morrison & Foerster LLP
`(cid:150) Nature of Suit: Tool License Violation
`Services: Representing Ubiquiti. Providing consulting on software
`licenses, and reviewing the evidences
`
`3M v. Amphenol Corporation
`Jurisdiction: US ITC, Washington, D.C.
`Counsel: Akin Gump Strauss Hauer & Feld LLP
`(cid:150) Nature of Suit: Infringement of three (wire shielding related) patents
`Services: Representing 3M. Providing consulting on wire shieling
`technologies, SI (signal integrity) issues and solutions, drafting expert
`reports
`
`A Group of Consumers v. Huawei Device USA, Inc. & Google Inc.
`Jurisdiction: US District Court, Northern District of California, San Jose
`Division
`Counsel: Girard Gibbs, LLP
`(cid:150) Nature of Suit: Defective phones (with battery drain and boot-loop
`defects)
`Services: Representing the group of customers. Studying numerous
`technical and research documents on the sources of boot-loop issues
`
`2/18 – 3/18
`
`12/17 – 7/18
`
`11/17 – 08/18
`
`10/17 – 11/17
`
`8/17 – 3/19
`
`5
`
`Ex. 1015
`LG Electronics v. Ancora / Page 8 of 17
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`

`

`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(electromigration, self-heating, HCI, BTI, loose solder joints,
`power/cooling/thermal systems, interactions with battery drain issues,
`etc.), running lab experiments on Nexus 6P phones, drafting expert
`report
`
`A Group of Consumers v. LG Electronics
`Jurisdiction: US District Court, Central District of California, Western
`Division
`Counsel: Girard Gibbs, LLP
`(cid:150) Nature of Suit: Defective phones (with Bootloop defect)
`Services: Representing the group of customers. Studying numerous
`technical and research documents on the sources of boot-loop issues
`(electromigration, self-heating, HCI, BTI, loose solder joints,
`power/cooling/thermal systems, etc.), running lab experiments on
`various LG phones, drafting expert report
`
`Semcon IP Inc, v. ZTE
`Jurisdiction: U.S. District Court, Eastern District of Texas, Marshall
`Division
`Counsel: Pillsbury Winthrop Shaw Pittman LLP
`(cid:150) Nature of Suit: Opening claim construction on 4 Semcon Patents
`(related to power optimization, etc.)
`Services: Represented ZTE. Source code review (Verilog, C), consulting,
`claim construction, draft expert report related to adaptive power
`optimization (DVFS, etc.)
`
`Broadcom v. MStar Semiconductor Inc., MediaTek Inc., & LG Electronics
`Inc.
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`Jurisdiction: U.S. District Court, Central District of California (C.D. Cal.)
`Counsel: Steptoe & Johnson LLP
`(cid:150) Nature of Suit: Infringement of 5 patents (related to image and video
`blending, etc.)
`Services: Represented Broadcom. Source code review (Verilog, VHDL,
`SystemVerilog, C/C++, Java, Perl) of numerous MStar, MediaTek and
`LG products consulting and drafting expert reports related to image
`and video processing and their hardware accelerators
`
`Image Processing Technologies LLC v. Samsung
`Jurisdiction: U.S. District Court, Central District of California (C.D. Cal.)
`Counsel: Andrews Kurth Kenyon LLP
`(cid:150) Nature of Suit: Infringement of 3 patents (related to face recognition)
`Service: Represented Image Processing Technologies. Source code
`review (Verilog, C), consulting related to pattern recognition, image
`processing
`
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`6/17 – 10/17
`
`5/17 – 9/17
`
`6/17 – 9/17
`
`6/17 – 8/17
`
`6
`
`Ex. 1015
`LG Electronics v. Ancora / Page 9 of 17
`
`

`

`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`NSN (Nokia Solutions and Networks) v. Huawei
`Jurisdiction: U.S. District Court, Eastern District of Texas, Marshall
`Division
`Counsel: Alston & Bird LLP
`(cid:150) Nature of Suit: Infringement of 9 Nokia patents (related to LTE
`technologies)
`Services: Represented NSN. Source code review (Verilog, VHDL,
`SystemVerilog, C/C++, Perl), consulting, drafting expert reports related
`to LTE and LTE-Advanced
`
`Pennsylvania One Call System Inc. v. Huckestein Mechanical Services Inc.,
`& Peripheral Manufacturing Inc.
`Jurisdiction: Common Pleas of Allegheny County, Pennsylvania
`Counsel: Deasey, Mahoney & Valentini, Ltd, Clark Hill, PLC & Burns
`White
`(cid:150) Nature of Suit: Server room equipment damage by fire suppression
`system
`Services: Represented Huckestein, consulting, analyzing and testing
`evidence
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`
`
`(cid:150)
`
`(cid:150)
`
` TiVo v. Samsung Electronics Co., Ltd, et al.
`Jurisdiction: U.S. District Court, Eastern District of Texas
`Counsel: Irell & Manella, LLP
`(cid:150) Nature of Suit: Patent
`Services: Represented TiVo. Source code review (Verilog,
`SystemVerilog, C), consulting, drafting expert report
`
`A customer (Grigor Melkonyan) v. Progressive Corporation
`Jurisdiction: Superior Court of California, County of Los Angeles
`Counsel: D&Z Law Group , LLP
`(cid:150) Nature of Suit: Insurance Dispute
`Services: Represented Grigor. Studied the evidence related to
`cellphone networks and prepared technical support
`
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`SpaceX
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`Jurisdiction: Unfiled matter
`Counsel: LydeckerDiaz
`(cid:150) Nature of Suit: Breach of contract
`Services: Confidential
`
`Fitbit v. Jawbone
`Jurisdiction: ITC, N.D. of California
`Counsel: Gibson, Dunn & Crutcher
`(cid:150) Nature of Suit: Intellectual Property – Patent
`Services: Represented Fitbit. Source code review of both Fitbit and
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`1/17 – 9/17
`
`1/17 – 8/17
`
`6/16 – 11/16
`
`4/16 – 11/16
`
`3/16 – 3/16
`
`11/15 – 5/16
`
`7
`
`Ex. 1015
`LG Electronics v. Ancora / Page 10 of 17
`
`

`

`Jawbone products (Assembly, C/C++, Verilog, VHDL, SystemVerilog,
`Java, Perl, Python, etc.), drafting expert reports related to Fitbit patents
`8868377, 8920332, 9026053, 9048923, 9089760, 9106307, 8909543,
`9031812, and 9042971, and Jawbone patents: 8073707, 8398546,
`8529811, 8961413, 8446275, and 8793522
`
`
`Kinglite Holdings, Inc., v.
`American Megatrends Inc., Micro-Star International Co., MSI Computer
`Corp., Giga-Byte Technology Co., & GBT Inc.,
`Jurisdiction: USPTO
`Counsel: Stadheim & Grear
`(cid:150) Nature of Suit: Intellectual Property – Patent
`Services: Presented Kinglite. Consulting and source code review
`(C/C++) related to one patent. Testimony and expert reports for 6
`patents related to operating systems, and BIOS graphics
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`(cid:150)
`
`
`Fujitsu v. Texas Instruments
`Jurisdiction: Cross-border Patent Licensing Negotiation
`Counsel: Morrison Forester LLP
`(cid:150) Nature of Suit: Intellectual Property – Patent
`Services: Represented Fujitsu. Provided consulting for many patents
`related to architecture, power optimization, cache policies, graphical
`processors, operating systems, etc.
`
`(cid:150)
`
`7/15 – 5/16
`
`6/15 – 5/16
`
`HONORS AND AWARDS
`
`ColdFlux: CAD Methodologies and Tools for Single Flux Quantum Based Superconductive Electronics. This
`is multi-disciplinary IARPA project involving a group of faculty members from various schools with Professor
`Pedram as the team lead. I work on the verification of SFQ. Awarded in December 2016 for the years 2017
`to 2022.
`Best Paper Nomination, ASPDAC Conference, 2016.
`Recipient of the first inaugural Dean’s Award for Teaching Excellence, Viterbi School of Engineering, April
`2014.
`Travel grant to attend BUPT to give several talks on my teaching style to faculty and students, May 31-June
`6, 2014.
`Travel grant awarded by Viterbi School to attend NETI-2 conference (Advanced National Effective Teaching
`Institute), Montreal, Canada, July 14-15, 2014.
`USC Center For Excellence In Teaching Innovative undergraduate teaching award, 2011
`Research Corporation (SRC) research grant ($100k per year 2006 to 2009) on proposal (written jointly with
`Professor Massoud Pedram) entitled “Statistical Static Timing & Power Analysis & Circuit Optimization,”
`2006.
`Best Paper Award nomination, International Symposium on VLSI Design, Automation and Test Conference
`(VLSI-DAT), April 2006.
`Recipient of Ph.D. graduate award from Association of Professors and Scholars of Iranian Heritage
`(APSIH), 2006.
`International Academic Achievement award, USC, 2006.
`Mentorship award of Young Student Support Program (YSSP), Design Automation Conf., San Diego, 2004.
`
`8
`
`Ex. 1015
`LG Electronics v. Ancora / Page 11 of 17
`
`

`

`Outstanding leadership award, USC, 2004.
`TxTEC (Texas Telecommunications Engineering Consortium) scholarship recipient on “Energy efficient
`VLSI architectures for communications and signal processing,” written jointly with Professor Nourani, 2000.
`Ranked 10th amongst about 5000 Electrical Engineers in the nationwide M.S. entrance exam, Iran.
`Outstanding intern award for the work in Takta Research Co., Tehran.
`Entrance Undergraduate Fellowship, Amirkabir University of Technology (Tehran Polytechnic).
`Ranked the 27th amongst more than 200000 in the nationwide B.S. entrance exam, Iran.
`Ranked the 3rd amongst more than 200000 in the Math category of the nationwide B.S. entrance exam, Iran.
`
`JOURNAL PUBLICATIONS
`
`1. M. Cheng, P. Bogdan, S. Nazarian, There Is Hope After All: Quantifying Opinion and Trustworthiness in
`Neural Networks, Frontiers in Artificial Intelligence, 2020.
`2. M. Cheng, J. Li, P. Bogdan, S. Nazarian, “H2O-Cloud: A Resource and Quality of Service-Aware Task
`Scheduling Framework for Warehouse-Scale Data Centers”, TCAD, 2019.
`3. G. Pasandi, R. Mehta, M. Pedram, S. Nazarian, “Hybrid Cell Assignment and Sizing for Power, Area,
`Delay Product Optimization of SRAM Arrays”, TCAS-II, 2019.
`4. Y. Xiao, S. Nazarian, P. Bogdan, “Self-Optimizing and Self-Programming Computing Systems: A
`Combined Compiler, Complex Networks and Machine Learning Approach”, TVLSI 2019.
`5. J. Li, Z. Yuan, Z. Li, A. Ren, C. Ding, J. Draper, S. Nazarian, Q. Qiu, B. Yuan, Y. Wang, "Normalization
`and Dropout
`for Stochastic Computing-Based Deep Convolutional Neural Networks", Elsevier’s
`Integration, the VLSI Journal, 2018.
`6. T. Cui, J. Li, Y. Wang, S. Nazarian, M. Pedram, “An Exploration of Applying Gate-Length-Biasing
`Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes”, IEEE Transactions on
`Emerging Topics in Computing (TETC), 2018.
`7. J. Li, X. Lin, S. Nazarian, M. Pedram, “CTS2M: concurrent task scheduling and storage management for
`residential energy consumers under dynamic energy pricing,” IET Cyber-Physical Systems: Theory &
`Applications, 2017.
`8. T. Cui, S. Chen, Y. Wang, Q. Zhu, S. Nazarian, M. Pedram, “An optimal energy co-scheduling framework
`for smart buildings,” Integration, the VLSI Journal 58, 2017.
`9. T. Cui, S. Chen, Y. Wang, S. Nazarian, and M. Pedram, “Optimal Control of PEVs with a Charging
`Aggregator Considering Regulation Service Provisioning,” IEEE Transactions on Cyber-Physical
`Systems, 2017.
`10. W. Lee, Y. Wang, T. Cui, S. Nazarian, and M. Pedram "TEI-power: Temperature Effect Inversion Aware
`Dynamic Thermal Management for FinFET Circuits", TODAES ((ACM Transactions on Design Automation
`of Electronic Systems), 2017.
`11. Y. Kun, J. Li, S. Nazarian, P. Bogdan, “Fundamental Challenges Towards Making IoT a Reality,”
`TODAES, 2017.
`12. T. Cui, S. Chen, Y. Wang, Q. Zhu, S. Nazarian, and M. Pedram. An Optimal Energy Co-Scheduling
`Framework for Smart Building,” Integration, the VLSI Journal, Oct. 2016.
`13. T. Cui, Y. Wang, S. Nazarian, and M. Pedram. “A Learning-Based Profit Maximization Algorithm for Utility
`Companies in an Oligopolistic Energy Market with Dynamic Prices and Intelligent Users”, AIMS Energy
`22-38, Jan. 2016.
`14. S. Nazarian, D. Das, “An Efficient Current-Based Logic Cell Model for Crosstalk Delay Analysis,”
`International Journal of Electronics, pp. 439-467, Volume 100, Issue 4, 2013.
`15. S. Nazarian, H. Fatemi, M. Pedram, “Accurate timing and noise analysis of combinational logic cells using
`current source modeling,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 92-
`103, Volume 19, Issue 1, Jan 2011.
`16. S. Nazarian, M. Pedram, “Analysis of coupled interconnects in VDSM technologies,” International Journal
`of Electronics, pp. 903-937, Volume 95, Issue 9, 2008.
`17. M. Pedram, S. Nazarian, “Thermal modeling, analysis, and management in VLSI circuits: Principles and
`Methods,” Proc. of IEEE Special Issue on Thermal Analysis of ULSI, pp. 1487-1501, Aug. 2006.
`
`9
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`

`

`CONFERENCE PUBLICATIONS
`
`18. Y. Hu, S. Nazarian, P. Nuzzo, “SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption
`Scheme,” VLSI-SOC, 2020.
`19. G. Pasandi, M. Peterson, M. Herrera, S. Nazairan, M. Pedram, “Deep-PowerX: A Deep Learning-Based
`Framework forLow-Power Approximate Logic Synthesis,” ISLPED, 2020.
`20. M. Cheng, S. Nazarian, P. Bogdan, “VRoC: Variational Autoencoder-aided Multi-task Rumor Classifier
`Based on Text,” WWW, 2020.
`21. S. Nazarian, P. Bogdan, “S4oC: A Self-optimizing, Self-adapting Secure System-on-Chip Design
`Framework to Tackle Unknown Threats – A Network Theoretic, Learning Approach,” Invited. ISCAS,
`2020.
`22. X. Wang, J. Chen, Y. Wang, M. Pedram, P. Bogdan, S. Nazarian, “Efficient Task Mapping for Manycore
`Systems,” ISCAS, 2020.
`23. Saeed Abrishami, A. Eshratifar, D. Eigen, Y. Wang, S. Nazarian, M. Pedram, “Efficient Training of Deep
`Convolutional Neural,” Invited. ISQED, 2020.
`24. S. Abrishami, M. Pedram, S. Nazarian, “NN-PARS: A Neural Network Method for Parallelizing Current
`Source Model Based Circuit Simulation,” ISQED, 2020.
`25. S. Abrishami, M. Pedram, S. Nazarian, “CSM-NN: A Neural Network Based Current Source Modeling
`Approach for Fast and Accurate Logic Circuit Simulation,” ICCD, 2019.
`26. S. Nazarian, A. Fayyazi, M. Pedram, “Low-Power Multi-Domain SFQ Logic - A Design and Verification
`Framework,” ICCD, 2019.
`27. P Bogdan, F Chen, A Deshwal, JR Doppa, BK Joardar, HH Li, S Nazarian, L. Song, Y. Xiao, “Taming
`extreme heterogeneity via machine learning based design of autonomous manycore systems,”
`CODES/ISSS, 2019.
`28. A. Fayyazi, S. Kunu, S. Nazarian, P.A. Beerel, M. Pedram, “SpRRAM: A Predefined Sparsity Based
`Memristive Neuromorphic Circuit for Low Power Application,” ISVLSI, 2019.
`29. K. Singh, V. Gupta, R. Gupta, A. Fayyazi, M. Pedram, S. Nazarian, “A Hybrid Framework for Functional
`Verification using Reinforcement Learning and Deep Learning”, GLSVLSI, 2019.
`30. M. Yan, Y. Feng, Y. Son, G. Pasandi, M. Pedram, S Nazarian, “kNN-CAM: A kNN-based Configurable
`Approximate Floating Point Multiplier for Energy-Area Minimization”, ISQED, 2019.
`31. G. Pasandi, M. Pedram, S Nazarian, “Approximate Logic Synthesis: A Reinforcement Learning-Based
`Technology Mapping Approach”, ISQED, 2019.
`32. A. Wong, K. Su, H. Sun, A Fayyazi, M Pedram, S Nazarian, “VeriSFQ: A Semi-formal Verification
`Framework and Benchmark for Single Flux Quantum Technology”, ISQED, 2019.
`33. A. Fayyazi, S. Nazarian, P. Nuzzo, M Pedram, “Deep Learning-Based Circuit Recognition Using Sparse
`Mapping and Level-Dependent Decaying Sum Circuit Representations”, DATE, 2019.
`34. C. J. Fourie, K. Jackman, M. M. Botha, S. Razmkhah, P. Febvre, C. L. Ayala, Q. Xu, N. Yoshikawa, E.
`Patrick, M. Law, Y. Wang, M. Annavaram, P. A. Beerel, S. Gupta, S. Nazarian, M. Pedram. “ColdFlux
`Superconducting EDA and TCAD Tools Project: Overview and Progress”, IEEE Transactions on Applied
`Superconductivity. Jan. 2019.
`35. F. Wang, H. Zhu, P. Popli, Y. Xiao, P. Bodgan, S. Nazarian, “Accelerating Coverage Directed Test
`Generation for Functional Verification: A Neural Network-based Framework", GLSVLSI, pp. 207-212,
`2018.
`36. R. Mehta, Y. Huang, M. Cheng, S. Bagga, N. Mathur, J. Li, J. Draper, S. Nazarian, "High Performance
`Training of Deep Neural Networks Using Pipelined Hardware Acceleration and Distributed Memory,"
`International Symposium on Quality Electronic Design (ISQED), 2018.
`37. Y. Xiao, S. Nazarian, P. Bogdan, “Prometheus: Processing-in-memory Heterogeneous Architecture
`Design from a Multi-layer Network Theoretic Strategy,” DATE, 2018.
`38. H. Yang, F. Kang, C. Ding, J. Li, J. Kim, D. Baek, S. Nazarian, X. Lin, P. Bogdan, N. Chang, "Prediction-
`Based Fast Thermoelectric Generator Reconfiguration for Energy Harvesting from Vehicle Radiators,"
`Proc. of Design Automation and Test in Europe (DATE), 2018.
`39. M. Cheng, J. Li, S. Nazarian, "DRL-Cloud: Deep Reinforcement Learning-Based Resource Provisioning
`and Task Scheduling for Cloud Service Providers," Proc. Asia and South Pacific Design Automation
`Conference (ASP-DAC), 2018.
`
`10
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`Ex. 1015
`LG Electronics v. Ancora / Page 13 of 17
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`

`

`40. Y. Xiao, Y. Xue, S. Nazarian, P. Bogdan, "A Load Balancing Inspired Parallel Execution Optimization
`Framework for Many-core Systems", Proc. of ICCAD, Nov. 2017.
`41. M. Nazemi, S. Nazarian, M. Pedram, “High-Performance FPGA Implementation of Equivariant Adaptive
`Separation via Independence Algorithm for Independent Component Analysis”, Proc. of the 28th Annual
`IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),
`July 2017.
`42. H. Cheng, J. Li, J. Draper, S. Nazarian, and Y. Wang, "Deadline-Aware Joint Optimization of Sleep
`Transistor and Supply Voltage for FinFET Based Embedded Systems", Proc. of ACM Great Lakes Symp.
`on VLSI, 2017.
`43. S. Nazar-shahsavani, A. Shafaei Bejestan, S. Nazarian, and M. Pedram. A Thermally-Aware Energy
`Minimization Methodology for Global Interconnects,” Proc. of Design Automation and Test in Europe, Mar.
`2017.
`44. J. Li, S. Nazarian, “Fast and Energy-Aware Resource Provisioning and Task Scheduling Algorithm for
`Cloud Systems”, Proc. of Int’l Symp. on Quality Electronic Design, Mar. 2017.
`45. L. Wang, T. Cui, S. Nazarian, Y. Wang, and M. Pedram. “Standard Cell Library Based Layout
`Characterization and Power Analysis for 10nm Gate-All-Around (GAA) Transistors,” Proc. of IEEE Int’l
`System-on-Chip Conference (SOCC), Sept. 2016.
`46. T. Cui, J. Li, A. Shafaei Bejestan, S. Nazarian, and M. Pedram, “An Efficient Timing Analysis Model for 6T
`FinFET SRAM using Current-Based Method,” ISQED, pp. 263-268, Mar. 2016.
`47. J. Li, X. Lin, S. Nazarian, and M. Pedram. “Negotiation-based resource provisioning and task scheduling
`algorithm for cloud systems,” Proc. of Int’l Symp. on Quality Electronic Design, Mar. 2016.
`48. T. Cui, S. Chen, Y. Wang, Q. Zhu, S. Nazarian, M. Pedram, “Optimal Co-Scheduling of HVAC Control and
`Battery Management for Energy-Efficient Buildings Considering State-of-Health Degradation,” ASP-DAC,
`Jan. 2016, (Best Paper Nomination).
`49. L. Wang, A. Shafaei, S. Chen, Y. Wang, S. Nazarian, and M. Pedram. “10nm Gate-Length Junctionless
`Gate-All-Around (JL-GAA) FETs Based 8T SRAM Design Under Process Variation Using a Cross-Layer
`Simulation,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Oct. 2015.
`50. W. Lee, D. Shin, Y. Wang, S. Nazarain, and M. Pedram. “Design and Optimization of a Reconfigurable
`Power Delivery Network for Large-Area, DVS-Enabled OLED Displays,” Proc. of the Int’l Symp. on Low
`Power Electronics and Design, July 2015.
`51. T. Cui, S. Chen, Y. Wang, S. Nazarian and M. Pedram. “Optimal Control of PEVs for Energy Cost
`Minimization and Frequency Regulation in the Smart Grid Accounting for Battery State-of-Health
`Degradation,” Proc. of Design Automation Conf., Jun. 2015.
`52. T. Cui, Y. Wang, S. Nazarian, and M. Pedram. “Layout Characterization and Power Density Analysis for
`Shorted-Gate and Independent-Gate 7nm FinFE