United States Patent r191
`Gephardt et al.
`
`[54] SYSTEM FOR DOCKING A PORTABLE
`COMPUTER TO A HOST COMPUTER
`WITHOUT SUSPENDING PROCESSOR
`OPERATION BY A DOCKING AGENT
`DRIVING THE BUS INACTIVE DURING
`DOCKING
`
`[75]
`
`Inventors: Douglas D. Gephardt, Austin; Scott
`Swanstrom, Cedar Park, both of Tex.
`
`[73] Assignee: Advanced Micro Devices, Inc., Austin,
`Tex.
`
`[21] Appl. No.: 255,663
`Jun. 9, 1994
`
`[22] Filed:
`
`Related U.S. Application Data
`
`[51]
`
`[63] Continuation-in-part of Ser. No. 217,951, Mar. 25, 1994,
`abandoned.
`Int. CI.6
`............................ G06F 13/14; G06F 13/20;
`G06F 13/36; G06F 13/40
`[52] U.S. Cl . .......................... 395/283; 395/281; 395/287;
`395/288; 364/231.1; 364/240; 364/242.7
`[58] Field of Search ..................................... 395n5o, 100,
`395/283, 281, 287, 288; 364/231.1, 240,
`242.7
`
`[56]
`
`References Cited
`
`U.S. PXI'ENT DOCUMENTS
`
`4,530,069
`4,769,764
`4,969,830
`4,999,787
`5,030,128
`5,052,943
`5,126,954
`5,175,671
`5,187,645
`5,195,183
`5,210,855
`5,241,542
`5,265,238
`5,313,596
`5,317,697
`
`7/1985 Desrochers .............................. 395/822
`9/1988 Levanon .................................. 361/680
`11/1990 Daly et al. . ............................. 439/136
`3/1991 McNally et al ......................... 364/514
`7/1991 Herron et al ........................... 439/372
`10/1991 Davis ...................................... 439/357
`6/1992 Morita ..................................... 361/683
`12/1992 Sasaki ..................................... 361/686
`2/1993 Spalding et al ......................... 361/686
`3/1993 Miller et al .......................... 395/200.2
`5/1993 Bartol ...................................... 395/500
`8/1993 Natarajan et al. ...................... 370/311
`11/1993 Canova, Jr. et al .................... 395/651
`5/1994 Swindler et al. . ...................... 395/325
`5/1994 Husak et al ............................. 395/325
`
`I IIIII IIIIIIII Ill lllll 111111111111111 1111111111 1111111111111111 Ill lllll llll
`US005632020A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,632,020
`May 20, 1997
`
`5,323,291
`5,353,417
`5,386,567
`5,394,552
`5,488,572
`5,526,493
`5,530,810
`
`6/1994 Boyle et al. . ........................... 361/683
`10/1994 Fuoco et al ............................. 395/325
`1/1995 Lien et al. . ............................. 395/700
`2/1995 Shirota .................................... 395/750
`1/1996 Belmont .............................. 364/514 R
`6/1996 Shu ......................................... 395/281
`6/1996 Bowman ................................. 395/281
`
`FOREIGN PXI'ENT DOCUMENTS
`
`0426134A2
`0426134A3
`0637793Al
`WO94/09425
`
`5/1991 European Pat. Off ..
`5/1991 European Pat. Off ..
`2/1995 European Pat. Off ..
`4/1994 WIPO .
`
`OTHER PUBLICATIONS
`
`HPSIR, Special Infrared Communications Specification,
`introduction pages and pp. 1-9.
`
`Primary Examiner-Thomas C. Lee
`Assistant Examiner-fil S. Kj_rn
`Attorney, Agent, or Firm-Foley & Lardner
`
`[57]
`
`ABSTRACT
`
`A computer system includes a bus arbiter for providing
`immediate access to a bus in response to an external require(cid:173)
`ment or event. In a <lockable computer system capable of hot
`docking or warm docking, the bus arbiter grants exclusive,
`non-preemptive access to the buses to the docking agent
`which is capable of quieting (rendering inactive) the bus of
`the portable computer and docking station in response to a
`notice signal. The notice signal is indicative of a change of
`states from the undocked state to the docked state or from
`the docked state to the undocked state. The notice signal may
`be provided from software, a user-actuated switch, or an
`infrared signal. In an audio-capable computer, the bus arbiter
`provides exclusive non-preemptive access to the digital
`signal processing peripheral device so that audio glitches are
`avoided. The arbiter preferably includes an override circuit
`for countermanding the fairness scheme employed by the
`bus arbiter and granting immediate bus access in response to
`the external event or condition. The bus arbiter preferably is
`able to provide fixed or rotating priority for bus accesses of
`other peripheral devices on the bus. The arbiter is preferably
`integrated with the main processor of the computer system.
`
`24 Claims, 6 Drawing Sheets
`
`10"\
`
`20
`
`22
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 1
`
`

`

`"' = N =
`"' ~
`
`N
`
`Ol
`
`
` ~
`
`i(cid:127)
`
`(cid:127)'
`
`0'I
`
`&.
`~
`
`-...J
`\0
`\0
`
`
`i(cid:127)
`(cid:127)'
`
`9
`~
`
`:f
`
`~ 4""1'-a
`
`~ • 00
`
`•
`
`-
`
`CIRCUIT
`CONTROL
`DOCKING
`
`(cid:127)
`
`!_
`44
`
`35
`'1
`
`40
`'1
`
`42
`~
`
`CONTROLLER
`
`MICRO-
`
`PERIPHERAL
`
`PERIPHERAL
`
`-
`
`_j
`46
`
`FIG. 1
`
`' I
`
`~
`V
`
`I'\
`
`34
`
`30
`
`28
`
`PERIPHERAL! I PERIPHERAL
`
`-_;_ -
`I
`40 I 6...------,
`50
`
`AGENT
`J DOCKING
`
`(
`32
`
`4 43
`7
`
`"n ml/
`r1
`26
`
`24
`
`27
`
`I (PU
`
`22
`
`20
`
`10'\
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 2
`
`

`

`"' = N =
`"' ~
`
`N
`
`Ol
`
`0'I
`~
`N
`~
`~
`0"'
`00.
`
`s N
`~ = ..... a
`
`"""" ~
`9
`
`---1
`
`•
`00
`~ •
`
`35
`i
`
`~
`
`J
`
`CONTROLLER
`
`MICRO-
`
`PERIPHERAL
`
`PERIPHERAL
`
`-
`
`FIG. 2
`
`47
`~
`
`,-
`
`t
`
`34
`
`J
`
`25
`
`3
`
`.
`
`~
`46
`
`22
`
`,--
`
`,--
`
`[_
`45
`
`-
`
`-
`
`I'
`I I _r'_
`43 I
`50
`
`--
`
`II H
`
`10"\
`
`30
`
`28
`
`26
`
`PERIPHERAL! I PERIPHERAL
`
`CPU
`
`I
`
`41
`
`24
`
`ARBITER
`
`52 ,-------, 40 .
`47
`
`20
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 3
`
`

`

`N
`~ w
`....
`Ol
`
`.... = N =
`
`0-.,
`
`~
`
`s,
`i
`
`t:I"'
`00
`
`--.,I
`~
`~
`lo(cid:173)
`
`~
`~
`~
`
`~ f"'t'-a
`~ • 00 •
`
`FIG. 3
`
`30
`
`28
`
`PERIPHERALI I PERIPHERAL
`
`89
`
`27
`
`PERIPHERAL
`
`AUDIO
`
`60
`
`70
`
`24
`
`CPU
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 4
`
`

`

`,... = N =
`
`N
`0"I. w
`,...
`Ot
`
`0'I
`~
`.a::,.
`~
`~
`t:I"'
`r:r.i
`
`--.J
`\0
`\0
`I-"
`F
`N
`~
`~
`
`~ a
`~ = ~
`d • 00
`
`•
`
`FIG. 4
`
`92
`
`107
`\
`
`1141 1\0
`
`I\
`
`I UO 11 C
`
`I\
`
`118
`
`.120
`
`J
`
`I
`
`, 122 I
`
`I
`
`128
`
`124
`
`129
`
`125
`
`126 I 130 I
`
`(GNTO PGNT
`
`(REQO
`
`REQl (GNTI
`
`AGENT
`
`PREQ
`
`140
`
`134
`
`105
`
`104
`
`106
`
`112
`
`100
`
`ARBITER
`
`141
`
`135
`
`142
`
`137
`
`143
`
`138
`
`90"\
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 5
`
`

`

`N
`~
`-..
`'-11
`
`-.. = N =
`
`r0 ..
`g:
`
`r0
`
`"""' 0-1
`0
`!JI
`
`1-- i ---1
`9
`N
`~
`~
`
`'"""" ~ a
`~
`•
`00
`~
`
`143
`142
`141
`140
`
`BACKOFF
`
`164
`
`PACK
`
`GNT3
`GNT2
`GNTl
`
`ACKNOWLEDGE
`
`LOGIC
`
`160
`
`I
`l LOGIC
`PRIMARY
`
`IRDY
`
`FIG. 5
`
`181
`
`1168
`
`1166
`
`1168
`
`166
`
`LOGIC
`REoum ~,e ' :] o PREO
`FRAME
`
`I
`I 182
`I
`
`½
`192
`
`171
`
`J
`
`1 LOGIC
`IO REQUEST
`
`I 1173
`
`I
`
`I
`
`_)
`162
`
`I I
`
`MONITOR I I
`
`LOCK
`
`1 LOGIC
`0 I REQUEST
`
`106 1~'17~0
`
`107
`
`I
`
`I
`
`I
`l ---•
`
`100
`
`160
`
`190
`
`150
`
`137 I
`
`136 I
`
`135 I
`
`f
`
`134
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 6
`
`

`

`N
`~
`01
`
`~ = N =
`
`~
`
`0'.
`s,
`0'.
`~ a
`t:r
`00.
`
`0
`
`"'-I
`~
`338 ~
`~
`~
`
`1-l
`
`"""' a
`• ;p
`~ • 7JJ.
`
`ACCESS BUS
`DEVICES TO
`PERIPHERAL
`
`ALLOW
`
`I
`
`DEASSERT
`
`PACK
`
`FIG. 6
`
`,J
`336
`.... u
`
`ASSERTION OF PACK
`REQ 0-3 DURING
`
`IGNORE
`
`332 """
`
`PACK
`ASSERT
`
`TRANSACTION
`OF CURRENT -
`.,..J WAIT FOR END '.,..J
`328 ""u
`326
`.,,u
`
`-
`
`GRANT 0-3
`DEASSERT
`
`REQUEST
`PRIMARY
`RECEIVE w
`324
`.,.1.,
`
`✓300
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 7
`
`

`

`5,632,020
`
`1
`SYSTEM FOR DOCKING A PORTABLE
`COMPUTER TO A HOST COMPUTER
`WITHOUT SUSPENDING PROCESSOR
`OPERATION BY A DOCKING AGENT
`DRIVING THE BUS INACTIVE DURING
`DOCKING
`
`RELATED APPLlCATIONS
`
`5
`
`2
`a lockout, deadlock, livelock or other arbitration condition
`which causes errors or inefficiencies on the bus. Locking
`errors may even cause fatal system errors or hardware
`crashes.
`Lockout errors can permanently prohibit a peripheral
`device from obtaining access to the bus. For example, a
`lower priority bus master may be locked out if two high
`priority bus masters on a peripheral component interconnect
`(PCI) bus attempt simultaneously to access the lower pri-
`10 ority bus master when it is locked (being held for the
`exclusive use of an initiator of an access). To prevent such
`an error, the fairness scheme countermands the priority
`scheme and guarantees the lower priority bus master access
`to the bus.
`Additionally, the fairness scheme is necessary to prevent
`locking errors such as deadlocks or livelocks. Deadlocks and
`livelocks occur when each of two bus masters must wait for
`a response from the other before an operation on the bus can
`be completed. Such a deadlock or livelock can be due to
`20 locked/exclusive bus transactions in combination with write
`back cache transactions. Also, deadlocks and livelocks may
`occur when an access is unable to be completed because
`other bus masters are utilizing necessary system resources.
`The fairness scheme even overrides a fixed priority
`25 scheme fo prevent locking errors. Therefore, prior art arbi(cid:173)
`ters are not capable of guaranteeing a particular bus master
`access to the bus in a particular amount of time ( a time(cid:173)
`bound access) because the fairness scheme can override the
`access by the particular bus master. Thus, although the
`30 fairness scheme is necessary to prevent locking errors, the
`fairness scheme disadvantageously prevents the bus arbiter
`from providing an exclusive (highest priority), non(cid:173)
`preemptive (non-interruptable) bus access.
`Particular computer systems such as <lockable computer
`systems and audio-capable computer systems are subject to
`decreased performance or even catastrophic failure if the
`systems do not respond immediately to an external situation
`(requirement or event). In these types of systems, a particu(cid:173)
`lar peripheral device must be given access to the bus for the
`system to respond to the external situation. Because the
`external situation often demands an immediate response, a
`bus arbiter is needed which provides an exclusive, non(cid:173)
`preemptive access to the bus so the particular peripheral
`device may quickly respond to the external situation.
`More particularly, an external event such as a docking
`event in a <lockable computer system requires a peripheral
`device or CPU undertake protective measures to prevent
`signaling failures, bus crashes and component damage
`caused by physically connecting or disconnecting active
`buses of the system. The active buses of the <lockable
`computer system may be advantageously protected by a
`docking agent, CPU, or other circuitry which quiets the
`active buses in response to the docking event. Exemplary
`docking agents, CPUs and other circuitry are discussed in
`55 U.S. Pat. application Ser. No. 08/217,951, filed Mar. 25,
`1994, entitled "An Apparatus and Method for Achieving Hot
`Docking Capabilities for Dockable Computer."
`Generally, the docking agent must receive ownership of
`the bus as soon as possible. Any time spent waiting for the
`60 bus arbiter to grant ownership is disadvantageous because
`the docking event may have to be delayed until ownership
`is granted. Further, prior art bus arbiters may preempt the
`control of the bus by the docking agent during the docking
`event thereby causing a catastrophic failure. Thus, there is a
`65 need for a <lockable computer system which includes a bus
`arbiter optimized for responding to an impending docking
`event.
`
`The present application is a continuation-in-part applica(cid:173)
`tion of U.S. patent application Ser. No. 08/217,951, filed
`Mar. 25, 1994, abandoned, entitled "An Apparatus and
`Method for Achieving Hot Docking Capabilities for a Dock(cid:173)
`able Computer System," assigned to the assignee of the
`present invention. The present application is also related to 15
`U.S. Pat. application Ser. No. 08/217,952, filed Mar. 25,
`1994, entitled "A Dockable Computer System Capable of
`Electric and Electromagnetic Communication," assigned to
`the assignee of the present invention.
`
`TECHNICAL FIELD
`
`The present invention relates generally to a computer
`system including a processor, a bus arbiter, and several bus
`masters coupled together on at least one bus, and more
`particularly to a bus arbiter for granting control of the at least
`one bus to one of the bus masters in response to an external
`requirement or event.
`
`BACKGROUND OF THE INVENTION
`
`35
`
`40
`
`Computer systems generally include a number of periph-
`eral devices coupled together on a bus. The peripheral
`devices perform a variety of data storage, computational,
`data manipulation, display, control and audio functions for
`the computer system. The peripheral devices are often bus
`masters-devices which are capable of initiating a read or a
`write transaction on the bus. The peripheral devices initiate
`and complete transactions on the bus as they efficiently
`perform their respective operations without unnecessarily
`burdening the CPU, other peripheral devices or other system
`resources.
`Computer systems having a number of bus masters
`employ a bus arbiter to assign ownership or control of the
`bus when one or more bus masters attempt to access it. Bus
`arbiters generally include a number of request-input and 45
`grant-output pairs, each pair associated with a particular bus
`master. When a bus master needs to access the bus to
`perform an operation, it provides a bus request signal to the
`bus arbiter. When the bus arbiter determines that the request(cid:173)
`ing bus master may have access to the bus, the bus master 50
`provides a grant signal. When the bus master receives the
`bus grant signal, the bus master has access to the bus and
`performs the operation.
`When two or more bus masters simultaneously request
`access to the bus, the bus arbiter determines which master
`should be granted access and which master should be denied
`access. The arbiter follows a fixed or rotational priority
`scheme when granting access to the bus. A fixed priority
`scheme assigns a priority order to each bus master and grants
`ownership of the bus in accordance with that priority order;
`a rotational priority scheme changes the priority order of
`each bus master over time in accordance with an algorithm,
`program or other method.
`Prior art bus arbiters, whether fixed or rotational, employ
`a fairness scheme (lock control) which overrides the priority
`scheme and temporarily reassigns the priority order to
`prevent a locking error on the bus. A locking error may be
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 8
`
`

`

`5,632,020
`
`3
`An external requirement such as the prevention of a
`"sound glitch" in an audio-capable computer system
`requires digital data representative of a sound wave to be
`procured within the stringent timing demands of digital
`sound production. Audio-capable computer systems gener(cid:173)
`ally employ a digital signal processing peripheral device to
`generate the digital data representative of the sound wave. If
`the peripheral device does not produce the digital data in the
`requisite time, the sound wave may contain an audibly
`noticeable "sound glitch" which affects the integrity of the
`sound wave and often annoys the user. Excess time spent
`waiting for the bus arbiter to grant ownership of the bus to
`the peripheral device delays the generation of the digital
`data, thereby causing the "sound glitch." Thus, there is a
`need for an audio-capable computer system including a bus
`arbiter optimized for preventing "sound glitches."
`Thus, there is a need for a bus arbiter which is able to
`grant access to the bus in response to an external event or
`requirement. More particularly, there is a need for a bus
`arbiter which includes a dedicated request/grant pair which
`provides exclusive and non-preemptive access to the bus.
`
`SUMMARY OF THE INVENTION
`The present invention relates to a computer system sub- 25
`ject to an external condition, including a plurality of periph(cid:173)
`eral devices operatively coupled with a bus. The computer
`system includes a bus arbiter having a primary acknowledge
`output coupled with a particular one of the peripheral
`devices. The bus arbiter provides a PRTh1ARY ACKNOWL(cid:173)
`EDGE signal on the primary acknowledge output in
`response to the external condition. The particular one of the
`plurality of the peripheral devices receives a time-bound
`access to the bus when the PRTh1ARY ACKNOWLEDGE
`signal is provided.
`The present invention also relates to a bus arbiter for use
`in a computer system having a bus, a first master and a
`plurality of second bus masters. The first bus master and the
`plurality of the second bus masters are coupled to the bus.
`The bus arbiter includes a primary request input coupled to
`the first bus master, a plurality of secondary request inputs
`coupled to the plurality of the second bus masters, a primary
`acknowledge circuit coupled to the primary request input, a
`secondary logic circuit coupled to the plurality of the
`secondary request inputs, and a lock monitor circuit coupled
`to the secondary logic circuit and a bus. The secondary logic
`circuit has a secondary output coupled to the primary logic
`circuit, and the lock monitor circuit provides a fairness
`signal. The secondary logic circuit provides a secondary
`select signal at the secondary output in accordance with a
`plurality of SECONDARY REQUEST signals received at
`the plurality of the secondary request inputs and the fairness
`signal. The primary logic circuit provides a primary select
`signal in response to a PRTh1ARY REQUEST signal on the
`primary request input and the secondary select signal. The
`primary logic circuit grants access to the bus in accordance
`with the primary select signal. The primary select signal
`grants access to the first bus master when the PRTh1ARY
`REQUEST signal is received.
`The present invention further relates to a <lockable com(cid:173)
`puter system comprised of a host computer unit including a
`station bus and a mobile computer unit including a unit bus.
`The <lockable computer system is capable of residing in a
`docked state in which the mobile computer unit is opera(cid:173)
`tively associated with the host computer station and an 65
`undocked state in which the mobile computer unit is physi(cid:173)
`cally separate from the host computer station. The <lockable
`
`4
`computer system also includes a docking agent which is
`coupled to the unit bus and provides a quiet request signal
`in response to the system changing between states. The
`improvement includes a bus arbiter having a quiet bus
`5 request input coupled to the docking agent. The bus arbiter
`grants control of the unit bus to the docking agent in
`response to the QUIEf BUS request signal.
`The present invention additionally relates to a method of
`docking or undocking a portable computer having a com-
`10 puter bus and a host station having a host bus. The portable
`computer includes a docking agent coupled to the computer
`bus for quieting the computer bus, peripheral devices
`coupled to the computer bus, a bus arbiter for granting
`access to the computer bus, and a notice circuit for gener(cid:173)
`ating a notice signal in response to docking or undocking the
`15 portable computer. The computer bus is physically, electri(cid:173)
`cally coupled to the host bus when the portable computer is
`docked with the host station. The method comprises the
`steps of granting time-bound access to the computer bus to
`the docking agent in response to the notice signal, the
`20 docking agent quieting the computer bus in response to
`being granted access by the bus arbiter, coupling or uncou(cid:173)
`pling the host bus and the computer bus, and allowing the
`peripherals to have access to the computer bus after the host
`bus and computer bus are coupled or uncoupled.
`The present invention still further relates to a portable
`computer for use in a <lockable computer system, capable of
`assuming at least two states, a docked state and an undocked
`state. The <lockable computer system includes a notice
`circuit before providing a notice signal when the <lockable
`30 computer system is about to change states, and a host station
`including a host bus coupled to a host connector. The
`portable computer includes a computer connector, a com(cid:173)
`puter bus coupled to the computer connector, a docking
`agent coupled to the computer bus and a bus arbiter. The host
`connector is physically coupled to the portable connector
`35 when the <lockable computer system is in the docked state,
`and the host connector is physically separate from the
`computer connector when the <lockable computer system is
`in the undocked state. The docking agent includes a quiet
`request output and provides a quiet request signal. The bus
`40 arbiter is coupled to the quiet request output and grants
`ownership of the computer bus to the docking agent in
`response to the quiet request signal.
`The present invention advantageously provides a bus
`arbiter optimized for allowing a peripheral device to respond
`45 to an external situation. The bus arbiter can provide an
`exclusive, non-preemptive access to the bus so a particular
`peripheral device may quickly respond to the external situ(cid:173)
`ation. The bus arbiter can also provide a time-bound access
`to the bus so a peripheral device can respond to the external
`50 situation in a minimum amount of time.
`In one aspect of the present invention, the bus arbiter is
`employed in a <lockable computer system and grants access
`to the bus to a docking agent in response to a docking event,
`In another aspect of the present invention, the bus arbiter
`55 grants access to a digital signal processing peripheral device
`in an audio-capable computer system so that "sound
`glitches" are avoided. In still a further aspect of the present
`invention, the bus arbiter includes a dedicated primary
`request input for receiving a request for a time-bound access
`60 to the bus, In yet another aspect of the present invention, the
`bus arbiter may provide a BACKOFF signal which requests
`the termination of the current bus transaction.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention will hereafter be described with reference
`to the accompanying drawings, wherein like numerals
`denote like elements, and:
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 9
`
`

`

`5,632,020
`
`5
`FIG. 1 schematically illustrates a dockable computer
`system employing a first exemplary embodiment of the
`present invention;
`FIG. 2 schematically illustrates a dockable computer
`system employing a second exemplary embodiment of the 5
`present invention;
`FIG. 3 schematically illustrates an audio-capable system
`employing a third exemplary embodiment of the present
`invention;
`FIG. 4 is a more detailed schematic block diagram of a
`bus arbiter in accordance with the present invention for use
`in the systems illustrated in FIGS. 1-3;
`FIG. 5 is a more detailed schematic block diagram of the
`bus arbiter illustrated in FIG. 4; and
`FIG. 6 is a simplified flow chart of the operation of the bus
`arbiter illustrated in FIG. 4.
`
`10
`
`30
`
`6
`peripheral device 42, peripheral device 40, or microcontrol(cid:173)
`ler 35 via system bus 24, connectors 34 and 36, and docking
`bus 46.
`When dockable computer system 10 is about to change
`states (a docking event), dockable computer system 10
`preferably provides an ADVANCE NOTICE signal warning
`of the impending docking event. Preferably, docking control
`circuit 44 includes circuitry for sensing an impending dock(cid:173)
`ing event and for communicating the ADVANCE NOTICE
`signal across a communication link 50, as described below.
`The ADVANCE NOTICE signal· can be provided on
`system bus 24, docking bus 46, communication link 50, or
`various control lines in dockable computer system 10. For
`example, when dockable computer system 10 changes from
`15 an undocked state to a docked state (an external event),
`communication link 50 preferably provides an infrared
`ADVANCE NOTICE (warning) signal which is received by
`docking agent 32. Communication link 50 can be an elec(cid:173)
`tromagnetic communication link, long pin interface, or
`20 wireless communication link such as those disclosed in U.S.
`patent application Ser. No. 08/217,952, filed Mar. 25, 1994,
`and entitled, "Dockable Computer System Capable of Elec(cid:173)
`tric and Electromagnetic Communication", assigned to the
`assignee of the present invention. Alternatively, portable
`25 computer 20 or docking station 22 can provide a software(cid:173)
`actuated ADVANCE NOTICE signal or a user-actuated
`ADVANCE NOTICE signal.
`Preferably, docking agent 32 operates to quiet or render
`inactive system bus 24 before it and docking bus 46 are
`physically coupled or uncoupled during a docking event.
`Docking agent 32 is shown as an off-line device which may
`or may not be involved in the non-docking operations of
`portable computer 20. Docking agent 32 operates similarly
`35 to a PCI agent device, host agent device, standard agent
`device or other device capable of quieting a bus.
`Docking agent 32 quiets system bus 24 generally by
`ensuring that there are no active transfers occurring on bus
`24 by asserting bus ownership over system bus 24, asserting
`40 bus mastership over bus 24, performing a software idle
`subroutine, performing an interrupt service routine which
`idles bus 24, or rendering bus 24 inactive. Docking agent 32
`is preferably designed along the lines of that circuitry
`described in U.S. Pat. application Ser. No. 08/217,951, filed
`45 March 25, 1994, entitled "An Apparatus and Method for
`Achieving Hot Docking Capabilities for a Dockable Com(cid:173)
`puter System."
`Bus arbiter 38 is integrated within CPU 26 and includes
`a quiet request input 40 coupled to a quiet request control
`50 line 47 and a quiet acknowledge output 42 coupled to a quiet
`acknowledge control line 49. CPU 26 is able to monitor bus
`activity on bus 24 via a bus input 27. Bus input27 preferably
`includes control lines for receiving signals such as a
`FRAME signal and an IRDY (Initiator Ready) signal uti-
`55 lized by the PCI protocol which indicate a transaction is
`occurring on bus 24. Docking agent 32 includes a quiet
`acknowledge input 44 coupled to quiet acknowledge control
`line 49, and a quiet request output 43 coupled to quiet
`request control line 47.
`Bus arbiter 38 is advantageously integrated with CPU 26
`so bus arbiter 38 is capable of disconnecting current bus
`cycles by providing an idle, stop, halt or other bus cycle
`control command to CPU 26 and peripheral devices 28 and
`30. Alternatively, bus arbiter 38 may signal CPU 26 or a bus
`65 bridge (not shown) to disconnect the current bus cycle. Bus
`arbiter 38 can also be integrated with other components such
`as a host or PCI bus bridge (not shown).
`
`60
`
`DETAILED DESCR1PTION OF THE
`PREFERRED EXEMPLARY EMBODIMENTS
`FIG. 1 is a schematic block diagram of a dockable
`computer system 10 including a portable computer 20 and a
`docking (host) station 22. Portable computer 20 is a mobile
`computer unit including a CPU 26, a system bus 24, a bus
`arbiter 38 and a· docking agent 32. Portable computer 20 can
`also include a peripheral device 28 and a peripheral device
`30. System bus 24 couples CPU 26, peripheral device 28,
`peripheral device 30 and docking agent 32. An external
`connector 34 is also coupled with system bus 24. System bus
`24 can be a CPU-to-memory bus, an I/0 bus, a standard bus,
`PCI bus, a sub-bus, a span bus or any other type of bus
`functionally operative in the microcomputer environment
`Alternatively, components of computer system 10 can be
`coupled together via bridges, sub-buses and other conduc(cid:173)
`tors (not shown), and CPU 26 can be coupled to bus 24 via
`a host/PC! bus bridge (not shown).
`Docking station 22 includes a docking control circuit 44
`coupled to a docking bus 46. Docking station 22 can also
`include a microcontroller 35, a peripheral device 40 and a
`peripheral device 42. Microcontroller 35 can be replaced by
`a more powerful microprocessor as warranted by applica(cid:173)
`tions for system 10, and it is within the scope of the present
`invention to utilize a minicomputer as the host system
`should the user so desire. Docking station 22 is a host station
`which can have superior, equal or inferior computing power
`compared to portable computer 20.
`Docking bus 46 couples docking control circuit 44,
`microcontroller 35, peripheral device 40 and peripheral
`device 42. An external connector 36 is also coupled to
`docking bus 46. Docking bus 46 can be a host-to-memory
`bus, an I/0 bus, a standard bus, a PCI bus, a sub-bus, a span
`bus or any other type of bus as noted generally above.
`When dockable computer system 10 is in an undocked
`state, external connectors 34 and 36 are not physically
`coupled. Therefore, in the undocked state, system bus 24 and
`docking bus 46 are not in physical, electrical communica(cid:173)
`tion. In this undocked state, portable computer 20 is oper(cid:173)
`able as a stand-alone computer and is physically separate
`from docking station 22.
`In the docked state, docking station 22 receives portable
`computer 20 so dockable computer system 10 operates as a
`single desktop computer or an integrated computer system.
`When dockable computer system 10 is in this docked state,
`external connectors 34 and 36 are physically coupled. With
`connectors 34 and 36 coupled, CPU 26 can electrically
`communicate with components in docking station 22 such as
`
`Petitioners Microsoft Corporation and HP Inc. - Ex. 1033, p. 10
`
`

`

`5,632,020
`
`7
`Bus arbiter 38 generally assigns ownership of bus 24 to
`peripheral device 28, peripheral device 30, peripheral device
`40 and peripheral device 42 in accordance with a fixed or
`rotational priority scheme and a fairness scheme. The fair(cid:173)
`ness scheme overrides the fixed or rotational priority scheme 5
`to prevent locking errors such as lockouts, livelocks and
`deadlocks.
`The operation of system 10 during an external situation
`such as a docking event is described below. Docking agent
`32 provides a quiet request (primary request) signal on quiet
`request control line 47 in response to receiving the
`ADVANCE NOTICE signal on communication link 50. Bus
`arbiter 38 receives the QUIEr REQUEST signal and deas(cid:173)
`serts all grants given to other bus masters such as CPU 26
`and peripheral devices 28 and 30. After the current bus
`transaction on bus 24 is completed, bus arbiter 38 grants bus
`ownership to docking agent 32 by providing a quiet
`acknowledge (primary acknowledge) signal across quiet
`acknowledge control line 49. Docking agent 32 is able to
`quiet system bus 24 in response to receiving the QUIEf
`ACKNOWLEDGE signal on quiet acknowledge control line
`49. Alternatively, bus arbiter 38 may grant CPU 26 owner(cid:173)
`ship of bus 24 for CPU-based bus quieting techniques.
`The QUIET ACKNOWLEDGE signal can advanta(cid:173)
`geously indicate that there are no active transfers occurring
`on bus 24. Because bus arbiter 38 has the capability to wait
`for the end of the current bus transaction, bus arbiter 38 may
`be configured to issue the QUIEr ACKNOWLEDGE signal
`only when bus 24 is completely idle (docking state safe).
`Thus, bus arbiter 38 may signal docking agent 32 that bus 24
`is quiet by providing the QUIEr ACKNOWLEDGE signal
`and eliminate the need for additional bus cycle monitoring
`circuitry.
`Preferably, bus arbiter 38 provides docking agent 32 with
`a time-bound access to bus 24, essentially to guarantee
`ownership of bus 24 to docking agent 32 upon request. In
`this preferred embodiment, time bound access refers to a
`high priority or primary access which allows agent 32 to
`gain control of bus 24 in an appropriate amount of time so
`that bus 24 may be prepared for the docking event. Bus
`arbiter 38 provides the time-bound access, preferably by
`employing a priority scheme which grants exclusive, non(cid:173)
`preemptive access to bus 24 in response to the QUIET
`REQUEST signal. This priority scheme grants the exclusive,
`non-preemptive access despite the action of the fairness
`scheme and allows docking agent 32 to be granted access to
`bus 24 when other high priority bus masters such as CPU 26
`and peripheral devices 28 and 30 contend for bus 24. Also.
`exclusive, non-preemptive access prevents other bus masters
`such as CPU 26, device 28, device 30, device 40 and device
`42 from removing bus ownership from docking agent 32.
`Thus, this time-bound access ensures that bus 24 may be
`quieted in a minimum amount of time so catastrophic failure
`is avoided as bus 24 is docked or undocked with docking bus
`46.
`System and application parameters typically define the
`amount of ti