llllll||||||||lllllllllllll|l||||I|l||||||l|ll||||||lllllllllllllllllllllll
`USOOS479639A
`
`United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,479,639
`
`Ewertz et al.
`[45] Date of Patent: Dec. 26, 1995
`
`
`
`[54]
`
`[75]
`
`[73]
`
`[21]
`
`[22]
`
`[63]
`
`[51]
`[52]
`
`[58]
`
`[56]
`
`COMPUTER SYSTEM WITH A PAGED
`NON-VOLAT]LE MEMORY
`
`Inventors: James H. Ewertz; Orville H.
`Christeson, both of Portland; Douglas
`L. Gabe], Aloha; Sean T. Murphy,
`Portland, all of Greg.
`
`OTHER PUBLICATIONS
`
`Markus A. Levy, “Designing with Flash Memory”, Circuit
`Cellar Ink, Dec. 1990, pp. 50—58.
`Jerry Jex, “Flash Memory BIOS For PC and Notebook
`Computers”, IEEE, 1990, pp. 692—695.
`Waite, et al., “Soul of CP/M”, Howard W. Sams and Co.,
`1983, pp. 2—7, 177—182 and 279~322.
`
`Assignee:
`
`Intel Corporation, Santa Clara, Calif.
`
`(List continued on next page.)
`
`Appl. No.: 279,692
`
`Filed:
`
`Aug. 26, 1994
`
`Primary Examiner—Tod R. Swarm
`Assistant Examiner—Hiep T. Nguyen
`Attorney, Agent, or Firm—Blakely, Sokoloif, Taylor & Zaf—
`man
`
`Related US. Application Data
`
`[57]
`
`ABSTRACT
`
`Continuation of Ser. No. 137,376, Oct. 14, 1993, Pat. No.
`5,371,876, which is a continuation of Ser. No. 698,318, May
`10, 1991, abandoned.
`
`Int. Cl.6 ...................................................... G061? 12/02
`US. Cl.
`.......................... 395/430; 395/479; 395/413;
`395/419; 364/DIG. 1
`Field of Search .............................. 364/200 MS File,
`364/900 MS File; 395/400, 425
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`364/706
`5/1979 Poland ............
`4,153,937
`395/400
`9/1981 Holtey et al.
`4,290,104
`395/400
`.
`2/1983 Bradley et al.
`4,374,417
`395/400
`.
`4/1984 Fletcher et al.
`4,441,155
`395/425
`.
`4/1984 Bradley et a1.
`4,443,847
`395/425
`8/1986 Kummer .........
`4,608,632
`8/1988 Byrd .................. 371/66
`4,763,333
`1/1989 Goss et a1
`......
`395/700
`4,799,145
`5/1989 Henderson et al.
`395/425
`4,831,522
`4/1989 Foreman et a1.
`395/700
`4,862,349
`7/1991 Styrna et al.
`395/275
`5,034,915
`.
`5,053,990 10/1991 Kreifels et a1.
`395/425
`5,117,492
`5/1992 Nash ...................
`395/400
`5,126,808
`6/1992 Montalvo et al.
`..
`357/235
`.....
`5,134,580
`7/1992 Bertram et a1.
`395/650
`
`8/1992 Bealkowski et al.
`5,136,713
`395/700
`
`......
`5,142,680
`8/1992 Otunan et al.
`395/700
`
`................... 395/700
`5,210,875
`5/1993 Bealkowski et al.
`
`
`
`A computer system wherein a paging technique is used to
`expand the useable non-volatile memory capacity beyond a
`fixed address space limitation. The computer system of the
`preferred embodiment includes a flash memory component
`for storing non-volatile code and data including a system
`BIOS in the upper 128K of memory. The useful BIOS
`memory space is effectively increased while maintaining the
`address boundary of the upper 128K region. The address
`space of the non-volatile memory device is logically sepa-
`rated into distinct pages of memory (Pages 14). Using the
`apparatus and techniques of the present invention, Page 1,
`Page 3 and Page 4 may be individually swapped into the
`address space originally occupied by Page 1 (the swappable
`page area). In the preferred embodiment, Page 2 is held
`static and thus is not used as a swap area. Each of the
`swappable pages, Page 1, Page 3, and Page 4, contain
`processing logic called swapping logic used during the
`swapping or paging operation. The swapping logic operates
`in conjunction with paging hardware to effect the swapping
`of pages into the swappable page area. The high order
`processor address lines are input by a page decoder. The
`page decoder is used to modify the address actually pre-
`sented to the non-volatile memory device. A page register
`provides a means by which the processor may select a page
`in non-volatile memory. In an alternative embodiment of the
`present invention, several different forms of configuration or
`identification information may be stored in a page of non-
`volatile memory.
`
`14 Claims, 11 Drawing Sheets
`
`
`
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`SAMSUNG EX. 1035 - 1/24
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`

`

`SAMSUNG EX. 1035 - 2/24
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`

`

`US. Patent
`
`m
`
`mwe2:mago—52
`
`
`mwooo<Sewn—mmMommooem
`
`936997495
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`5£5
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`
`
`SAMSUNG EX. 1035 - 3/24
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`

`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 2 of 11
`
`5,479,639
`
`256
`
`192K
`
`F0000h
`EFFFFh
`
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`E8000h
`
`320
`
`
`
`VIDEO (32K)
`
`EOOOOh
`128Km
`SWAPPING LOGIC
`
`—_-—-———————-————-———-—-—
`—-—————_—_—-_—-————_——-
`
`PAGE 3
`(303)
`
`PAGE 4
`(304)
`
`32]
`
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`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 3 of 11
`
`5,479,639
`
`
`
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`SAMSUNG EX. 1035 - 5/24
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`
`
`
`

`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 4 of 11
`
`5,479,639
`
`FIGURE 4
`
`PAGE = NEW_PAGE
`101
`
`102
`
`SWITCH_PAGE
`
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`

`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 5 of 11
`
`5,479,639
`
`FIGURE 5
`
`SW_SHADOW_OFF
`501
`
`SW_CACHE_OFF
`502
`
`
`
`
`
`
`PAGE >
`
`MAX_PAGE
`503
`
`NO-506
`
`PAGE_REG = PAGE_REG
`AND PAGE_REG_MASK
`0R PAGE
`507
`
`PAGE_ENTRY_TABLE
`(PAGE*2)
`508
`
`509
`
`JUMP TO NEW
`PAGE
`
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`

`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 6 of 11
`
`5,479,639
`
`FIGURE 6
`
`YES ~603
`
`SW_SWADOW_ON
`604
`
`PAGE = error page
`605
`
`
`606
`
`SW_CACHE_ON
`605
`
`TRUE_ENTRY_POINT
`
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`

`

`U.S. Patent
`
`Dec. 26, 1995
`
`Sheet 7 of 11
`
`5,479,639
`
`FFFFFh
`
`SWAPPING LOGIC ._.__..>
`
`Page 1
`
`Swappable Page Area
`(700)
`
`a . ________
`
`mooon
`EFFFFh
`
`RECOYERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`age 2
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`E8000h
`
`VIDEO (32K)
`
`EOOOOh
`
`(704)
`
`POST PTOSWTI
`(701)
`
`EFFFFh
`
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`E8000h
`
`VIDEO (32K)
`
`E0000h
`
`SWAPPING LOGIC
`
`SWAPPING LOGIC
`
`Run-Time BIOS
`
`Page 3
`
`g -
`
`Page 4
`
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`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 8 of 11
`
`5,479,639
`
`FIGURE 7b
`A
`
`Page 1
`
`Swappable Page Area
`(700)
`
` : 8
`(704)
`
`EFFFFh
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`>
`
`______
`
`"
`
`F0000h
`EFFFFh
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`age 2
`RESERVED FOR USER (8K)
`EAOOOh
`_____._______ —>
`RESERVED FOR SYSTEM (8K)
`E8000h
`_.._._______________
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`ESOOOh
`
`VIDEO (32K)
`
`VIDEO (32K)
`
`EOOOOh
`SWAPPING LOGIC
`
`_ _________
`
`EOOOOh
`
`Page 3
`
`= _
`
`SWAPPING LOGIC
`
`Run—Time BIOS
`
`P3864
`
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`

`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 9 of 11
`
`5,479,639
`
`705
`
`Swappable Page Area
`(700)
`
`F0000h
`EFFFFh
`
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`E8000h
`
`VIDEO (32K)
`
`EOOOOh
`
`
`(704)
`
`EFFFFh
`
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`E8000h
`
`VIDEO (32K)
`
`EOOOOh
`
`SWAPPING LOGIC
`
`Run-Time BIOS
`
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`

`

`US. Patent
`
`‘Dec. 26, 1995
`
`Sheet 10 of 11
`
`'
`
`5,479,639
`
`705
`
`FIGURE 7d
`
`POST Program
`(701)
`
`(700)
`
`EFFFFh
`
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`E8000h
`
`VIDEO (32K)
`
`EOOOOh
`
`SWAPPING LOGIC
`
`FOOOOh
`EFFFFh
`RECOVERY BIOS (16K)
`(Electronically protected from
`erasure or modification)
`ECOOOh
`
`RESERVED FOR USER (8K)
`EAOOOh
`
`RESERVED FOR SYSTEM (8K)
`E8000h
`
`VIDEO (32K)
`
`EOOOOh
`
`
`(704) Swappable Page Area
`
`Run-Time BIOS
`
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`

`US. Patent
`
`Dec. 26, 1995
`
`Sheet 11 of 11
`
`5,479,639
`
`FIGURE 8 COPY FLASH UPDATE ROUTINES
`802
`
`TO RANDOM ACCESS MEMORY
`
`SUBFUNCTION = 02 OR 82H
`CLEAR NON-VOLATILE
`MEMORY?
`803
`
`NO-806
`
`YES - 805
`
`
`
`
`
`SUBFUNCTION = 03 OR 83H
`WRITE NON-VOLATILE
`MEMORY?
`807
`
` WRITE SLOT INFORMATION IN FLASH
`
`NON-VOLATILE MEMORY
`
`808
`
`
`No - 313
`
`
` UPDATE FLASH NON-VOLATILE
`BOOKKEEPING SECTION
`
`810
`
` RELEASE FLASH UPDATE ROUTINE
`
`RANDOM ACCESS MEMORY
`
`
`811
`
`
`CONTINUE NORMAL
`. PROCESSING
`812
`
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`

`1
`COMPUTER SYSTEM WITH A PAGED
`NON-VOLATILE MEMORY
`
`This is a continuation of application Ser. No. 08/137,376,
`filed Oct. 14, 1993, now US. Pat. No. 5,371,876, which is
`a continuation of Ser. No. 07/698,318, filed May 19, 1991,
`abandoned.
`
`FIELD OF THE INVENTION
`
`The present invention relates to the field of computer
`systems. Specifically, the present invention relates to the
`field of computer system architectures incorporating a non-
`volatile forrn of basic operating system processing logic.
`
`BACKGROUND OF THE INVENTION
`
`Many prior art computer systems are typically configured
`at a minimum with a processor, a random access memory
`device, and a read only memory device. Some systems, such
`as a variety of calculators, may operate with only a processor
`and a read only memory device. Read only memory devices
`(ROM) provide a non-volatile form of memory that is not
`destroyed when power is removed from the computer sys-
`tem.
`
`Prior an computer systems are typically bootstrapped (i.e.
`power up initialized) using the processing logic (i.e. firm-
`ware) stored within the read only memory device internal to
`the computer system. Since the read only memory device is
`non-volatile, the firmware within ROM is guaranteed to
`contain valid data or instructions; thus, the prior an computer
`system can be reliably bootstrapped using firmware within
`ROM. Many computer systems have successfully used this
`technique. One such system is the IBM Personal Computer
`(PC) developed by the IBM Corporation of Armonk, NY.
`Prior an versions of the IBM PC use read only memory
`devices for storage of firmware or a basic input/output
`system (BIOS) software program. The BIOS is an operating
`system that provides the lowest level of software control
`over the hardware and resources of the computer system.
`ROM storage may also be used for non-volatile retention of
`network configuration data or application specific data.
`ROM devices in the prior art
`include basic read only
`memory devices (ROM), programmable read only memory
`devices (PROM), and erasable programmable read only
`memory devices (EPROM). Battery-backed random access
`memory devices such as CMOS RAM devices may also be
`used for non-volatile retention of network configuration data
`or application specific data in a computer system.
`Although ROM-based computer systems have been very
`successful in the prior art, a number of problems exist with
`the use of these devices in a computer system. Most com-
`puter systems have a finite address space in which each of
`the computer
`system resources must operate. These
`resources include ROM, random access memory (RAM),
`input/output devices, and possibly other processors. ROM
`devices with a BIOS contained therein are typically con—
`strained to a specific address range within the addsess space
`available. In order to maintain compatibility with a particu—
`lar computer architecture, designers and developers in the
`computer industry create products in reliance on a particular
`ROM address standard. For example,
`the IBM PC AT
`architecture mandates that the ROM BIOS and other firm—
`ware based applications are limited to a 128K address space
`at the top of the first megabyte of memory. With this'
`architecture, however, the ROM BIOS cannot exceed 128K
`of ROM space. Within this ROM space, the BIOS must
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,479,639
`
`2
`
`contain processing logic for initializing and controlling
`many of the hardware systems and resources of the com-
`puter system. With the increased functionality of modern
`computer systems, the complexity of hardware systems and
`resources increases as does the quantity of BIOS code
`required to support them. Also, because of new technologies
`and capabilities such as Extended Industry Standard Archi-
`tecture (EISA) systems, flash memory and multi-language
`support for international operation of a computer system, it
`is becoming increasingly unfeasible to fit all desired BIOS
`features within the 128K boundary of the IBM PC AT
`architecture. Other varieties of computer systems typically
`have an established limit for the size of their BIOS. Even
`
`though the need for expanding the BIOS boundary is grow-
`ing, the boundary cannot be arbitrarily modified without
`losing compatibility with established standards.
`Thus, a means for expanding the useable BIOS memory
`space without violating established BIOS address boundary
`standards is needed.
`
`SUMMARY OF THE INVENTION
`
`The present invention is a computer system wherein a
`paging technique is used to expand the useable non-volatile
`memory capacity beyond a fixed address space limitation.
`The computer system of the preferred embodiment com—
`prises a bus for communicating information, a processor
`coupled with the bus for processing information, a random
`access memory device coupled with the bus for storing
`information and instructions for the processor, an input
`device such as an alpha numeric input device or a cursor
`control device coupled to the bus for communicating infor-
`mation and command selections to the processor, a display
`device coupled to the bus for displaying information to a
`computer user, and a data storage device such as a magnetic
`disk and disk drive coupled with the bus for storing infor—
`mation and instructions. In addition, the computer system of
`the preferred embodiment includes a flash memory compo-
`nent coupled to the bus for storing non-volatile code and
`data. Devices other than flash memory may be used for
`storing nonvolatile code and data. Using the present inven-
`tion, a paging technique expands the useable non-volatile
`memory capacity beyond a fixed address space limitation.
`The flash memory device used in the preferred embodi-
`ment contains four separately erasable/programmable non-
`symmetrical blocks of memory. One of these four blocks
`may be electronically locked to prevent erasure or modifi—
`cation of its contents once it is installed. This configuration
`allows the processing logic of the computer system to update
`or modify any selected block of memory without affecting
`the contents of other blocks. One memory block contains a
`normal BIOS. The BIOS comprises processing logic instruc-
`tions that are executed by the processor.
`In the preferred embodiment, the BIOS is constrained to
`the upper 128K of the first Mbyte of the addressable memory
`space in the computer system. Because of computer system
`design constraints and compatibility,
`the BIOS may not
`occupy locations outside of the upper 128K region. In the
`present invention, the useful BIOS memory space is effec—
`tively increased while maintaining the 128K boundary of the
`upper 128K region. This enlargement of the useable BIOS
`space is realized using the paging technique of the present
`invention. In the preferred embodiment, the address space of
`the non-volatile memory device is logically separated into
`four distinct 64K byte pages of memory (Pages 1—4). Using
`the apparatus and techniques of the present invention, Page
`
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`

`5,479,639
`
`3
`1, Page 3 and Page 4 may be individually swapped into the
`address space occupied by the BIOS (the swappable page
`area). In the preferred embodiment, Page 2 is held static and
`thus is not used as a swap area.
`Each of the swappable pages, Page 1, Page 3, and Page 4,
`contain processing logic called swapping logic used during
`the swapping or paging operation. The swapping logic
`operates in conjunction with paging hardware to effect the
`swapping of pages into the region occupied by the BIOS.
`The high order processor address lines are input by a page
`decoder. The page decoder is used to modify the address
`actually presented to the non-volatile memory device. A
`page register provides a means by which the processor may
`select a page in non-volatile memory.
`In an alternative embodiment of the present invention,
`several different forms of configuration or identification
`information may be stored in a page of non-volatile memory.
`Configuration information in this form may include EISA
`configuration data, other bus protocol information or net-
`work information. Identification information may include an
`Ethernet address, system serial numbers, or software license
`numbers.
`
`It is therefore an object of the present invention to provide
`a means for expanding the memory capacity for the BIOS
`while maintaining address space boundaries. It is a further
`object of the present invention to provide a means for paging
`a system BIOS in a computer system. It is a further object
`of the present invention to provide a means for selecting a
`particular page of BIOS memory. It is a further object of the
`present invention to provide a means for swapping pages of
`BIOS. It is a further object of the present invention to
`provide a means for using page-resident processing logic for
`controlling the page swapping operation. It is a further
`object of the present invention to provide a means for
`maintaining at least one static page. It is a further object of
`the present invention to provide a means for storing con-
`figuration or identification information. It is a further object
`of the present invention to provide a means for storing and
`retrieving EISA information in flash memory.
`These and other objects of the present invention will
`become apparent as presented and described in the following
`detailed description of the preferred embodiment.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is an illustration of the computer system of the
`present invention.
`FIG. 2 is an illustration of the pages of BIOS used in the
`preferred embodiment.
`FIGS. 3a and 3b illustrate the paging hardware used in the
`present invention.
`FIGS. 4—6 are flow charts of the paging processing logic
`of the present invention.
`FIGS. 7a through 7d illustrate a memory map in various
`paging configurations.
`FIG. 8 illustrates processing logic for updating a flash
`memory device with EISA configuration data.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`The present invention is a computer system wherein a
`paging technique is used to expand the useable non-volatile
`memory capacity beyond a fixed address space limitation. In
`the following description, numerous specific details are set
`forth in order to provide a thorough understanding of the
`invention, however, it will be apparent to one of ordinary
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`skill in the art that these specific details need not be used to
`practice the present
`invention. In other instances, well
`known structures, circuits, and interfaces have not been
`shown in detail in order not to unnecessarily obscure the
`present invention.
`'
`Referring to FIG. 1, a block diagram of the architecture of
`the computer system of the present invention is illustrated.
`The preferred embodiment of the present invention is imple-
`mented using an 80386 or 80486 microprocessor manufac-
`tured by the Assignee of the present invention. It will be
`apparent to those of ordinary skill in the art, however, that
`alternative processors and computer system architectures
`may be employed. In general, such computer systems as
`illustrated by FIG. 1 comprise a bus 100 for communicating
`information, a processor 101 coupled with the bus for
`processing information, a random access memory device
`102 coupled with bus 100 for storing information and
`instructions for the processor 101, an input device 104 such
`as an alphanumeric input device or a cursor control device
`coupled to the bus 100 for communicating information and
`command selections to the processor 101, a display device
`105 coupled to the bus 100 for displaying information to a
`computer user, and a data storage device such as a magnetic
`disk and disk drive coupled with the bus 100 for storing
`information and instructions.
`
`In addition, the computer system of the preferred embodi—
`ment includes a read only memory component 103 coupled
`to the bus 100 for storing non—volatile code and data. In the
`preferred embodiment, read only memory device 103 is a
`flash memory component well known in the art.
`Several types of non—volatile memory devices currently
`existing in the art may be reprogrammed without removing
`the device from a circuit board on which the device is
`installed. One class of reprogrammable nonvolatile memory
`devices is flash memory. Several different types of flash
`memory devices exist in the art. Using a dedicated set of
`electrical signals, the contents of flash memory may be
`erased and reprogrammed with new data. Many prior art
`flash memory devices only allow complete erasure and
`reprogramming of all memory locations of the device. Other
`flash memory devices, however, are partitioned into sepa-
`rately erasable and programmable blocks of memory in a
`single flash memory device. In the preferred embodiment of
`the present
`invention, such a partitioned flash memory
`device is used. In the preferred embodiment,
`two flash
`memory devices denoted 28F001BT are used. The
`28F001BT flash memory devices are 1M bit memory
`devices manufactured by the Assignee of the present inven-
`tion. It will be apparent to those skilled in the art that other
`forms of reprogrammable non-volatile memory devices may
`be used with the invention taught herein. One example of
`such a non-flash device is an electrically erasable program-
`mable read only memory (EEPROM).
`The flash memory device used in the preferred embodi-
`ment contains four separately erasable/programmable non-
`symmetrical blocks of memory. One of these four blocks
`may be electronically locked to prevent erasure or modifi-
`cation of its contents once it is installed. This configuration
`allows the processing logic of the computer system to update
`or modify any selected block of memory without affecting
`the contents of other blocks. The dynamic updating of a
`selected area of non-volatile memory is the subject of a
`co-pending patent application Ser. No. 07/695,952, filed
`May 6, 1991, and assigned to the Assignee of the present
`invention.
`
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`In the preferred embodiment, a basic input/output system
`(BIOS) is stored in flash memory 103. In addition, other
`system and application specific processing logic and data
`parameters may also be stored in flash memory 103. The
`following sections describe how the contents of flash
`memory 103 may be paged in a manner allowing the
`effective size of the flash memory 103 to increase without
`expanding accesses beyond a fixed address boundary. It will
`be apparent to those skilled in the art that the paged flash
`memory technique of the present invention may be used in
`a computer system using any type of non-volatile memory
`and is not limited to a system employing flash memory.
`Referring to the preferred embodiment illustrated in FIG.
`2, a paged BIOS memory map of the contents of flash
`memory 103 is depicted. In the preferred embodiment, the
`BIOS is constrained to the upper 128K of the first Mbyte of
`the addressable memory space in the computer system. This
`address space is identified by region 320 illustrated in FIG.
`2. In the prior art, the 128K region 320 is used for storage
`of the BIOS. The upper region 301 is used for storage of the
`normal system BIOS while the lower region 302 is used for
`storage of other logic and data such as overflow BIOS code
`and/or data, video or other BIOS’s, set-up code or data, and
`other information or logic.
`In the present invention, the useful BIOS memory space
`is effectively increased while maintaining the 128K bound-
`ary of region 320. This enlargement of the useable BIOS
`space is realized using the paging technique of the present
`invention. In the preferred embodiment, the memory map
`illustrated in FIG. 2 is logically separated into four distinct
`64K byte pages of memory. These pages are denoted Page
`1 (301), Page 2 (302), Page 3 (303), and Page 4 (304). Using
`the apparatus and techniques of the present invention, Page
`3 (303) and Page 4 (304) may be individually swapped into
`the address space occupied by Page 1 (301). In the preferred
`embodiment, Page 2 (302) is held static and thus is not used
`as a swap area.
`
`It will be apparent to those skilled in the art that the 64K
`byte page size of the preferred embodiment may be imple-
`mented as a different page size in order to better accommo—
`date an alternative embodiment. The techniques of the
`present invention, however, may still be used with a different
`page size. Similarly, the preferred embodiment defines two
`swappable pages, page 3 (303) and page 4 (304), outside of
`the 128K boundary of region 320. It will be apparent to those
`skilled in the art that additional pages may be defined using
`the techniques of the present invention in order to further
`enlarge the useable area of the BIOS.
`Each of the swappable pages, Page 1 (301), Page 3 (303),
`and Page 4 (304), contain processing logic called swapping
`logic used during the swapping or paging operation. For
`example, the swapping logic for Page 1 (301) occupies a
`location in region 315. Similarly, each swappable page has
`swapping logic that resides in a fixed location relative to
`each page. The swapping logic operates in conjunction with
`paging hardware to effect the swapping of pages into the
`region occupied by Page 1
`(301). The operation of the
`swapping logic is described below in relation to the flow
`charts of FIGS. 4 and 5. The paging hardware of the present
`invention is described next.
`
`Referring now to FIG. 3a, a block diagram of the paging
`hardware of the present invention is illustrated. A portion of
`the interface between processor 101 and non-volatile
`memory or flash device 103 is an address presented to flash
`memory and/or decoder logic on address lines 210. The
`address signals thus presented define the location in flash
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`memory 103 accessed by processor 101. For purposes of
`illustration, address lines 210 are shown separated into two
`components. The address signals on lines 211 comprise the
`. low-order 16 bits of the address output by processor 101.
`Higher—order address signals are output on line 212. It will
`be apparent to those skilled in the art that the number of high
`order address signals presented on line 212 depends on the
`address width of processor 101. For purposes of illustration,
`only four address signals or bits are shown on line 212 in
`order to illustrate an access to the highest order location of
`flash memory 103.
`The four address lines on line 212 in the preferred
`embodiment are input by a page decoder 217. Page decoder
`217 is used to modify the address actually presented to flash
`memory 103 on address lines 219. A second input to page
`decoder 217 comes from a page register 214 on line 216.
`Page register 214 provides a means by which processor 101
`may select a page in flash memory 103. Processor 101
`selects a page by outputting a binary value on lines 215 that
`corresponds to the desired page. In the preferred embodi-
`ment, the output on line 215 to page register 214 is per-
`formed using an OUT instruction provided in the instruction
`set of processor 101. The use of an OUT instruction for
`loading an external register in this manner is well known in
`the art. Once page register 214 is loaded with a page number,
`this page number is provided to page decoder 217 on line
`216.
`
`'
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`Page decoder 217 manipulates the address actually pre-
`sented to flash memory 103 on address lines 219 by first
`reading the high order processor address bits received on
`lines 212. If the value represented by the high order pro-
`cessor address bits on lines 212 defines a processor access to
`the swappable page area (i.e. address range FOOOOh through
`FFFFFh), page decoder 217 then reads the page number
`stored in page register 214. The page number is used to
`replace the value of the high order processor address actu—
`ally output to flash memory 103 on address lines 219. In this
`manner, a processor access to the swappable page area can
`be redirected to a pre-determined page. If the value repre-
`sented by the high order processor address bits on lines 212
`defines a processor access to an area of flash memory other
`than the swappable page area, the page decoder 217 does not
`need to read the page register and the processor address is
`passed through unmodified to the flash memory device 103.
`An example of the operation of page register 214 and page
`decoder 217 is illustrated in FIG. 3b. If a value correspond-
`ing to Page 1 is loaded in page register 214 by processor 101
`and a processor address in the swappable page range F0000h
`through FFFFFh is presented by processor 101 on lines 211
`and 212, high order processor address bits 16—19 output by
`processor 101 on lines 212 each take a binary value of 1,
`thereby defining an address range of FOOOOh through
`FFFFFh. Because processor 101 has accessed the swappable
`page area, page decoder 217 is enabled to read page register
`214 for the value stored therein. In this example, page
`decoder 217 reads a value corresponding to Page 1 and
`replaces the high order processor address with the Page 1
`value. Thus, a flash memory address in the range of FOOOOh
`through FFFFFh is presented to the flash memory 103. This
`address range (FOOOOh through FFFFFh) corresponds to
`Page 1 (301) illustrated in FIG. 2. Because Page 1 was
`already located in the swappable page address space, no
`other page needed to be swapped in. Thus, for the simple
`case of Page 1, the processor address was essentially passed
`through to flash memory 103, even though the page decoder
`217 still performed the address modification. This case is
`illustrated in FIG. 7a.
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`In the preferred embodiment, Page 2 will never be loaded
`in page register 215, since this is a non-swappable page.
`Thus a processor access to the non-swappable address area
`(EOOOOh through EFFFFh) does not produce address modi-
`fication by page decoder 217. This case is illustrated in FIG.
`7b.
`
`Referring now to the Page 3 example illustrated in FIG.
`3b, page register 214 is loaded with a value corresponding
`to Page 3. A processor address in the swappable page range
`FOOOOh through FFFFFh is presented by processor 101 on
`lines 211 and 212. In this case, page decoder 217 reads the
`Page 3 value from page register 214 and replaces the high
`order processor address with the Page 3 value. This address
`modification results in a redirection of the processor address
`to a different address in flash memory 103 corresponding to
`the location of Page 3. In the example of FIG. 3b, the Page
`3 value is ODh. This value redirects the Page 3 access to the
`flash memory address range DOOOOh through DFFFFh. It
`will be apparent to those skilled in the art that the processor
`memory access may be redirected to any area of flash
`memory 103. Other alternative embodiments may use a
`different Page 3 value and thereby redirect a Page 3 access
`to a different location in flash memory 103. The Page 3 case
`is illustrated in FIG. 7c.
`
`In the Page 4 example shown in FIG. 3b, a Page 4 value
`of 0Ch is used to redirect a processor 101 access to the flash
`memory address range COOOOh through CFFFFh. Again, the
`redirection to address range C0000h through CFFFFh is
`only provided by way of example. Note also that
`the
`processor 101 is aware only of loading the page register and
`accessing the swappable page area (FOOOOh through
`FFFFFh) in flash memory 103. The processor 101 is not
`aware of the redirection of the high order processor address.
`The Page 4 case is illustrated in FIG. 7d.
`In the last two examples shown in FIG. 3b, processor 101
`accesses a non-swappable page area (i.e. area 301 ) so the
`address is not modified. In the first of these examples,
`processor 101 presents an address in the range EOOOOh
`through EFFFFh on lines 210. Since such an address is not
`in the swappable page area; therefore, the value in page
`register 214 becomes irrelevant. In this case,
`the page
`decoder 217 simply passes the processor address through to
`the flash memory 1