UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`Case No. 6:19-cv-00236-ADA
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`LG DISPLAY CO., LTD., a Korean
`corporation
`LG ELECTRONICS, INC., a Korean
`corporation
`and SONY CORPORATION, a
`Japanese corporation,
`
`Defendants.
`
`PLAINTIFF SOLAS OLED LTD.’S SECOND SUPPLEMENTAL
`RESPONSES AND OBJECTIONS TO DEFENDANTS’
`FIRST SET OF INTERROGATORIES (NOS. 1-17)
`
`Pursuant to Rules 26 and 33 of the Federal Rules of Civil Procedure, Plaintiff Solas OLED
`
`Ltd. (“Solas”) hereby objects and responds to Defendants LG Display Co., Ltd, LG Electronics, Inc
`
`and Sony Corporation’s (collectively “Defendants”) First Set of Interrogatories as follows:
`
`I.
`
`PRELIMINARY STATEMENT
`
`Discovery in this matter is still ongoing. Solas is presently pursuing its investigation and
`
`analysis of the facts and law relating to this case and has not completed such investigation or
`
`preparation for trial. Therefore, these responses and objections, while based on diligent factual
`
`exploration by Solas and its counsel, reflect only Solas’s current state of knowledge, understanding
`
`and belief with regard to the matters about which inquiry has been made. Solas anticipates that,
`
`1
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`LG DISPLAY CO., V. SOLAS OLED, LTD.
`IPR2020-01055
`Exhibit 2013
`Page 1 of 59
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`

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`interrogatory may be determined, including at least the following: SOLAS_LG_0013269;
`
`SOLAS_LG_0013371;
`
`SOLAS_LG_0019653-686;
`
`SOLAS_LG_0003213-3234;
`
`SOLAS_LG_0003149-3153; SOLAS_LG_0019644-19650; SOLAS_LG_0003146-48.
`
`Solas’s investigation is ongoing; Solas reserves the right to modify or supplement this
`
`response should additional information become available.
`
`SECOND SUPPLEMENTAL RESPONSE TO INTERROGATORY NO. 9 (OCT. 15, 2020):
`
`Solas further responds as follows. Pursuant to Federal Rule of Civil Procedure 33(d), Solas
`
`identifies the following documents from which information responsive to this interrogatory may
`
`be determined: SOLAS_LG_0021883-SOLAS_LG_0021892.
`
`Solas’s investigation is ongoing; Solas reserves the right to modify or supplement this
`
`response should additional information become available.
`
`INTERROGATORY NO. 10:
`
`For each Asserted Claim of the Asserted Patents, identify on an element-by-element basis
`
`all evidence, including portions of the specifications of the Asserted Patents and of any related
`
`patents or applications cited by page, column and line number (where relevant) and/or by reference
`
`to figures and their reference numerals (where relevant), that You contend provide sufficient
`
`written description support under 35 U.S.C. § 112 for that element.
`
`RESPONSE TO INTERROGATORY NO. 10:
`
`Solas objects to this interrogatory on the grounds that it is overbroad and unduly
`
`burdensome. Solas objects to this interrogatory on the grounds that it is impermissibly compound.
`
`Solas further objects to this interrogatory to the extent that it seeks information protected by the
`
`attorney-client privilege, the work product doctrine, or any other applicable privilege. Solas further
`
`objects to this request because it prematurely seeks disclosure of expert opinion. Solas further
`
`
`
`39
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`IPR2020-01055
`Exhibit 2013
`Page 2 of 59
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`objects that this interrogatory seeks contentions on a matter upon which Defendants bear the
`
`burden of proof by clear and convincing evidence. Defendants’ invalidity contentions fail to
`
`sustain any burden as to this issue and fail to adequately set forth with particularity any contention
`
`that the asserted claims lack written description support.
`
`Subject to and without waiving its specific or general objections, Solas responds as follows.
`
`Any contentions regarding written description at this stage of the litigation must necessarily be
`
`preliminary, both because written description is the proper subject of expert analysis, and because
`
`conclusions regarding written description require consideration of all, or at least a substantial
`
`portion, of the relevant evidence. An expert opinion on written description would be premature at
`
`this point at least because Defendants have not yet served their expert reports detailing their
`
`theories as to the alleged inadequacy of the written description of the Asserted Claims. Defendants
`
`carry the burden of proof to show that the Asserted Claims lack adequate written description, and
`
`Solas is not required to respond to theories that have not yet been fully propounded by Defendants.
`
`Should Defendants serve expert reports setting forth their theories alleging that the Asserted
`
`Claims lack adequate written description, Solas will serve a rebuttal expert report concerning
`
`validity on December 4, 2020, in accordance with the Court’s Scheduling Order (Dkt. No. 59),
`
`and Solas directs Defendants to that expert report.
`
`Solas’s investigation is ongoing; Solas reserves the right to modify or supplement this
`
`response should additional information become available.
`
`SUPPLEMENTAL RESPONSE TO INTERROGATORY NO. 10 (SEPT. 11, 2020):
`
`Solas further responds as follows. Despite bearing the burden to prove lack of written
`
`description by clear and convincing evidence, Defendants assertions are deficient and do not
`
`provide Solas with adequate notice. For example, Defendants’ final invalidity contentions merely
`
`
`
`40
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`LG DISPLAY CO., V. SOLAS OLED, LTD.
`IPR2020-01055
`Exhibit 2013
`Page 3 of 59
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`list various claim elements as purportedly lacking sufficient written description without any
`
`additional explanation, making it impossible for Solas to understand or even respond to
`
`Defendants’ assertions.
`
`A POSITA reading the specifications of the asserted patents, as well as any material
`
`incorporated by reference, would recognize that the specifications describe the full scope of each
`
`claim term identified by Defendants, and that the inventor(s) possessed the full scope of that term.
`
`An exemplary set of supporting portions of each specification is provided below. In addition to
`
`these identified exemplary disclosures, Solas incorporates all materials cited in the parties’ claim
`
`construction briefing concerning these limitations or portions thereof. To the extent that relevant
`
`claim language was construed by the Court, the claim construction proceedings in this case provide
`
`further support that the terms are consistent with the intrinsic evidence and have sufficient written
`
`description support. The below listings are not intended to be an exhaustive list, and should
`
`Defendants later be allowed to present actual theories and arguments supporting their contentions
`
`that the disclosed elements lack written description, Solas expressly reserves the right to rely on
`
`portions of the intrinsic record not included in this response.
`
`
`
`
`
`’891 Patent Claim Limitation
`
`Exemplary Disclosures
`
`“taps a diode driving current”
`
`Abstract, Fig. 1, 1:64-2:18, 2:65-3:12, 3:13-26,
`
`Claims 1, 3.
`
`“current measuring and voltage regulating
`
`Abstract, Fig. 1, 1:64-2:18, 2:65-3:12, 3:13-26,
`
`circuit”
`
`Claims 1, 3.
`
`
`
`41
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`Page 4 of 59
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`“the diode during driving of said gate of said
`
`Abstract, Fig. 1, 1:64-2:18, 2:65-3:12, 3:13-26,
`
`third transistor due to its non-linear switching
`
`Claims 1, 3.
`
`characteristic acts as a switch for a current
`
`deviation”
`
`“providing to the data conductor a voltage
`
`Abstract, Fig. 1, 1:5-12, 1:64-2:18, 2:65-3:12,
`
`signal which is dependent on a current
`
`3:13-26, Claims 1, 3.
`
`measuring and a voltage comparison”
`
`“wherein all above mentioned elements of the
`
`Abstract, Fig. 1, 1:45-54, 2:19-31, Claims 1, 3.
`
`driving circuit are located at a same side of said
`
`light emitting diode, so that no contacts must
`
`be guided through a semiconductor material of
`
`the diode”
`
`
`
`’068 Patent Claim Limitation
`
`Exemplary Disclosures
`
`“a plurality of light emitting layers which are
`
`Figs. 1-4 and associated description, Abstract,
`
`formed on said plurality of pixel electrodes”
`
`3:29-54, 4:15-23,
`
`“a plurality of signal lines which are patterned
`
`Figs. 23, 24, 25
`
`(including associated
`
`together with the gates of said plurality of
`
`descriptions), Abstract, 1:38–40, 2:52–53,
`
`driving transistors”
`
`2:62–65, 8:47–51, 9:44–53, 11:4–6, 14:46–48,
`
`25:4-27, 26:32-60, Claims 1, 3, 13, 15,
`
`“a plurality of supply lines which are patterned
`
`Abstract, Figs. 23, 24, 25, 1:38–40, 2:52–53,
`
`together with the sources and drains of said
`
`2:62–65, 8:47–51, 9:44–53, 11:4–6, 14:46–48,
`
`plurality of driving transistors”
`
`
`
`42
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`IPR2020-01055
`Exhibit 2013
`Page 5 of 59
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`
`
`’137 Patent Claim Limitation
`
`Exemplary Disclosures
`
`“data line”
`
`Figs. 1, 6, 7, 8, 11, 12, 15, 16 (and associated
`
`descriptions), 2:1-10, 2:12-25, 2:34-41, 2:53-
`
`63, 4:35-46, 4:47-5:2, 5:62-6:5, 12:1-17,
`
`12:30-63, 15:10-29, 16:19-32, 16:60-17:2,
`
`17:13-29, 17:58-67, 18:1-10, 18:19-31, 19:44-
`
`51, 19:58-65, 21:63-22:32, 23:20-29, 25:32-
`
`45, 27:1-15, 27:16-24, 28:61-66, 29:27-40,
`
`30:10-32, 31:15-38, Claims 1, 2, 10, 12, 13, 16,
`
`17, 18, 20, 25, 27, 28, 34, 36.
`
`“applies the compensation voltage to the drive
`
`Figs. 1, 6, 7, 8, 11, 12, 15, 16 (and associated
`
`element through the data line before the
`
`descriptions), 3:66-4:23, 4:35-46, 5:3-8, 5:23-
`
`gradation signal generation circuit supplies the
`
`27, 6:39-56, 7:16-40, 10:8-20, 10:26-40,
`
`gradation current to the display pixel”
`
`11:23-39, 16:52-59, 18:58-19:20, 19:58-65,
`
`25:32-45, 31:15-22, Claims 1, 7, 8, 10, 11, 14,
`
`16, 18, 19, 22, 27, 28, 34, 36, 37.
`
`“supplying, after the drive element holds the
`
`Figs. 1, 3, 4, 5, 8, 9, 10, 11, 14, 4:22-34, 5:34-
`
`voltage, a gradation current”
`
`41, 7:41-60, 10:45-59, 12:1-18, 13:46-67,
`
`
`
`
`
`
`
`20:26-36, 20:54-21:3, 36:22-35, Claims 1, 10,
`
`18, 36.
`
`43
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`IPR2020-01055
`Exhibit 2013
`Page 6 of 59
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`

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`Solas’s investigation is ongoing; Solas reserves the right to modify or supplement this
`
`response should additional information become available.
`
`SUPPLEMENTAL RESPONSE TO INTERROGATORY NO. 13 (SEPT. 11, 2020):
`
`Solas further responds as follows. Solas incorporates its responses to Interrogatories Nos.
`
`11 and 12 as containing information responsive to this interrogatory. Solas also identifies Gerald
`
`Padian as having knowledge responsive to this interrogatory.
`
` Pursuant to Federal Rule of Civil Procedure 33(d), Solas has produced or will produce
`
`documents from which further information responsive to this interrogatory may be determined,
`
`including at least the following: SOLAS_LG_0003193-97
`
`Solas’s investigation is ongoing; Solas reserves the right to modify or supplement this
`
`response should additional information become available.
`
`INTERROGATORY NO. 14:
`
`For each Asserted Claim of each Asserted Patent, describe whether you assert the claim is
`
`valid, and for each claim you assert is valid: (a) describe in detail each and every basis for your
`
`contention of validity; (b) with respect to each prior art reference, or combination of prior art
`
`references, identified by Defendants as a basis for invalidity under 35 U.S.C. § 102 or § 103,
`
`describe in detail each and every basis on which you contest such assertion of invalidity, including
`
`but not limited to which, if any, limitation of each claim you assert is not disclosed by that prior
`
`art reference or combination of prior art references, and describe in detail the complete basis for
`
`any disagreement you have with the analysis set forth by Defendants; (c) with respect to 35 U.S.C.§
`
`112, describe in detail each and every basis for your contention that the requirements of 35 U.S.C.§
`
`112 are satisfied, including describe in detail the complete basis for any disagreement you have
`
`with § 112 analysis set forth by Defendants; (d) identify all Documents you assert support your
`
`
`
`48
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`IPR2020-01055
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`assertions of validity; and (e) identify the three (3) Persons most knowledgeable about the factual
`
`bases for your assertions.
`
`RESPONSE TO INTERROGATORY NO. 14:
`
`Solas objects to this interrogatory on the grounds that it is overbroad and unduly
`
`burdensome. Solas objects to this interrogatory on the grounds that it is impermissibly compound.
`
`Solas further objects to this interrogatory to the extent that it seeks information protected by the
`
`attorney-client privilege, the work product doctrine, or any other applicable privilege. Solas further
`
`objects that this interrogatory seeks contentions upon matters which Defendants carry the burden
`
`of proof. Solas further objects to this request because it prematurely seeks disclosure of expert
`
`opinion.
`
`Subject to and without waiving its specific or general objections, Solas responds as follows.
`
`Solas asserts that each of the Asserted Claims is valid. The Asserted Patents are entitled to a
`
`presumption of validity and Defendants have failed to rebut that presumption. An expert opinion
`
`on validity would be premature at this point at least because Defendants have not yet served their
`
`expert reports detailing their theories as to the alleged invalidity of the Asserted Claims.
`
`Defendants carry the burden of proof to show by clear and convincing evidence that the Asserted
`
`Claims are invalid, and Solas is not required to respond to theories that have not yet been fully
`
`propounded by Defendants. Should Defendants serve expert reports setting forth their theories
`
`alleging that the Asserted Claims are invalid, Solas will serve a rebuttal expert report concerning
`
`validity, on December 4, 2020, in accordance with the Court’s Scheduling Order (Dkt. No. 59),
`
`and Solas directs Defendants to that expert report.
`
`Solas’s investigation is ongoing; Solas reserves the right to modify or supplement this
`
`response should additional information become available.
`
`
`
`49
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`LG DISPLAY CO., V. SOLAS OLED, LTD.
`IPR2020-01055
`Exhibit 2013
`Page 8 of 59
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`

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`SUPPLEMENTAL RESPONSE TO INTERROGATORY NO. 14 (SEPT. 11, 2020):
`
`Solas further responds as follows. As to § 112, Solas incorporates its supplemental response
`
`to Defendants’ Interrogatory No. 10. As to alleged lack of enablement or indefiniteness,
`
`Defendants bear the burden to prove these defenses by clear and convincing evidence. Defendants
`
`assertions are deficient and do not provide Solas with adequate notice. For example, Defendants’
`
`final invalidity contentions merely list various claim elements as purportedly lacking enablement
`
`or being indefinite without any additional explanation, making it impossible for Solas to
`
`understand or even respond to Defendants’ assertions. To the contrary, a POSITA would
`
`understand in view of the intrinsic and extrinsic evidence that each of the terms Defendants’
`
`identify are enabled and not indefinite. Further, Solas incorporates all materials cited in the parties’
`
`claim construction briefing concerning these limitations or portions thereof. To the extent that
`
`relevant claim language was construed by the Court, the claim construction proceedings in this
`
`case provide further support that the terms are enabled and not indefinite.
`
`As to prior art invalidity, Solas identifies and incorporates the relevant record in the file
`
`histories of the Asserted Patents, as well as any reexam or IPR proceedings. For example, Solas
`
`incorporates any Patent Owner Preliminary Responses and Patent Owner Responses (and material
`
`cited therein) that were or will be served in IPRs on the Asserted Patents, including:
`
`•
`
`IPR2020-01238 on the ’068 patent filed by Defendant LG Display Co., Ltd.; IPR2020-
`
`01055 on the ’137 patent filed by Defendant LG Display Co., Ltd; and IPR2020-00177
`
`on the ’891 patent filed by Defendant LG Display Co., Ltd.
`
`Further, Defendants have not shown that the lengthy list of alleged “prior art” is really prior
`
`art or that it provides any legitimate basis to invalidate these claims under any specific theory of
`
`anticipation or obviousness.
`
`
`
`50
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`IPR2020-01055
`Exhibit 2013
`Page 9 of 59
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`As to obviousness, Defendants have not charted any combination of references, or
`
`indicated which elements are missing from any reference or where those missing elements could
`
`be found in a different prior art reference. Defendants’ analysis of obviousness purporting to
`
`provide motivation to combine some “references identified in Appendix B” with “other references
`
`in Appendix B” does not provide Solas with notice of Defendants’ invalidity theories because it
`
`does not identify specific combinations of references and specific claim limitations. In their final
`
`invalidity contentions, Defendants state “[t]o the extent that Solas contends that any of the references
`
`identified in Appendix B do not disclose these limitations, a person of ordinary skill in the art would
`
`have arrived at the purported invention based on her own background knowledge and/or one or more
`
`of the prior art references identified in the chart below.” Defendants then present long string cites to
`
`various portions of the cited art for various limitations. Thus, for just a single claim element,
`
`Defendants attempt to combine any of the more than twenty references cited in its Appendix B
`
`with any other reference cited in Appendix B, resulting in thousands of possible permutations. If
`
`Defendants have an actual theory of invalidity based on obviousness, it is well-hidden among these
`
`thousands of possible combinations. It is unduly burdensome to ask Solas to address each of these,
`
`and Solas will not do so. In addition, none of these alleged combinations include any analysis of
`
`why a POSITA would look to the cited portion of the prior art and combine that with a particular
`
`embodiment described in a different reference. Defendants take a similar approach to obvious
`
`combinations involving references cited in Appendices A and C to their invalidity contentions,
`
`and the vast number of possible combinations similarly prevents Solas from learning of
`
`Defendants’ actual invalidity theories.
`
`As to Defendants’ purported anticipation analysis included in the claim charts attached to
`
`Defendants’ invalidity contentions, it is filled with citations to different embodiments within each
`
`alleged prior art reference. For this reason, the analysis is deficient. Defendants have also not
`
`
`
`51
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`IPR2020-01055
`Exhibit 2013
`Page 10 of 59
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`offered any analysis as to why any of the citations offered actually disclose the relevant claim
`
`limitation. Solas disagrees that any of these citations satisfy Defendants’ burden to prove by clear
`
`and convincing evidence that any of the claim limitations are present in the alleged prior art, much
`
`less that each limitation of any asserted claim in present in the prior art. Nor does Defendants’
`
`cursory assertions adequately show that a POSITA would understand that any claim limitation is
`
`present by clear and convincing evidence. Defendants’ anticipation (and obviousness) assertions
`
`also fail for the reasons that were or will be explained in Solas’s Preliminary Responses or Patent
`
`Owner Responses in IPRs challenging the Asserted Patents.
`
`Solas’s investigation is ongoing; Solas reserves the right to modify or supplement this
`
`response should additional information become available.
`
`SUPPLEMENTAL RESPONSE TO INTERROGATORY NO. 14 (OCT. 15, 2020):
`
`Solas stands on its objections to this interrogatory, including that it is overbroad, unduly
`
`burdensome, and calls for expert testimony. Solas also maintains that Defendants’ invalidity
`
`contentions are vague and ambiguous, deficient, and lack specificity making it impossible or
`
`impractical for Solas to respond. Neverthless, in the parties’ recent meet and confers, Defendants’
`
`requested that Solas provide some exemplary limitations that it believes are not satisfied by the
`
`prior art. Based on those discussion and with the understanding any identification of specific claim
`
`elements are exemplary and non-limiting, Solas further responds as follows:
`
`’068 Patent
`
`Solas identifies the following non-exhaustive claim limitations of the ’068 patent that
`
`Defendants have failed to show are disclosed, taught, or suggested by U.S. Patent No. 7,358,529
`
`(“Childs 529”):
`
`
`
`52
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`IPR2020-01055
`Exhibit 2013
`Page 11 of 59
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`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of the
`
`driving transistors being electrically connected to one of the supply lines; and”
`
`• “wherein the feed interconnections have a width of 7.45 to 44.00 μm”
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of driving
`
`transistors being electrically connected to one of the supply lines;”
`
`• “the feed interconnections are formed by patterning a material film which is
`
`different from a material film serving as a prospective pixel electrode and a material
`
`film serving as a prospective counter electrode and which is thicker than the gates
`
`of the driving transistors and the sources and drains of the driving transistors.”
`
`Solas further identifies the following non-exhaustive claim limitations of the ’068 patent
`
`that Defendants have failed to show are disclosed, taught, or suggested by U.S. Patent Application
`
`Pub. No. 2004/0149886 (“Matsueda 886”):
`
`
`
`53
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`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of the
`
`driving transistors being electrically connected to one of the supply lines; and”
`
`• “wherein the feed interconnections have a width of 7.45 to 44.00 μm”
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of driving
`
`transistors being electrically connected to one of the supply lines;”
`
`• “the feed interconnections are formed by patterning a material film which is
`
`different from a material film serving as a prospective pixel electrode and a material
`
`film serving as a prospective counter electrode and which is thicker than the gates
`
`of the driving transistors and the sources and drains of the driving transistors.”
`
`Solas further identifies the following non-exhaustive claim limitations of the ’068 patent
`
`that Defendants have failed to show are disclosed, taught, or suggested by U.S. Patent No.
`
`7,483,001 (“Matsueda 001”):
`
`
`
`54
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`IPR2020-01055
`Exhibit 2013
`Page 13 of 59
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`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of the
`
`driving transistors being electrically connected to one of the supply lines; and”
`
`• “wherein the feed interconnections have a width of 7.45 to 44.00 μm”
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of driving
`
`transistors being electrically connected to one of the supply lines;”
`
`• “the feed interconnections are formed by patterning a material film which is
`
`different from a material film serving as a prospective pixel electrode and a material
`
`film serving as a prospective counter electrode and which is thicker than the gates
`
`of the driving transistors and the sources and drains of the driving transistors.”
`
`Solas further identifies the following non-exhaustive claim limitations of the ’068 patent
`
`that Defendants have failed to show are disclosed, taught, or suggested by U.S. Patent No.
`
`6,933,533 (“Yamazaki 533”):
`
`
`
`55
`
`LG DISPLAY CO., V. SOLAS OLED, LTD.
`IPR2020-01055
`Exhibit 2013
`Page 14 of 59
`
`

`

`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of the
`
`driving transistors being electrically connected to one of the supply lines; and”
`
`• “a plurality of feed interconnections which are formed on said plurality of supply
`
`lines along said plurality of supply lines, respectively.”
`
`• “wherein the feed interconnections have a width of 7.45 to 44.00 μm”
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of driving
`
`transistors being electrically connected to one of the supply lines;”
`
`• “a plurality of feed interconnections which are connected to said plurality of supply
`
`lines along said plurality of supply lines”
`
`• “the feed interconnections are formed by patterning a material film which is
`
`different from a material film serving as a prospective pixel electrode and a material
`
`film serving as a prospective counter electrode and which is thicker than the gates
`
`of the driving transistors and the sources and drains of the driving transistors.”
`
`
`
`56
`
`LG DISPLAY CO., V. SOLAS OLED, LTD.
`IPR2020-01055
`Exhibit 2013
`Page 15 of 59
`
`

`

`Solas further identifies the following non-exhaustive claim limitations of the ’068 patent
`
`that Defendants have failed to show are disclosed, taught, or suggested by EP1130565A1
`
`(“Yumoto 565”):
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of the
`
`driving transistors being electrically connected to one of the supply lines; and”
`
`• “wherein the feed interconnections have a width of 7.45 to 44.00 μm”
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of driving
`
`transistors being electrically connected to one of the supply lines;”
`
`• “the feed interconnections are formed by patterning a material film which is
`
`different from a material film serving as a prospective pixel electrode and a material
`
`film serving as a prospective counter electrode and which is thicker than the gates
`
`of the driving transistors and the sources and drains of the driving transistors.”
`
`
`
`57
`
`LG DISPLAY CO., V. SOLAS OLED, LTD.
`IPR2020-01055
`Exhibit 2013
`Page 16 of 59
`
`

`

`Solas further identifies the following non-exhaustive claim limitations of the ’068 patent
`
`that Defendants have failed to show are disclosed, taught, or suggested by U.S. Patent No. 6281552
`
`(“Kawasaki 552”):
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of the
`
`driving transistors being electrically connected to one of the supply lines; and”
`
`• “a plurality of feed interconnections which are formed on said plurality of supply
`
`lines along said plurality of supply lines, respectively.”
`
`• “wherein the feed interconnections have a width of 7.45 to 44.00 μm”
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of feed interconnections which are connected to said plurality of supply
`
`lines along said plurality of supply lines”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of driving
`
`transistors being electrically connected to one of the supply lines;”
`
`
`
`58
`
`LG DISPLAY CO., V. SOLAS OLED, LTD.
`IPR2020-01055
`Exhibit 2013
`Page 17 of 59
`
`

`

`• “the feed interconnections are formed by patterning a material film which is
`
`different from a material film serving as a prospective pixel electrode and a material
`
`film serving as a prospective counter electrode and which is thicker than the gates
`
`of the driving transistors and the sources and drains of the driving transistors.”
`
`Solas further identifies the following non-exhaustive claim limitations of the ’068 patent
`
`that Defendants have failed to show are disclosed, taught, or suggested by Japanese Patent
`
`Application No. 2002318555 (“Koyama 555”):
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`the substrate;”
`
`• “a plurality of supply lines which are patterned together with the sources and drains
`
`of said plurality of driving transistors and arrayed to cross said plurality of signal
`
`lines via the gate insulating film, one of the source and the drain of each of the
`
`driving transistors being electrically connected to one of the supply lines; and”
`
`• “wherein the feed interconnections have a width of 7.45 to 44.00 μm”
`
`• “a plurality of signal lines which are patterned together with the gates of said
`
`plurality of driving transistors and arrayed to run in a predetermined direction on
`
`th