(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0067971 A1
`(43) Pub. Date:
`Mar. 31, 2005
`Kane
`
`US 2005OO67971A1
`
`(54) PIXEL CIRCUIT FOR AN ACTIVE MATRIX
`ORGANIC LIGHTEMITTING DODE
`DISPLAY
`
`(76) Inventor: Michael Gillis Kane, Skillman, NJ
`(US)
`Correspondence Address:
`DANN, DORFMAN, HERRELL & SKILLMAN,
`P.C.
`SARNOFF CORPORATION
`1601 MARKET STREET, SUITE 720
`PHILADELPHIA, PA 19103 (US)
`(21) Appl. No.:
`10/953,087
`(22) Filed:
`Sep. 29, 2004
`Related U.S. Application Data
`(60) Provisional application No. 60/507,060, filed on Sep.
`29, 2003.
`
`Publication Classification
`
`(51) Int. Cl. ................................................... G09G 3/10
`
`(52) U.S. Cl. ..................................... 315/169.3; 315/169.1
`
`(57)
`
`ABSTRACT
`
`A pixel circuit for an OLED element comprises first, Second,
`third and fourth transistors wherein controllable conduction
`paths of the first and Second transistors are connected for
`receiving a data Signal current, and the control electrodes
`thereof are connected for receiving a Select signal for being
`enabled thereby. The third and/or fourth transistors are
`connected for establishing a current in the OLED element
`responsive to the data Signal current and the Select signal.
`Capacitance may be provided by at least one of the transis
`tors or by additional capacitance.
`
`Vold
`
`
`
`100"
`
`Select line S
`
`data line
`
`LG Display Co., Ltd.
`Exhibit 1019
`Page 001
`
`

`

`Patent Application Publication Mar. 31, 2005 Sheet 1 of 2
`
`US 2005/0067971 A1
`
`Vodd
`
`OLED
`
`10
`
`Select line B
`
`Select line A
`
`data line
`
`FIGURE 1
`
`(PRIOR ART)
`
`
`
`Select line S
`
`1OO
`
`
`
`data line
`
`FIGURE 2
`
`LG Display Co., Ltd.
`Exhibit 1019
`Page 002
`
`

`

`Patent Application Publication Mar. 31, 2005 Sheet 2 of 2
`
`US 2005/0067971 A1
`
`Void
`
`100'
`
`
`
`Select line S
`
`data line
`FIGURE 3
`
`data line
`
`FIGURE 4
`
`Vodd
`
`OLED
`
`LG Display Co., Ltd.
`Exhibit 1019
`Page 003
`
`

`

`US 2005/OO67971 A1
`
`Mar. 31, 2005
`
`PXEL CIRCUIT FOR AN ACTIVE MATRIX
`ORGANIC LIGHT-EMITTING DODE DISPLAY
`0001) This Application claims the benefit of U.S. Provi
`sional Application Ser. No. 60/507,060 filed Sep. 29, 2003.
`0002 The present invention relates to a pixel circuit, and
`in particular to a pixel circuit Suitable for an active matrix
`display.
`Passive matrix organic light-emitting diode
`0.003
`(OLED) displays suffer from a limitation in the number of
`lines (i.e. rows) in a display due to activation of one line at
`a time thereby to require a high current flow needed to
`provide moderate average current to each line. An active
`matrix OLED (AMOLED) display Substantially mitigates
`these problems because the OLED pixels can operate all the
`time. Analog data is written into the AMOLED pixel array
`one row at a time, but the OLEDs thereof are operated at
`essentially 100% duty cycle. This is accomplished by pro
`Viding an analog memory circuit for each pixel using active
`devices, i.e. transistors.
`0004. Many existing AMOLED pixels and drive schemes
`apply to Voltage-programmed displayS. A voltage-pro
`grammed display is one in which the analog data that is
`applied to the display is applied as a voltage. The alternative
`is a current-programmed display, wherein the analog data is
`applied to the display as a current.
`0005 All active-matrix liquid-crystal displays (AML
`CDs) are voltage-programmed, because the liquid-crystal is
`a Voltage-Sensitive element. It is like a capacitor whose
`electro-optic properties are Sensitive to the Voltage acroSS it.
`But an OLED is different. The brightness of an OLED
`element depends primarily on the current through it, and
`only Secondarily on the Voltage that is applied in order to
`produce that current. In an AMOLED display there are
`transistors in each pixel circuit, and the programming of the
`pixel circuit to drive the desired current through the OLED
`is accomplished by applying a Voltage to the transistors in
`the pixel circuit (for a voltage-programmed pixel), or by
`applying a current to the transistors in the pixel circuit (in a
`current-programmed pixel). Of course, the configuration of
`the transistors in the pixel will be different in the two cases.
`0006. In a voltage-programmed display, the data applied
`to the data lines, i.e. columns, is a Voltage, not a current, and
`it is much faster to charge the large capacitance associated
`with the column to its Steady-State Voltage from a Voltage
`Source than from a current Source. (Even with current
`programming, the column capacitance must be charged to its
`Steady-state Voltage before the pixel can be considered
`programmed, because until the capacitance is charged, Some
`of the programming current is being diverted to charge the
`column capacitance rather than to program the pixel.) The
`main disadvantage of current-programmed AMOLED pixels
`is the difficulty of charging the column within a line time.
`0007 On the other hand, in a voltage-programmed dis
`play pixel the analog data is applied as a Voltage, but it must
`be converted to a current that will be driven through the
`OLED element. This voltage-to-current conversion is per
`formed by a transistor relying on its transconductance, a
`Small-signal quantity g=AI/AV that represents the ratio of
`current-output to Voltage-input at a given bias level, So that
`the OLED element current will vary with the transconduc
`tance of a transistor in the pixel circuit. Because transcon
`
`ductance depends on Such factors as the mobility of the
`transistor and the gate capacitance, which can vary acroSS
`the display thereby creating nonuniformity within a display,
`and from display to display, requiring each display module
`to be individually adjusted at the factory. In addition, Voltage
`programmed pixels can also have Sensitivity to transistor
`threshold Voltage, which varies acroSS the display and from
`display to display, which also produces similar display
`nonuniformity.
`0008. In a current-programmed pixel, however, non-uni
`formity in the transconductance of the transistor does not
`necessarily produce non-uniformity in the display. The ana
`log data Signal is applied as a current, and this value of
`current (or some fixed multiple of it) is applied to the OLED
`element and So transistor non-uniformities are not a prob
`lem. However, certain prior-art current-programmed pixels
`can have a Secondary problem with transistor nonuniformi
`ties because of mismatch between the two transistors form
`ing a current mirror in the pixel circuit.
`0009 FIG. 1 is an electrical circuit schematic diagram of
`a prior art pixel circuit 10 which operates as follows. When
`the pixel is to be programmed, both Select lines A and B are
`pulsed high. A programming current I is drawn from the data
`line by the column driver circuit. Since all other pixels in this
`column are unselected, the current I flows through transis
`tors P1 and N2 (once the column and pixel have been
`charged to a stable Voltage). Since transistor N1 is on at this
`time, transistor P1 Self-biases to a gate-to-Source Voltage
`that sets its drain current to equal the programming current
`I. Then select lines A and B are turned off, and the voltage
`on the gate of transistor P1 is stored there with the help of
`capacitor C. Since transistor P2 is matched to transistor P1,
`and they share the same gate-to-Source Voltage, and assum
`ing transistor P2 is kept in Saturation, the OLED drive
`current is now Set to the same value as the programming
`current I, or a fixed multiple thereof, depending on the size
`ratios of transistors P1 and P2. (This configuration of two
`transistorS is known as a current mirror, because the current
`flowing through transistor P1 is “mirrored” by that flowing
`through transistor P2.) This current through the OLED
`element continues to flow while transistors N1 and N2 are
`off. The overall brightness of the display can be scaled down
`by pulsing Select line B prior to the time for programming
`the pixel again, one frame time later. This turns on transistor
`N1 without turning on transistor N2, so that transistor P1
`Self-biases to Zero current, and the current through transistor
`P2 and the OLED drops to Zero as well for the rest of the
`frame time.
`0010. To reduce the disadvantage of longer charging time
`of a current-programmed OLED display driven from a fixed
`current Source, the column charging time may be reduced by
`using a programming current I that is larger than the desired
`OLED current. The ratio of the channel width of transistor
`P1 to that of transistor P2 in the current mirror (e.g., the
`“width ratio” of P1 to P2) may be used to scale the
`programming current down to the appropriate level. Thus,
`transistor P1 might be five times wider than transistor P2,
`and the programming current I is set by the driver chip to be
`five times higher than the desired OLED current, so that five
`times the program current is available to charge the data line
`capacitance.
`0011 Disadvantageously, prior art pixel circuit 10 must
`be fabricated using a polysilicon technology because it has
`
`LG Display Co., Ltd.
`Exhibit 1019
`Page 004
`
`

`

`US 2005/OO67971 A1
`
`Mar. 31, 2005
`
`two p-channel devices, which can not be made using an
`amorphous-silicon (a-Si) thin-film transistor (TFT) technol
`ogy. Amorphous Silicon TFT processing is more readily
`available and is lower in cost than polysilicon TFT process
`ing, but a-Si TFTs are only available as n-channel devices.
`The p-channel devices in this prior art pixel circuit 10 cannot
`Simply be replaced with n-channel devices, with appropriate
`circuit changes, because this will place the OLED (whose
`anode is accessible to the transistors) in the Source of the
`n-channel transistor, and the prior art circuit 10 will not
`work.
`0012. Accordingly, it would be desirable to have a pixel
`circuit that may utilize only n-channel transistorS So as to be
`compatible with a-Si TFT processing, e.g., by permitting the
`OLED to be in the Source of the current mirror transistors,
`as well as compatible with polysilicon processing. It would
`also be desirable to have an improved pixel circuit that may
`utilize n-channel transistors and p-channel transistors that
`can be fabricated with polysilicon processing.
`0013 To this end, a pixel circuit for an OLED element
`comprises first, Second, third and fourth transistors wherein
`controllable conduction paths of the first and Second tran
`Sistors are connected for receiving a data Signal current, and
`the control electrodes thereof are connected for receiving a
`select signal for being enabled thereby. The third and/or
`fourth transistors are connected for establishing a current in
`the OLED element responsive to the data Signal current and
`the Select Signal. Capacitance may be provided by at least
`one of the transistors or by additional capacitance.
`BRIEF DESCRIPTION OF THE DRAWING
`0.014. The detailed description of the preferred embodi
`ment(s) will be more easily and better understood when read
`in conjunction with the FIGURES of the Drawing which
`include:
`FIG. 1 is an electrical circuit schematic diagram of
`0.015
`a prior art pixel circuit;
`0016 FIG. 2 is an electrical circuit schematic diagram of
`an example embodiment of a pixel circuit;
`0017 FIG. 3 is an electrical circuit schematic diagram of
`an example embodiment of a pixel circuit; and
`0.018
`FIG. 4 is an electrical circuit schematic diagram of
`an example embodiment of a pixel circuit.
`0019. In the Drawing, where an element or feature is
`shown in more than one drawing figure, the same alphanu
`meric designation may be used to designate Such element or
`feature in each figure, and where a closely related or
`modified element is shown in a figure, the same alphanu
`merical designation primed. Similarly, Similar elements or
`features may be designated by like alphanumeric designa
`tions in different figures of the Drawing. It is noted that,
`according to common practice, the various features of the
`drawing are not to Scale, and the dimensions of the various
`features are arbitrarily expanded or reduced for clarity, and
`any value Stated in any Figure is given by way of example
`only.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT(S)
`0020 Current-programmed AMOLED pixel circuits are
`described, Some of which employ transistors of only one
`
`polarity, e.g., only n-channel transistors, which could be
`provided using amorphous Silicon thin-film transistor (a-Si
`TFT) technology, e.g., as used in conventional AMLCD
`displayS. Alternatively, even though polysilicon processes
`can produce both n-channel and p-channel transistors, it
`might be desirable to Simplify the poly Silcon transistor
`process by fabricating transistors of only one polarity. Other
`pixels described herein use transistors of both polarities, i.e.
`both n-channel and p-channel transistors, which could be
`provided using conventional CMOS processes, Such as a
`low-temperature polysilicon CMOS process.
`0021. A current mirror circuit provides a current through
`the OLED pixel element that is a predetermined multiple of
`the programming current, wherein the multiplier may be
`unity or may be greater or less than unity. Good matching is
`required of the two transistors in the current mirror, So that
`the OLED current is a well-defined function of the program
`ming current. However, in polysilicon it is difficult to get
`two transistors to match, even if they are next to each other,
`because the random grain Structure of the polysilicon mate
`rial produces "random' device variations. As a result, the
`OLED element current may have a “random' component,
`and the display can be nonuniform.
`0022. The pixels described herein address this need for
`matching in two different ways: (a) by using a current mirror
`formed of n-channel transistors, which are compatible with
`amorphous Silicon processing and therefore do not manifest
`the random nonuniformities of polysilicon transistors, or (b)
`by utilizing the same transistor to both receive the program
`ming current and, after programming, to drive current
`through the OLED element, so that no matching problem
`SCS.
`0023 Plural pixel circuits described are typically
`arranged in rows or lines of a Scanned display. The time
`taken to Scan each row (line) is referred to as the line time
`or Select interval, and the time taken to Scan all rows (lines)
`of a display is referred to as the frame time. Each pixel
`circuit is programed to provide a current that is a Scaled
`value of a programming or data current applied thereto
`during a line time which is a portion of the frame time in a
`Scanned display. Each pixel is typically "refreshed” or
`reprogrammed during the line time and the line time is 1/N
`of the frame time where there are N lines in the display.
`0024 FIG. 2 is an electrical circuit schematic diagram of
`an example embodiment of a pixel circuit 100. An
`AMOLED pixel employs a current-programmed current
`mirror N1, N2 in which the OLED element is in the Source
`of the mirror transistors N1, N2. The circuit 100 shown uses
`n-channel transistors, although one skilled in the art could
`translate the circuit into an implementation with p-channel
`transistors. However, because OLED technology typically
`makes the anode of the OLED elements accessible to the
`transistors, n-channel transistor technology is more natural.
`Circuit 100 is thus compatible with a-Si TFT processing.
`0025 Operation of circuit 100 is as follows. When the
`row is Selected, the Select line S is pulsed high, turning on
`transistorS N3 and N4, and a programming or data current I
`is driven down the row by the column driver circuit via the
`data line conductor. After the column line and pixel capaci
`tances are charged, this data current I flows through tran
`sistors N4, N1, and the OLED element. A gate-to-source
`voltage is established on transistor N1 that is the proper
`
`LG Display Co., Ltd.
`Exhibit 1019
`Page 005
`
`

`

`US 2005/OO67971 A1
`
`Mar. 31, 2005
`
`Voltage value for establishing a drain current of value I to
`flow through transistor N1. At the same time a current flows
`through transistor N2 that is a scaled version of the current
`I flowing through transistor N1, depending on the Size ratioS
`of transistorS N2 to N1, Since their gates are connected in
`parallel and So receive the same gate-to-Source Voltage, as
`long as both transistors are kept in Saturation.
`0026. At the end of the line time, i.e. the time in which
`the current flowing in element OLED is established respon
`Sive to the data current I, the Select pulse on the Select line
`S becomes low, and transistors N3 and N4 are turned off.
`The gate-to-Source Voltage at the gate of transistorS N1 and
`N2 is Stored on capacitor C. Amorphous Silicon transistors,
`such as transistors N1, N2, typically exhibit relatively large
`capacitances between their gate and Source/drain electrodes,
`and So a separate element providing a capacitance C may not
`be necessary. Thus the current flowing through the OLED
`element is programmed to the desired level, i.e. a Scaled
`values responsive to data current I. The ratio of the width of
`transistor N2 to that of transistor N1 establishes the ratio of
`programming current I to the OLED current, i.e. the Scaling
`factor. The column convergence time can be improved by
`increasing this ratio, thus increasing the programming cur
`rent.
`0027. It is noted that one end of the respective control
`lable conduction paths of transistors N3 and N4 of circuit
`100 are connected together for receiving data Signal current
`I. When transistors N3 and N4 are enabled, each is capable
`of conducting all or part of data Signal current I, however, at
`or before the end of the line time all or substantially all of
`data signal current I flows through transistors N4 and N1.
`Preferably, this current reaches a Substantially Steady State
`condition, and the Scaled current that flows in the element
`OLED responsive to data Signal current I also reaches a
`Substantially steady State condition, e.g., at a value that is
`Substantially the desired Scaled value of data line current I.
`0028. At the end of the select interval during which
`transistors N3, N4 are enabled by the select line S being
`high, the current through the OLED element drops by the
`amount I of the data current as transistor N1 is turned off by
`the Select line S becoming low, and the Voltage acroSS the
`OLED also decreases somewhat. Preferably, the capacitor C,
`together with the gate-to-Source capacitance of transistors
`N1 and N2, is Sufficiently large So that the Voltage change
`across the OLED after the end of the select interval will not
`Substantially change the gate-to-Source Voltage acroSS tran
`Sistor N2, So its current will remain Substantially the same
`until the next Select interval.
`0029) A pixel circuit 100 for an OLED element may
`comprise an OLED element and first and Second transistors
`N3, N4 of a first polarity. Each of the first and second
`transistors N3, N4 has a controllable conduction path and a
`control electrode for controlling the conduction of the con
`trollable conduction path. One end of the controllable con
`duction paths of the first and second transistors N3, N4 are
`connected together for receiving a data Signal current I and
`the control electrodes of the first and second transistors N3,
`N4 are connected to each other for receiving a Select Signal
`for being enabled thereby. Third and fourth transistors N1,
`N2 each have a controllable conduction path and a control
`electrode for controlling the conduction of the controllable
`conduction path, and at least one of the third and fourth
`
`transistors N1, N2 exhibits a capacitance between its control
`electrode and its conduction path. One end of the control
`lable conduction paths of the third and fourth transistors N1,
`N2 are connected together and to an OLED element. The
`control electrodes of the third and fourth transistors N1, N2
`are connected to each other and to the other end of the
`controllable conduction path of the first transistor N3 and the
`other end of the controllable conduction path of the third
`transistor N1 is connected to the other end of the controllable
`conduction path of the Second transistor N4. As a result, a
`current is established in the OLED element is responsive to
`the data Signal current I when the first and Second transistors
`N3, N4 are enabled by the select signal.
`0030 Pixel circuit 100 may further comprise a capaci
`tance C coupled between the one end of the controllable
`conduction path of the third transistor N1 and the control
`electrode thereof. The third and fourth transistors N1, N2
`may be of the first polarity. The one ends of the controllable
`conduction paths of the third and fourth transistors N1, N2
`may be connected to the anode of the OLED element, and
`a cathode of the OLED element and the other end of the
`controllable conduction path of the fourth transistor N2 may
`be coupled for receiving a potential Vdd therebetween.
`0031) The pixel circuit 100 may be in combination with
`a plurality of like pixel circuits 100 arranged in rows and
`columns to define a display having a plurality of OLED pixel
`elements, and row conductors may be associated with pixel
`circuits 100 in each row of the display and column conduc
`tors associated with pixel circuits in each column of the
`display. Therein, the column conductors may apply the data
`Signal current I and the row conductors may apply the Select
`Signal.
`0032. One or more pixel circuits 100 may be embodied,
`for example, in an amorphous-Silicon circuit, in a poly
`Silicon circuit, or in a Single-crystal Silicon circuit.
`0033) Although the pixel circuit 100 illustrated in FIG.2
`would likely be Subject to unpredictable matching between
`the two transistors N1, N2 in the current mirror if imple
`mented in polysilicon technology, if implemented in amor
`phous Silicon (a-Si) technology the matching between these
`two transistors N1, N2 is expected to be better, because a-Si
`does not have a grain Structure as does polysilicon. How
`ever, the AMOLED pixel circuit 100' illustrated in FIG. 3
`avoids this transistor matching problem entirely by using the
`Same transistor P1 for current-programming and for driving
`the OLED.
`0034 FIG. 3 is an electrical circuit schematic diagram of
`an example embodiment of a pixel circuit 100'. In pixel
`circuit 100' the select line S is pulsed high in order to
`program the current to element OLED provided by pixel
`circuit 100'. When the select line S is high, n-channel
`transistors N1 and N2 turn on, and p-channel transistor P2
`turns off. A programming current I is drawn from the data
`line by the column drive circuit (not shown), and this current
`flows from p-channel transistor P1 to the data line via
`transistor N2, once Steady State Voltages are reached on the
`column data line and in the pixel element OLED. This sets
`a gate-to-Source Voltage on transistor P1 that corresponds to
`the programming current I flowing in the data line.
`0035. At the end of the line time the select line S signal
`returns low, turning transistorS N1 and N2 off, and turning
`
`LG Display Co., Ltd.
`Exhibit 1019
`Page 006
`
`

`

`US 2005/OO67971 A1
`
`Mar. 31, 2005
`
`transistor P2 on, thereby allowing the programmed current
`I to flow in the OLED. A capacitor C is included in pixel
`circuit 100' to help store the voltage on the gate of transistor
`P1. Polysilicon transistors such as transistor P1 typically
`have a relatively Small gate-to-Source capacitance, and So a
`capacitor C will be typically be needed.
`0036) While pixel circuit 100' deals well with the current
`mirror matching problem, e.g., by utilizing transistor P1 to
`both establish the appropriate gate-to-Source Voltage and to
`conduct the programming current I and the programmed
`current, Slow column charging might be a problem under
`certain conditions. Pixel circuit 100' cannot deal with this
`problem by using a programming current I that is larger than
`the OLED current because the same transistor P1 is used for
`programming and for driving the OLED element. However,
`even though the programming current I must be the same as
`the OLED drive current, the Voltage Swing required on the
`column, i.e. on the data line conductor, can be reduced,
`which allows the column convergence to the final current
`value I to be sped up. By increasing the width of the
`conduction channel of transistor P1 the Voltage Swing can be
`made very Small, and So the column can be charged more
`quickly.
`0037. It is noted that one end of the respective control
`lable conduction paths of transistors N1 and N2 of circuit
`100' are connected together for receiving data Signal current
`I. When transistors N1 and N2 are enabled, each is capable
`of conducting all or part of data signal current I, and
`transistor P2 is not enabled, however, at or before the end of
`the line time all or Substantially all of data Signal current I
`flows through transistors N2 and P1. Preferably, this current
`reaches a Substantially Steady State condition, and the cur
`rent that flows in transistors P1, P2 and in the element OLED
`responsive to data Signal current I when transistorS N1 and
`N2 are not enabled and transistor P2 is enabled also reaches
`a Substantially steady State condition, e.g., at a value that is
`substantially the value of data line current I.
`0.038 A pixel circuit for an OLED element comprises
`first and second transistors N1, N2 of a first polarity, each of
`the first and Second transistors having a controllable con
`duction path and a control electrode for controlling the
`conduction of the controllable conduction path. One end of
`the controllable conduction paths of the first and Second
`transistors N1, N2 are connected together for receiving a
`data Signal current I, and the control electrodes of the first
`and Second transistors N1, N2 are connected to each other
`for receiving a Select Signal for being enabled thereby. Third
`and fourth transistors, P1, P2 each have a controllable
`conduction path and a control electrode for controlling the
`conduction of the controllable conduction path, and at least
`the third transistor P1 exhibits a capacitance C between its
`control electrode and its conduction path. One end of the
`controllable conduction paths of the third and fourth tran
`sistors P1, P2 are connected together and to the other end of
`the controllable conduction path of the second transistor N2,
`The control electrode of the third transistor P1 is connected
`to the other end of the controllable conduction path of the
`first transistor N1 and the control electrode of the fourth
`transistor P2 is connected to the control electrodes of the first
`and Second transistors N1, N2 for receiving the Select Signal
`for being enabled thereby. The other end of the controllable
`conduction path of the fourth transistor P2 is connected to
`the OLED element. As a result, a current is established in the
`
`OLED element responsive to the data signal current I when
`the first, second and third transistors N1, N2, P1 are enabled
`by the Select Signal.
`0039) Pixel circuit 100' may further comprise a capaci
`tance C coupled between the other end of the controllable
`conduction path of the third transistor P1 and the control
`electrode thereof. The third and fourth transistors P1, P2
`may be of a Second polarity opposite to the first polarity. The
`other end of the controllable conduction path of the fourth
`transistor P2 may be connected to an anode of the OLED
`element, and a cathode of the OLED element and the other
`end of the controllable conduction path of the third transistor
`P1 may be coupled for receiving a potential Vdd therebe
`tWeen.
`0040. A plurality of like pixel circuits 100' may be
`arranged in rows and columns to define a display having a
`plurality of OLED pixel elements. Row conductors may be
`associated with pixel circuits 100' in each row of the display
`and column conductors may be associated with pixel circuits
`100' in each column of the display. The column conductors
`may apply the data Signal current I and the row conductors
`may apply the Select Signal.
`0041) One or more pixel circuits 100' may be embodied
`in a poly-Silicon circuit or in a Single-crystal Silicon circuit.
`0042 FIG. 4 is an electrical circuit schematic diagram of
`an example embodiment of a pixel circuit 100". Circuit 100"
`differs from circuit 100' in that in circuit 100" the side of
`n-channel transistor N2 that was connected to the data line
`in circuit 100' is connected to the pixel side of n-channel
`transistor N1. Otherwise, circuit 100" is similar to circuit
`100' and operates in similar manner to circuit 100" as
`described above.
`0043. This arrangement has an advantage in that the total
`column capacitance is lower than that of circuit 100' which
`tends to Speed up pixel convergence to the final value,
`however, the charging current for the gate capacitance of
`p-channel transistor P1, which is drawn from data line
`current I, must flow through transistor N1 as well as through
`transistor N2, which tends to Slow pixel convergence.
`0044) When transistors N1 and N2 of circuit 100" are
`enabled, each is capable of conducting all or part of data
`Signal current I, and transistor P2 is not enabled, however, at
`or before the end of the line time all or substantially all of
`data signal current I flows through transistors N2 and P1.
`Preferably, this current reaches a Substantially Steady State
`condition, so that the current that flows in transistors P1, P2
`and the element OLED responsive to data Signal current I
`when transistors N1, N2 are not enabled and transistor P2 is
`enabled also reaches a Substantially steady State condition,
`e.g., at a value that is Substantially the desired value of data
`line current I.
`0045) A pixel circuit 100" for an OLED element com
`prises first and second transistors N1, N2 of a first polarity,
`each of the first and second transistors N1, N2 having a
`controllable conduction path and a control electrode for
`controlling the conduction of the controllable conduction
`path. One end of the controllable conduction path of the first
`transistor N1 is connected for receiving a data Signal current
`I and the other end of the controllable conduction path of the
`first transistor N1 is connected to one end of the controllable
`conduction path of the second transistor N2. The control
`
`LG Display Co., Ltd.
`Exhibit 1019
`Page 007
`
`

`

`US 2005/OO67971 A1
`
`Mar. 31, 2005
`
`electrodes of the first and second transistors N1, N2 are
`connected to each other for receiving a Select Signal for
`being enabled thereby. Third and fourth transistors P1, P2
`each have a controllable conduction path and a control
`electrode for controlling the conduction of the controllable
`conduction path, and at least the third transistor P1 exhibits
`a capacitance C between its control electrode and its con
`duction path. One end of the controllable conduction paths
`of the third and fourth transistors P1, P2 are connected
`together and to the other end of the controllable conduction
`path of the second transistor N2. The control electrode of the
`third transistor P1 is connected to the other end of the
`controllable conduction path of the first transistor N1. The
`control electrode of the fourth transistor P2 is connected to
`the control electrodes of the first and second transistors N1,
`N2 for receiving the Select signal for being enabled thereby,
`and the other end of the controllable conduction path of the
`fourth transistor P2 is connected to the OLED element. As
`a result, a current is established in the OLED element
`responsive to the data Signal current I when the first, Second
`and third transistors N1, N2, P1 are enabled by the select
`Signal.
`0046) The pixel circuit 100" may further comprise a
`capacitance C coupled between the other end of the con
`trollable conduction path of the third transistor P1 and the
`control electrode thereof. In pixel circuit 100" third and
`fourth transistors P1, P2 may be of a second polarity
`opposite to the first polarity. Further, the other end of the
`controllable conduction paths of the fourth transistor P2 may
`be connected to an anode of the OLED element, and a
`cathode of the OLED element and the other end of the
`controllable conduction path of the third transistor P1 may
`be coupled for receiving a potential Vdd therebetween.
`0047. A plurality of like pixel circuits 100" may be
`arranged in rows and columns to define a display having a
`plurality of OLED pixel elements. Row conductors may be
`associated with the pixel circuits 100" in