(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/00994.12 A1
`Kasai
`(43) Pub. Date:
`May 12, 2005
`
`US 2005.0099.412A1
`
`(54) PIXEL CIRCUIT, METHOD OF DRIVING
`THE SAME, AND ELECTRONIC APPARATUS
`(75) Inventor: Toshiyuki Kasai, Okaya-shi (JP)
`Correspondence Address:
`OLIFF & BERRIDGE, PLC
`P.O. BOX 19928
`ALEXANDRIA, VA 22320 (US)
`(73) Assignee: Seiko Epson Corporation, Tokyo (JP)
`(21) Appl. No.:
`10/930,947
`(22) Filed:
`Sep. 1, 2004
`(30)
`Foreign Application Priority Data
`
`Nov. 11, 2003 (JP)...................................... 2003-381,271
`
`Publication Classification
`
`(51) Int. Cl. .................................................... G09G 5/00
`
`(52) U.S. Cl. ........................... 345/204; 34.5/694; 34.5/698
`
`(57)
`
`ABSTRACT
`
`To control variation in a driving current depending on Vith
`in a current program mode pixel circuit. In a State in which
`a variable current Source 4a and a transistor T3 are electri
`cally isolated from each other, a gate Voltage of the diode
`connected transistor T3 is set to an offset voltage (Vdd-Vth)
`according to a threshold Voltage Vth thereof. Next, in a State
`in which the variable current Source 4a and the transistor T3
`are electrically connected to each other, data based on the
`offset Voltage and according to a product of a data current
`Idata and a Supply time thereof are written in a capacitor C1
`connected to a gate of the transistor T3. And then, a driving
`current according to data Stored in the capacitor C1 is
`generated by means of the transistor T3, whereby brightness
`of an organic EL element OLED is set.
`
`5
`
`
`
`CONTROL
`CIRCUIT
`
`
`
`COLUMN
`DIRECTION
`
`ROW
`DRECTION
`
`3 c
`Z
`2
`Z
`G
`
`Z
`t
`U
`20
`s
`
`O
`O
`c
`9.
`al
`
`DATA LINE DRIVING CIRCUIT
`
`2
`
`8
`
`4.
`Xm 6
`
`
`
`LG Display Co., Ltd.
`Exhibit 1022
`LG Display v. Solas
`IPR2020-01055
`
`Ex. 1022-001
`
`

`

`Patent Application Publication May 12, 2005 Sheet 1 of 14
`
`US 2005/00994.12 A1
`
`| | | | | | | | | | | | | | | | | | | | | | | | | |
`
`ŽIVOT, L?
`
`^_
`
`9 Uu X
`
`H—---
`
`• ! - - - -Z X
`
`{"+": ! NWT TOO
`
`G
`
`Z Å
`
`SCANNING LINE DRIVING CIRCUIT
`
`Ex. 1022-002
`
`

`

`Patent Application Publication May 12, 2005 Sheet 2 of 14
`
`US 2005/00994.12 A1
`
`
`
`SEL2
`
`t 3
`
`Ex. 1022-003
`
`

`

`Patent Application Publication May 12, 2005 Sheet 3 of 14
`
`US 2005/00994.12 A1
`
`= Vodd-Vth
`Vg
`
`Wodd
`
`3
`
`FG4A
`
`
`
`Vdd
`
`V did
`
`vg = Vodd-Vth - A V
`R Ido to At
`AW
`C
`
`ldoto
`
`FIG.4B
`
`ly
`C 1 -
`
`OLED
`
`Vcc
`
`-
`Ioled= 2 B
`
`dotor A !) 2
`C
`
`VSS
`
`FIG.4C
`
`Ex. 1022-004
`
`

`

`Patent Application Publication May 12, 2005 Sheet 4 of 14
`
`US 2005/00994.12 A1
`
`FIG.5
`
`
`
`
`
`SWS
`
`VOLTAGE
`CHANGING
`CIRCUIT
`
`Ex. 1022-005
`
`

`

`Patent Application Publication May 12, 2005 Sheet 5 of 14
`
`US 2005/00994.12 A1
`
`FIG.6
`
`
`
`VARIABLE CURRENT
`
`i-AVp
`
`(
`
`* ZXenouiriXZ.
`
`it 0 t 1
`
`t 1"
`
`t 2
`
`t 3
`
`t
`
`Ex. 1022-006
`
`

`

`Patent Application Publication May 12, 2005 Sheet 6 of 14
`
`US 2005/00994.12 A1
`
`FIG.7
`
`
`
`SEL1
`
`SWS1
`
`SWS2
`
`CIRCUIT
`
`Ex. 1022-007
`
`

`

`Patent Application Publication May 12, 2005 Sheet 7 of 14
`
`US 2005/00994.12 A1
`
`
`
`"- || –|------- - - - - - - - - - - - - - - - - ©N
`
`*:|--~~~|~~~Z
`
`t
`
`FG.8
`
`SEL1
`
`SEL2
`
`SWS1
`
`SWS2
`
`****
`
`FIG.9
`
`
`
`SELO
`
`SELib
`
`Ex. 1022-008
`
`

`

`Patent Application Publication May 12, 2005 Sheet 8 of 14
`
`US 2005/00994.12 A1
`
`1 F
`
`SEL1 c.
`
`SEL2
`
`t 2
`
`t 3
`
`Ex. 1022-009
`
`

`

`Patent Application Publication May 12, 2005 Sheet 9 of 14
`
`US 2005/00994.12 A1
`
`
`
`T3
`
`OLED
`
`VSS
`
`Ex. 1022-010
`
`

`

`Patent Application Publication May 12, 2005 Sheet 10 of 14
`
`US 2005/00994.12 A1
`
`
`
`X
`
`
`
`
`
`X
`
`
`
`4a /
`
`Vdd
`
`T3
`
`OLED
`
`VSS
`
`Vdd
`
`T3
`
`OLED
`
`WSS
`
`Vdd iya
`C 1
`
`Vg=Vodd-With
`FIG.13A
`
`Vdd live
`- C1
`
`vg = Wald-Vth - AV
`AV = ldoto. At
`C
`
`FIG.13B
`
`Vcc live
`C
`
`Vodd
`
`
`
`T3
`
`-l
`Ioleda 2 B
`
`Idol to al) 2
`C
`
`OLED
`
`VSS
`
`FIG.13C
`
`Ex. 1022-011
`
`

`

`Patent Application Publication May 12, 2005 Sheet 11 of 14
`
`US 2005/00994.12 A1
`
`FIG.14
`
`
`
`Ex. 1022-012
`
`

`

`Patent Application Publication May 12, 2005 Sheet 12 of 14
`
`US 2005/00994.12 A1
`
`FIG.15
`
`F
`
`SEL1
`
`SEL2
`
`SWS
`
`t 0
`
`t 1
`
`t 2
`
`t
`
`t 3
`
`Ex. 1022-013
`
`

`

`Patent Application Publication May 12, 2005 Sheet 13 of 14
`
`US 2005/00994.12 A1
`
`T3
`
`C1
`
`vs=v)
`
`OLED
`
`
`
`Vg=V+ Vih-- AV
`Idioto At
`A V= --
`
`VS-V - AV
`
`FIG.16B
`
`Vdd
`
`C1
`
`2
`
`C
`
`2
`
`OLED
`
`VSS
`
`FIG.16C
`
`Ex. 1022-014
`
`

`

`Patent Application Publication May 12, 2005 Sheet 14 of 14
`
`US 2005/00994.12 A1
`
`
`
`D
`
`FIG.17
`
`ROW
`
`
`
`DATA
`
`VCO
`
`Ex. 1022-015
`
`

`

`US 2005/00994.12 A1
`
`May 12, 2005
`
`PIXEL CIRCUIT, METHOD OF DRIVING THE
`SAME, AND ELECTRONIC APPARATUS
`
`BACKGROUND OF THE INVENTION
`0001) 1. Field of Invention
`0002 The present invention relates to a pixel circuit, a
`method of driving the Same, and electronic apparatus, and
`more specifically, it relates to a method of compensating Vith
`in a current-programmed method.
`0003 2. Description of Related Art
`0004 Recently, displays using an organic electrolumi
`nescent (EL) element draw attention. The organic EL ele
`ment is one of current-driven type elements in which the
`brightness is Set according to a driving current flowing
`therethrough. A data Supplying method to pixels using the
`organic EL element includes a Voltage-programmed mode in
`which Voltage-based data is Supplied to data lines and a
`current-programmed mode in which current-based data is
`Supplied to the data lines. In the Voltage-programmed mode,
`a problem occurs that variation in a driving current depend
`ing on a threshold voltage (hereinafter, referred to as 'Vth)
`of a driving transistor may be caused, but conventionally, the
`Solution is Suggested.
`0005 FIG. 17 is a diagram of a conventional voltage
`programmed mode pixel circuit. The pixel circuit has an
`organic EL element OLED, a capacitor C1 and three of
`n-channel type transistors T1 through T3, in which the
`capacitor C1 is provided between a gate and a Source of the
`transistor T3. The pixel circuit operates as the following
`processes by means of a Swing of a Voltage Vca of an
`opposing electrode. First, if the transistor T1 is turned off
`and the transistor T2 is turned on, a cathode Voltage Vca of
`the organic EL element OLED is set to -18V. Accordingly,
`Since the transistor T3 is turned on, an anode Voltage of the
`organic EL element OLED becomes lower than -Vth (Vth
`is a threshold Voltage of the transistorT3), and then a voltage
`higher than Vth is stored in the capacitor C1. Next, if the
`transistor T2 is turned off, a gate of the transistor T3 is in a
`floating State. Subsequently, if the cathode Voltage Vca is Set
`to 10V, a reverse bias Voltage is applied to the organic EL
`element. Accordingly, the transistor T3 is turned off, and
`then a gate Voltage of the transistor T3 becomes higher than
`Vth due to a change in the cathode Voltage Vca. Subse
`quently, the transistor T3 is turned on again, and then the
`anode of the organic EL element OLED becomes almost 0
`V. In this state, if the transistor T2 is turned on and the
`cathode voltage Vca is set to 0 V, the anode voltage of the
`organic EL element becomes Sufficiently low due to a
`capacitive coupling to be settled to -Vth, and Vth is Stored
`in the capacitor C1. Next, if the transistor T1 is turned on and
`the transistor T2 is turned off, a data Voltage defining
`grayScale level of a pixel is Supplied to the pixel circuit. If
`a Self-capacitance of the organic EL element OLED is Set to
`be Sufficiently larger than that of the capacitor C1, the anode
`Voltage of the organic EL element is maintained almost to
`-Vth when the cathode voltage Vca is 0 V, and in the
`capacitor C1 a voltage of Vith--Vdata is stored. And then, the
`transistor T1 and T2 are turned off together, and the cathode
`Voltage Vca is set to -18 V. At this time, Since the Voltage
`of Vith--Vdata is stored in the capacitor C1, a channel current
`(driving current) proportional to the voltage of Vith--Vdata
`flows through a channel of the transistor T3, whereby the
`
`organic EL element OLED is emitted. In such manner, if Vth
`is previously Stored in the capacitor C1 and data is written
`based on Vith, variation in Vth of the transistor T3 can be
`compensated, and further a driving current independent of
`Vth can be generated.
`
`SUMMARY OF THE INVENTION
`0006 Meanwhile, the current-programmed mode, unlike
`the Voltage-programmed mode, is generally advantageous in
`that an uniform driving current independent of Vth of a
`driving transistor can be generated. For this reason, the
`current-programmed mode is widely adopted. However, the
`current-programmed mode is made on the assumption that
`current-based data (current data) is written completely
`within a predetermined data writing period. Accordingly, if
`the data writing is not completed within the predetermined
`period, that is, the data writing is lacking, when the same
`grayScale is displayed, the driving current which must be
`primarily the same for every driving transistor may be
`differentiated depending on variation in Vith. This may be
`generated in a large-sized display in which a parasitic
`capacitance of a data line is very large and a high-definition
`display in which the number of Scanning lines is numerous
`and a data writing period is not Sufficiently Secured. Further,
`in the case that a current to be programmed in a pixel is very
`Small (when using high efficient EL element or phosphores
`cence material, the above problem may also occur. Besides,
`in the case that a Security of a contrast ratio is preceded, for
`design convenience, lack writing in a low-resolution gray
`Scale region may be tolerated at a certain degree, and the
`current to be programmed may be set in a wider range.
`0007. The present invention has been made in consider
`ation of the above problems, and its object is to Suppress
`variation in a driving current depending on Vth in a current
`programmed mode pixel circuit.
`0008. In order to solve the above problems, there is
`provided a method of driving a pixel circuit according to a
`first aspect of the present invention. The driving method
`comprises: a first Step of Setting a gate Voltage of a diode
`connected first transistor to an offset Voltage according to a
`threshold Voltage of the first transistor, in a State in which a
`variable current Source variably generating a data current is
`electrically isolated from the first transistor, a Second Step of
`Writing, in a capacitor connected to a gate of the diode
`connected first transistor, data Set based on the offset Voltage
`and according to a product of the data current Supplied from
`the variable current Source Via data lines and a Supply time
`thereof, in a State in which the variable current Source and
`the first transistor are electrically connected to each other,
`and a third Step of generating a driving current according to
`the data Stored in the capacitor by a Second transistor whose
`gate is connected to the capacitor to Set brightness of an
`electro-optical device.
`0009. In the first aspect, a transistor rolls as both the first
`transistor and the Second transistor. Further, the first tran
`Sistor and the Second transistor may constitute a current
`mirror.
`0010 Further, in the first aspect, preferably, the first step
`comprises a Step of turning off a Switching element provided
`between the variable current Source and the first transistor,
`and the Second Step comprises a step of turning on the
`Switching element. Further, in the first aspect, the driving
`
`Ex. 1022-016
`
`

`

`US 2005/00994.12 A1
`
`May 12, 2005
`
`method may further comprise a fourth Step of regulating the
`offset Voltage Set in the first Step, by variably controlling the
`terminal Voltage of a capacitor that another terminal is
`coupled to the data lines.
`0011. In this case, the amount of change of the terminal
`Voltage of a capacitor in the fourth Step is Set according to
`a grayScale level to be displayed.
`0012 Further, the driving method may comprise, prior to
`Setting the offset Voltage in the first Step, a fifth Step of
`Supplying, to the data lines, a predetermined Voltage having
`a Voltage level that turns on the first transistor.
`0013 More, there is provided a pixel circuit according to
`a Second aspect of the present invention. The pixel circuit
`comprises: a first transistor normally or Selectively diode
`connected through a control of a Switching transistor, for
`generating data according to data current Supplied from a
`variable current Source via the data lines, a capacitor con
`nected to a gate of the first transistor, in which data gener
`ated by the first transistor is written, a Second transistor,
`whose gate is connected to the capacitor, for generating a
`driving current according to data Stored in the capacitor, and
`an electro-optical element in which the brightness is Set
`according to the driving current generated by the Second
`transistor. Here, the first transistor Sets its gate Voltage to an
`offset Voltage according to its threshold Voltage in a State
`which the first transistor is electrically isolated from the
`variable current Source. Further, in a state which the first
`transistor is electrically connected to the variable current
`Source, the first transistor writes data Set based on the offset
`Voltage and according to a product of the data current
`Supplied from the variable current Source and a Supply time
`thereof, in the capacitor.
`0.014.
`In the second aspect, a transistor may rolls as both
`the first transistor and the second transistor. Further, the first
`transistor and the Second transistor may constitute a current
`mirror.
`Further, in the second aspect, the pixel circuit may
`0.015
`further comprises a Switching circuit for electrically isolat
`ing between the variable current Source and the data line for
`a period during which the gate Voltage is Set to the offset
`Voltage, and electrically connecting between the variable
`current Source and the data line for a period during which the
`data is written in the capacitor. Further, the pixel circuit may
`further comprise a precharge regulation circuit that regulate
`the offset voltage by variably controlling the terminal volt
`age of a capacitor that another terminal is coupled to the data
`lines. In this case, the precharge regulation circuit preferably
`controls the amount of change of the terminal Voltage of a
`capacitor according to a grayScale level to be displayed. In
`addition, the pixel circuit may further comprise a precharge
`acceleration circuit for Supplying, to the data lines, a pre
`determined Voltage having a Voltage level that turns on the
`first transistor, prior to a period during which the gate
`Voltage is Set to the offset Voltage.
`0016. More, there is provided an electronic apparatus
`according to a third aspect of the present invention. The
`electronic apparatus comprises an electro-optical device
`having a pixel circuit according to the Second aspect of the
`present invention.
`0.017. In the present invention, the gate voltage of the first
`transistor is previously set to the offset Voltage, and the data
`
`Writing to the capacitor is made in the current-programmed
`mode. Data to be written is set based on the offset voltage
`previously Set and according to the product of the data
`current and the Supply time thereof. Thus, when the driving
`current is generated based on data Stored in the capacitor, it
`is possible to reduce a dependency on Vth of the driving
`current. As a result, even when data writing is lacking, it is
`possible to generate an uniform driving current, and thus it
`is possible to Set the electro-optical device to have a desir
`able brightness.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0018 FIG. 1 is a block diagram showing a configuration
`of an electro-optical device;
`0019 FIG. 2 is a diagram of a pixel circuit according to
`a first embodiment;
`0020 FIG. 3 is a timing chart of operation according to
`the first embodiment;
`0021
`FIG. 4 is an explanatory view of the operation
`according to the first embodiment;
`0022 FIG. 5 is a diagram of a pixel circuit according to
`a Second embodiment;
`0023 FIG. 6 is a timing chart of operation according to
`the Second embodiment;
`0024 FIG. 7 is a diagram of a pixel circuit according to
`a third embodiment;
`0025 FIG. 8 is a timing chart of operation according to
`the third embodiment;
`0026 FIG. 9 is a diagram of a pixel circuit according to
`a fourth embodiment;
`0027 FIG. 10 is a timing chart of operation according to
`the fourth embodiment;
`0028 FIG. 11 is a diagram of a pixel circuit according to
`a fifth embodiment;
`0029 FIG. 12 is a timing chart of operation according to
`the fifth embodiment;
`0030 FIG. 13 is an explanatory view of the operation
`according to the fifth embodiment;
`0031
`FIG. 14 is a diagram of a pixel circuit according to
`a sixth embodiment;
`0032 FIG. 15 is a timing chart of operation according to
`the sixth embodiment;
`0033 FIG. 16 is an explanatory view of the operation
`according to the Sixth embodiment,
`FIG. 17 is a diagram of a conventional pixel
`0034)
`circuit.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`First Embodiment
`0035 FIG. 1 is a block diagram showing a configuration
`of an electro-optical device according to the present embodi
`ment. A display unit 1 is, for example, an active matrix type
`display panel in which the electro-optical device is driven by
`
`Ex. 1022-017
`
`

`

`US 2005/00994.12 A1
`
`May 12, 2005
`
`a TFT (thin film transistor). In the display unit 1, m dots by
`in lines of a group of pixels are arranged in a matrix (in a
`two-dimensional plan view). In the display unit 1, a group of
`Scanning lines Y1 through Yn each extending in a horizontal
`direction and a group of data lines X1 through Xm each
`extending in a vertical direction are provided, and pixels 2
`are arranged in correspondence with interSections of the
`Scanning lines and the data lines. Moreover, while in a
`monochromatic panel, one pixel corresponds to one pixel
`circuit described below, when one pixel comprises three R,
`G,B Sub-pixels like a color panel, one Sub-pixel corresponds
`to one pixel circuit. Further, as regards the configuration of
`the pixel circuit described below, one Scanning line may
`represent a respective one of Scanning lines (FIG. 11) or
`may represent a set of plural scanning lines (FIGS. 2, 5, 7,
`9 and 14).
`0036) A control circuit 5 synchronously controls a scan
`ning line driving circuit 3., a data line driving circuit 4 and
`a Switching circuit 6 based on a vertical Synchronizing Signal
`Vs, a horizontal Synchronizing Signal HS, a dot clock signal
`DCLK, grayScale data D, and So on, which are inputted from
`preceding devices. Under the Synchronous control, the Scan
`ning line driving circuit 3, the data line driving circuit 4 and
`the Switching circuit 6 cooperate with each other to control
`a display on the display unit 1.
`0037. The scanning line driving circuit 3 mainly com
`prises shift registers, output circuits, and So on, and outputs
`a scanning signal SEL to the scanning lines Y1 through Yn
`to perform a line Sequential Scanning. The Scanning Signal
`SEL is a two-level signal of a high potential level (herein
`after, referred to as “H level) and a low potential level
`(hereinafter, referred to as “L level). A Scanning line cor
`responding to a row of pixels to which data is written is Set
`to H level and other scanning lines are set to L level. The
`Scanning line driving circuit 3 performs the line Sequential
`Scanning for Selecting each Scanning line Y in a predeter
`mined order (in general, from top to bottom) for every
`period (1F) in which images of one frame are displayed.
`Meanwhile, the data line driving circuit 4 has mainly shift
`registers, line latch circuits, output circuits, and So on. In the
`present embodiment, if the current-programmed mode is
`adopted, the data line driving circuit 4 comprises a variable
`current Source (4a in FIG. 2) for variably generating a data
`current Idata based on grayScale data defining grayScale
`level to be displayed in the pixel 2. In one horizontal
`Scanning period (1H) corresponding to the period in which
`one Scanning line is Selected, the data line driving circuit 4
`Simultaneously outputs the data current Idata to a row of
`pixels to which current data is written, and at the same time,
`latches in a point Sequential manner data relevant to a row
`of pixels to be written in next one horizontal Scanning period
`(1H). In any horizontal Scanning period (1H), m data cor
`responding to the number of data lines X are Sequentially
`latched. And then, in next one horizontal Scanning period
`(1H), the latched m data are converted into current data Idata
`by means of the variable current Source, and are Simulta
`neously output to the corresponding data lines. Further, the
`Switching circuit 6 comprising m Switching elements, more
`Specifically, m Switching transistorST6 corresponding to the
`data lines X1 through Xm. The transistors T6 provided by
`one for every data line are, for example, n-channel type
`transistors and are commonly controlled by a single Switch
`ing signal SWS outputted from the control circuit 5. This
`
`control is performed in Synchronization with the line
`Sequential Scanning by means of the Scanning line driving
`circuit 3.
`0038 FIG. 2 is a diagram of a current-programmed mode
`pixel circuit according to the present embodiment. One pixel
`2 comprises an organic EL element OLED, four transistors
`T1 through T4 as an active element, and a capacitor C1
`Storing data. The organic EL element represented as a diode
`is a typical current-driven type element in which the bright
`neSS is Set by a current Ioled flowing therethrough. In this
`configuration example, the n-channel type transistorST1, T2
`and T4 and the p-channel type transistor T3 are used, but it
`is just an example. Thus, the channel types of the respective
`transistors T1 through T4 may be set differently from the
`above channel type combination. Further, between the data
`line X connected to the pixel 2 and the variable current
`Source 4a constituting a portion of the data line driving
`circuit 4, a Single Switching transistor T6 provided by one for
`every data line is connected. In the present Specification, as
`regards a three-terminal type transistor having a Source, a
`drain and a gate, one of the Source and drain is referred to
`as “one terminal and the other is referred as “the other
`terminal.
`0039. A gate of the Switching transistor T1 is connected
`to one Scanning line to which a first Scanning Signal SEL1
`is Supplied, and one terminal of the Switching transistor T1
`is connected to one data line X to which the data current
`Idata is Supplied. The other terminal of the Switching tran
`Sistor T1 is commonly connected to one terminal of the
`Switching transistor T2, one terminal of the driving transistor
`T3 and one terminal of the driving transistor T4. A gate of
`the Switching transistor T2 is connected to the Scanning line
`to which the first Scanning Signal SEL1 is Supplied, like the
`first Switching transistor T1. The other terminal of the
`Switching transistor T2 is connected to a node Ng to which
`one electrode of the capacitor C1 and a gate of the driving
`transistor T3 are commonly connected. To the other elec
`trode of the capacitor C1 and the other terminal of the
`driving transistor T3, a Vdd terminal is connected, through
`which a power Source Voltage is constantly Supplied. The
`Switching transistor 4 is provided between one terminal of
`the driving transistor T3 of which a gate is Supplied with a
`Second Scanning Signal SEL2 and an anode of the organic EL
`element OLED. A cathode of the organic EL element OLED
`is connected to a VSS terminal to which a reference Voltage
`Vss lower than the power source voltage Vdd is constantly
`Supplied. Moreover, in this configuration example, the driv
`ing transistor T3 functions a programming element for
`wiring data according to the data current Idata in the
`capacitor C1, as well as a driving element for generating the
`driving current Ioled primarily.
`0040 FIG. 3 is a timing chart of operation of the pixel
`circuit shown in FIG. 2. In a period to to t3 corresponding
`to one frame period (1F) described above, consecutive
`processes are generally divided into a precharge proceSS in
`an initial period to to t1, a data writing process in a
`Subsequent period t1 to t2, and a driving process in a last
`period t2 to t3.
`0041
`First, in the precharge period to to t1, a precharge
`to be completed within the pixel 2 is performed, and by
`means of this precharge, a Vth compensation of the driving
`transistor T3 is performed. More specifically, the level of the
`
`Ex. 1022-018
`
`

`

`US 2005/00994.12 A1
`
`May 12, 2005
`
`first Scanning Signal SEL1 becomes H level, and then the
`Switching transistors T1 and T2 are turned on together.
`Accordingly, the data line and one terminal (drain) of the
`driving transistor T3 are electrically connected to each other,
`and thus the driving transistor T3 becomes a diode-connec
`tion in which its gate and its drain are electrically connected
`to each other. In this period to to t1, since the level of the
`Switching Signal is Llevel and the Switching transistor T6 is
`turned off, the node Ng in the pixel 2 and the variable current
`Source 4a are Still electrically isolated from each other.
`Further, the level of the Second Scanning Signal SEL2
`becomes L level, and then the Switching transistor T4 is
`turned off. Accordingly, as shown in FIG. 4(a), in a State in
`which the node Ng and the variable current source 4a are
`electrically isolated from each other, the precharge of the
`capacitor C1 and the data line X is performed by means of
`the power source voltage Vdd of the Vdd terminal. By
`means of this precharge, a Voltage of the node Ng, that is, a
`gate Voltage Vg of the driving transistor T3 is Set to an offset
`voltage (Vdd-Vth), and its Voltage level is principally
`determined by means of the threshold voltage Vth of the
`driving transistor T3. In Such manner, prior to writing data,
`the voltage Vg of the node Ng is forcibly offset from a
`Voltage level depending on data written in the driving
`process of the previous one frame period (1F), to the offset
`voltage (Vdd-Vth) corresponding to a precharge level.
`Moreover, in this period to to t1, since the Switching
`transistor T4 is turned off, the organic EL element OLED
`does not emit.
`0.042
`Next, in the data writing period t1 to t2, based on
`the offset voltage (Vdd-Vth) set in the previous precharge
`period to to t1, the data is written in the capacitor C1. In this
`period t1 to t2, Since the Scanning Signals SEL1 and SEL2
`are respectively at the same level as those in the precharge
`period to to t1, the Switching transistors T1 and T2 are left
`to be turned on, and the Switching transistor T4 is left to be
`turned off. Further, in the timing til, the level of the Switching
`signal SWS rises to H level, and then the Switching transistor
`T6 which is turned off is Switched to be turned on. In Such
`manner, as shown in FIG. 4(b), the node Ng and the variable
`current Source 4a are electrically connected to each other. AS
`a result, a path of the data current Idata is formed, and the
`path is made in a Sequence of the Vdd terminal, a channel of
`the driving transistor T3 and the variable current source 4a
`(correctly speaking, channels of the Switching transistors T1
`and T6 also are included). The voltage Vg of the node Vg is
`calculated by means of the following equation 1.
`
`(Equation 1)
`AV=(Idata"At)/C
`0.043
`Here, Idata is a voltage level of the data current
`Idata generated by the variable current Source 4a, At is a time
`in the data writing period t1 to t2, that is, a Supply time of
`the data current Idata. Further, a coefficient C is a total
`capacitance relating to a driving path of the data current
`Idata including a wiring capacitance of the data line X and
`a capacitance of the capacitor C1. AS Seen from the equation
`1, the voltage Vg is changed by AV based on the offset
`voltage (Vdd-Vth), and the AV is principally specified
`according to a product of the data current Idata and its
`Supply time At. Thus, in the capacitor C1, charges according
`to the Voltage Vg are written as data. Moreover, in the period
`t1 to t2, like the previous precharge period to to t1, the
`Switching transistor T4 is left to be turned off, and thus the
`organic EL element OLED does not emit.
`
`0044) Further, in the driving period t2 to t3, the driving
`current Ioled corresponding to a channel current of the
`driving transistor T3 is Supplied to the organic EL element
`OLED, whereby the organic EL element is emitted. More
`Specifically, levels of the first Scanning Signal SEL1 and the
`Switching signal SWS fall to L level, the Switching transis
`tors T1, T2 and T6 are turned off together. Accordingly, the
`node Ng is electrically isolated from the variable current
`Source 4a. However, even after the electrical isolation, to the
`gate of the driving transistor T3, a Voltage according to data
`Stored in the capacitor C1 is continuously applied. Further,
`in Synchronization with the falling of the first Scanning
`Signal SEL1, the level of the Second Scanning Signal SEL2
`rises to H level. In the present Specification, the term
`Synchronization is used to represent a tolerable time offset
`to a margin for design as well as the same timing. In Such
`manner, as shown in FIG. 4(c), along a sequential path of
`the Vdd terminal, the channel of the driving transistor T3,
`the organic EL element OLED and the VSS terminal, the
`driving current Ioled flows. On an assumption that the
`driving transistor T3 operates in a Saturation region, the
`driving current Ioled (a channel current Isd of the driving
`transistor T3) flowing through the organic EL element
`OLED is calculated by the following equation 2. In the
`equation 2, a VSg is a voltage between the gate and the
`Source of the driving transistor T3. Further, again coefficient
`B is principally specified by a mobility it of carrier, a gate
`capacitance A, a channel width W and a channel length L of
`the driving transistor T3 (B-uAW/L).
`
`0045. Here, if the Vg calculated by the equation 1 is
`Substituted for the gate Voltage of the driving transistor T3,
`the equation 2 is transformed to the following equation 3.
`Ioled=%|B(VS-Vg-Vth)°=2|{Vdd-(Vdd-Vth-AV)-
`(Equation 3)
`Vth}*=2|BAV’-B/2(Idata 'AtiC)?
`0046. In the equation 3, it is important that the Vths are
`balanced each other during the equation transformation.
`This means that the driving current Ioled to be generated by
`the driving transistor T3 does not depend on the Vith. The
`emitting brightness of the organic EL element OLED is
`principally determined by the driving current Ioled accord
`ing to the product of the data current Idata and its Supply
`time At, and thus grayScale level of the pixel 2 is Set.
`0047. In such manner, in the present embodiment, in the
`precharge prior to the data writing, the Voltage of the node
`Ng is set to the offset voltage (Vdd-Vth) and data is written
`in the capacitor C1 based on the product of the data current
`Idata and its Supply time At. In general, variation in the Vth
`is larger than that of the At or the C, and therefore, by
`compensating the Vth, the degree of the precharge in each
`pixel 2 becomes equivalent even when characteristics of the
`driving transistor T3 in the display unit 1 are uneven. As a
`result, even in the case that the data writing is lacking as
`describe above, it is possible to SuppreSS Variation in the
`driving current depending on the Vth and thus improve
`display quality Still more.
`0048. Further, according to the present embodiment, it is
`possible to perform the precharge to be completed within the
`pixel 2, without providing an additional circuit for precharge
`outside the pixel 2. This is advantageous for Simplifying a
`configuration of the circuit or reducing the power consump
`tion.
`
`Ex. 1022-019
`
`

`

`US 2005/00994.12 A1
`
`May 12, 2005
`
`Second Embodiment
`0049. The present embodiment relates to a technique for
`regulating the offset Voltage (Vdd-Vth) corresponding to the
`precharge level according to a grayScale level to be dis
`played, based on the basic configuration of the first embodi
`ment described above. FIG. 5 is a diagram of a pixel circuit
`according to the present embodiment. The pixel circuit has
`a feature that a precharge regulation circuit 7 is added to the
`pixel circuit shown in FIG. 2, and other elements are the
`same as those of the pixel circuit of FIG. 2. Thus, the
`descriptions of like element