Microelectronics Reliability 42 (2002) 583–596
`
`www.elsevier.com/locate/microrel
`
`A review of recent MOSFET threshold voltage
`extraction methods
`A. Ortiz-Conde a,*, F.J. Garcııa Saanchez a, J.J. Liou b,1, A. Cerdeira c,
`M. Estrada c, Y. Yue d
`a Laboratorio de Electroonica del Estado Soolido (LEES), Universidad Simoon Bolııvar, Apartado Postal 89000, Caracas 1080A, Venezuela
`b Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816-2450, USA
`c Seccioon de Electroonica del Estado Soolido (SEES), Departamento de Ingenierııa Eleectrica, CINVESTAV-IPN, Avenida IPN No. 2508,
`Apartado Postal 14-740, 07300 DF, Mexico
`d Intersil Corporation, 2401 Palm Bay Road NE, Palm Bay, FL 32905, USA
`
`Received 22 December 2001
`
`Abstract
`
`The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be ex-
`tracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical
`circuits based on some of the most common methods are available to automatically and quickly measure the threshold
`voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of
`threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses
`specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics mea-
`sured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under
`saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical
`implementation of the several methods presented is illustrated and their performances are compared under the same
`challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk
`MOSFET with state-of-the-art short-channel
`length, and an experimental n-channel a-Si:H thin film MOS-
`FET. Ó 2002 Elsevier Science Ltd. All rights reserved.
`
`1. Introduction
`
`The threshold voltage (VT) is a fundamental param-
`eter for MOSFET modeling and characterization [1–6].
`This parameter, which represents the onset of significant
`drain current flow, has been given several definitions [7–
`9], but it may be essentially understood as the gate
`voltage value at which the transition between weak and
`strong inversion takes place in the MOSFET channel.
`
`There exist numerous methods to extract the value of
`threshold voltage [10–41] and various extractor circuits
`have also been proposed [42–44] to automatically mea-
`sure this parameter. Recently three books [1–3] and
`three articles [4–6] have reviewed and scrutinized dif-
`ferent available methods.
`The greater part of the procedures available to de-
`termine VT are based on the measurement of the static
`transfer drain current versus gate voltage (ID–Vg) char-
`acteristics [10–35] of a single transistor. Most of these
`ID–Vg methods use the strong inversion region [10–27],
`while only a few consider the weak inversion region [28–
`31]. Extraction is mostly done using low drain voltages
`so that the device operates in the linear region [10–33].
`However, VT extraction with the device operating in
`saturation is also frequently carried out [34,35].
`A common feature present of most VT extraction
`methods based on the ID–Vg transfer characteristics is
`0026-2714/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved.
`PII: S 0 0 2 6 - 2 7 1 4 ( 0 2 ) 0 0 0 2 7 - 6
`
`* Corresponding author. Fax: +582-9063631.
`E-mail addresses: ortizc@ieee.org (A. Ortiz-Conde),
`jli@
`ece.engr.ucf.edu (J.J. Liou), cerdeira@mail.cinvestav.mx (A.
`Cerdeira), yyue@intersil.com (Y. Yue).
`1 Also at: Department of Electronics Science and Technol-
`ogy, Huazhong University of Science and Technology, Wuhan
`430074, P.R. China.
`
`LG Display Co., Ltd.
`Exhibit 1008
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`A. Ortiz-Conde et al. / Microelectronics Reliability 42 (2002) 583–596
`
`the strong influence of the source and drain parasitic
`series resistances and the channel mobility degradation
`on the resulting value of the extracted VT. This situation
`is highly undesirable because the correct value of the
`extracted VT should not depend on parasitic components
`nor mobility degradation. In order to eliminate the in-
`fluence of these unwanted effects some methods have
`been proposed which are based on measuring capaci-
`tance as a function of voltage [36,37]. However these C–
`V methods have the disadvantage of requiring elaborate
`high-resolution equipment to measure the small capac-
`itances present in MOSFETs, particularly in very small
`geometry state-of-art devices. Other approaches to elimi-
`nate the influence of parasitic series resistances are based
`on measuring the ID–Vg transfer characteristics of vari-
`ous devices having different mask channel
`lengths
`[38,39], or on measuring several devices connected to-
`gether [40,41]. Although such multi-device approaches
`offer interesting solutions to this problem, they require
`additional work and the availability of several supple-
`mentary special devices. Another recently proposed
`method that requires repeated measurements is based on
`a proportional difference operator [26,27].
`The extraction of VT in non-crystalline MOSFETs is
`more conveniently performed using the drain current in
`saturation, considering that these devices present much
`smaller currents than single-crystalline devices. Amor-
`phous and polycrystalline thin film transistors (TFTs)
`introduce the additional difficulty that the saturation
`drain current in strong inversion is usually modeled by a
`power law with an exponent which can differ from 2
`[45,46]. Because of this behavior, using conventional VT
`extraction methods developed for single-crystal devices
`will generally produce values of VT that are unacceptable
`or at least not very accurate. Therefore the extraction
`method must be capable of extracting the value of the
`unknown power-law exponent parameter and take it
`into consideration in the extraction process. To that end,
`methods have been proposed that are specific for non-
`crystalline thin MOSFET TFTs [45,46] and thus allow
`to extract their threshold voltage correctly.
`This article will review and scrutinize the following
`existing ID–Vg methods for extracting VT in single-crystal
`MOSFETs, biased in the linear region: (1) constant-
`current (CC) method, which defines VT as the gate
`voltage corresponding to a certain predefined practical
`constant drain current [1–6,10,11]; (2) extrapolation in
`the linear region (ELR) method, which finds the gate
`voltage axis intercept of the linear extrapolation of the
`ID–Vg characteristics at its maximum first derivative
`(slope) point [1–6]; (3) transconductance linear extrap-
`olation (GMLE) method, which finds the gate voltage
`axis intercept of the linear extrapolation of the gm–Vg
`characteristics at its maximum first derivative (slope)
`point [19,20]; (4) second derivative (SD) method, which
`determines VT at the maximum of the SD of ID with
`
`respect to Vg [12]; (5) ratio method (RM), which finds the
`gate voltage axis intercept of the ratio of the drain
`current to the square root of the transconductance [13–
`18]; (6) transition method [33]; (7) integral method [32];
`(8) Corsi function method [21]; and (9) second derivative
`logarithmic (SDL) method, which determines VT at the
`minimum of the SD of logðIDÞ–Vg [31]; (10) linear co-
`factor difference operator [22] (LCDO) method, and (11)
`non-linear optimization [23,24].
`This article will also review the following two meth-
`ods to extract the VT of single-crystalline MOSFETs,
`operating in the saturation region: (1) extrapolation in
`the saturation region (ESR) method, which finds the
`gate voltage axis intercept of the linear extrapolation of
`the I 0:5
`D –Vg characteristics at its maximum first deriva-
`tive (slope) point [1,2]; and (2) G1 function extraction
`method [34,35].
`Finally, we will review and discuss some amorphous
`TFT specific procedures which have been recently pro-
`posed to extract the threshold voltage of these non-
`crystalline devices [45,46].
`
`2. Extraction from the ID–Vg curve of MOSFETs biased
`in the linear region
`
`In order to critically assess and compare the different
`linear region extraction methods reviewed here, we will
`apply them all to extract the value of the threshold
`voltage from the measured transfer characteristics of a
`state-of-the-art bulk single-crystal silicon enhancement-
`mode n-channel MOSFET with a 5 lm mask channel
`width, a 0.18 lm mask channel length, and a 32A gate
`oxide thickness. For this group of methods the device is
`biased to operate in the linear regime by applying a
`drain voltage of 10 mV. Fig. 1 presents the output
`characteristics of this device for general reference pur-
`poses.
`
`2.1. Constant-current method
`
`The CC method [1–6] evaluates the threshold voltage
`as the value of the gate voltage, Vg, corresponding to a
`given arbitrary constant drain current, ID and Vd < 100
`mV. A typical value [20] for this arbitrary constant drain
`current is ðWm=LmÞ  107, where Wm and Lm are the
`mask channel width and length, respectively. This
`method is widely used in industry because of its sim-
`plicity. The threshold voltage can be determined quickly
`with only one voltage measurement, as shown in Fig. 2.
`In spite of its simplicity, this method has the severe
`disadvantage of being totally dependent of the arbi-
`trarily chosen value of the drain current level. This is
`evident by the results in Fig. 2, where different gate
`voltages can be taken at different drain current values to
`represent the threshold voltages.
`
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`
`585
`
`fining the previously arbitrary drain current level used
`to define the threshold voltage at the drain current
`where d2ID=dV 2
`g presents a maximum. This amounts to a
`combination of the CC method and the second-deriva-
`tive method, which will be presented latter.
`
`2.2. Extrapolation in the linear region method
`
`The ELR method [1–6] is perhaps the most popu-
`lar threshold-voltage extraction method. It consists of
`finding the gate-voltage axis intercept (i.e., ID ¼ 0) of the
`linear extrapolation of the ID–Vg curve at its maximum
`first derivative (slope) point (i.e. the point of maximum
`transconductance, gm), as illustrated in Fig. 3. The value
`of VT is calculated by adding Vd=2 to the resulting gate-
`voltage axis intercept, which for the device at hand
`happens to be 0.51 V. The main drawback of this other-
`wise useful method is that the maximum slope point
`might be uncertain, because the ID–Vg characteristics can
`deviate from ideal straight line behavior at gate voltages
`even slightly above VT, due to mobility degradation ef-
`fects and to the presence of significant source and drain
`series parasitic resistances [2]. Therefore, the threshold
`voltage value extracted using this method, often referred
`to as the extrapolated VT, can be strongly influenced by
`
`Fig. 1. Measured ID–Vd output characteristics at five values of
`gate bias for the test bulk single-crystal n-channel MOSFET
`with 5 lm mask channel width and 0.18 lm mask channel
`length.
`
`Fig. 2. CC method implemented on the ID–Vg transfer charac-
`teristics of the test bulk device measured at Vd ¼ 10 mV. This
`method evaluates the threshold voltage as the value of the gate
`voltage corresponding to a given arbitrary constant drain cur-
`rent.
`
`Recently Zhou and his group have proposed [10,11]
`an improvement to the CC method. It consists on de-
`
`Fig. 3. ELR method implemented on the ID–Vg characteristics
`of the test bulk device measured at Vd ¼ 10 mV. This method
`consists of finding the gate-voltage axis intercept (i.e., ID ¼ 0) of
`the linear extrapolation of the ID–Vg curve at its maximum slope
`point.
`
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`
`parasitic series resistances and mobility degradation
`effects.
`
`maximum slope of the gm–Vg characteristics offers a
`better description of VT.
`
`2.3. Transconductance extrapolation method in the linear
`region
`
`2.4. Second-derivative method
`
`A seldom used method is the transconductance ex-
`trapolation method in the linear region (GMLE) which
`was proposed in 1998 [19,20]. This method suggests that
`the threshold voltage corresponds to the gate voltage
`axis intercept of the linear extrapolation of the gm–Vg
`characteristics at its maximum first derivative (slope)
`point. This method is based on the following arguments
`when the device is biased in the linear region. (1) In weak
`inversion, the transconductance depends exponentially
`on gate bias; (2) For strong inversion, if the series re-
`sistance and mobility degradation are negligible, the
`transconductance tends to a constant value; (3) The
`transconductance decreases slightly with gate bias due to
`the series resistance and mobility degradation; (4) In the
`transition region between weak and strong inversion, the
`transconductance depends linearly on gate bias. Fig. 4
`presents the application of this method to the gm–Vg
`characteristics producing an apparent value for VT of
`only 0.44 V. The following method also based on the
`
`The SD method [12], developed to avoid the depen-
`dence on the series resistances, determines VT as the gate
`voltage at which the derivative of the transconductance
`(i.e., dgm=dVg ¼ d2ID=dV 2
`g ) is maximum. The origin of
`this method can be understood by analyzing the fol-
`lowing ideal case of a MOSFET modeled with a simple
`level ¼ 1 SPICE model, where ID ¼ 0 for Vg < VT and ID
`is proportional to Vg for Vg > VT. Using the previous
`simplifying assumption, dID=dVg becomes a step func-
`tion, which is zero for Vg < VT and has a positive con-
`stant value for Vg > VT. Therefore, d2ID=dV 2
`g will tend to
`infinity at Vg ¼ VT. Since for a real device such simpli-
`fying assumptions are obviously not exactly true,
`d2ID=dV 2
`g will of course not become infinite, but will
`instead exhibit a maximum at Vg ¼ VT.
`this
`As Fig. 5 indicates,
`the implementation of
`method is highly sensitive to measurement error and
`noise, because the use of the SD amounts to applying a
`high-pass filter in the measurement. Notice in this figure
`that the maximum value of d2ID=dV 2
`g occurs at about
`Vg ¼ 0:54 V due to the measurement noise present;
`
`Fig. 4. Transconductance extrapolation method (GMLE) im-
`plemented on the gm ¼ dID=dVg versus Vg characteristics of the
`test bulk device measured at Vd ¼ 10 mV. This method suggests
`that the threshold voltage corresponds to the gate voltage axis
`intercept of the linear extrapolation of the gm–Vg characteristics
`at its maximum slope point.
`
`Fig. 5. SD method implemented on the plot of d2ID=dV 2
`g versus
`Vg of the test bulk device measured at Vd ¼ 10 mV. This method
`consists of finding the gate-voltage at which d2ID=dV 2
`g exhibits a
`maximum value.
`
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`
`587
`
`whereas if the noise is suppressed the maximum appears
`to be around Vg ¼ 0:50 V.
`
`2.5. Ratio method
`
`The RM [13–18], developed to avoid the dependence
`of the extracted VT value on mobility degradation and
`parasitic series resistance, proposes that the ratio of the
`drain current to the square root of the transconduc-
`tance (ID=g0:5
`m ) behaves as a linear function of gate bias,
`whose intercept with the gate-voltage axis will equal the
`threshold voltage. This method was originally published
`independently in 1988 by Jain [13] and by Ghibaudo
`[14]. Jain demonstrated that if the mobility degradation
`were negligible, the function ID=g0:5
`m would be indepen-
`dent of parasitic series resistance [13]. On the other
`hand, Ghibaudo showed that if the parasitic series re-
`sistance were negligible, the function ID=g0:5
`m would not
`depend on mobility degradation [14]. In 1995, Fikry and
`his coworkers proved [15] that the function ID=g0:5
`m is
`independent of mobility degradation, parasitic series
`resistance and velocity saturation effects. The RM was
`further improved in 2000 [18] to account for a more
`general mobility degradation model.
`Summarizing the RM developments, the drain cur-
`rent ID in the linear region can be expressed as [1–3]
`ID ¼ W
`ð
` VTÞVDS;
`lCo VGS
`Leff
`
`ð1Þ
`
`where W is the channel width, Co is the oxide capaci-
`tance per unit area, l is the effective free-carrier mobil-
`ity, and VGS and VDS are the intrinsic gate–source and
`drain–source voltages, respectively. The intrinsic volt-
`ages can be related to the external gate–source and
`drain–source voltages (Vg and Vd) by
`VGS ¼ Vg IDRD
`
`ð2Þ
`
`and
`VDS ¼ Vd IDðRS þ RDÞ:
`
`ð3Þ
`
`Here RD and RS represent the drain and source parasitic
`series resistances, respectively. According to Fikry et al.
`[15], the velocity saturation effect is imbedded in the
`
`following free-carrier mobility model:
`l0
`l ¼
`1 þ h Vg VT
`
`
`
`
`
`
`
`
`
`
`
`;
`
`1 þ l0Vd
`
`Leff vsat
`
`ð4Þ
`
`where l0 is the low-field mobility, h is the mobility de-
`gradation factor due to the vertical field, and vsat is the
`saturation velocity of the carriers. Using (1)–(4) and the
`
`
`approximation Vg ¼ VGS, it can be proved that
`ID
`¼ s1=2 Vg
` VT
`g1=2
`m
`
`ð5Þ
`
`;
`
`Fig. 6. RM implemented on the plot of the ratio of the drain
`current to the square root of the transconductance (ID=g0:5
`m )
`versus Vg of the test bulk device measured at Vd ¼ 10 mV. This
`method evaluates VT from the intercept to the lateral axis of its
`straight line fit.
`
`where gm is the transconductance and
`
`
`
`
`s ¼ Lm DLeff l0Vd
`
`vsat
`
`:
`
`ð6Þ
`
`W l0CoVd
`
`Then, by plotting the ID=g1=2m versus Vg curve the values
`
`of VT and s can be extracted from the intercept and the
`slope of its straight line fit. Fig. 6 shows the results of
`applying this method to the present test device. As can
`be observed, in the present case it is not clear where to
`do the linear approximation to be extrapolated to the Vg
`
`axis to extract the value of VT. The ID=g1=2m versus Vg
`curve for the present test device shown in Fig. 6 does not
`appear to totally fulfill this method’s assumptions, since
`it does not clearly behave in the linear manner expected.
`Therefore, the linear fit shown is just a guess, amidst the
`evident non-linearity and the noise present, significantly
`enhanced by dividing the current by the square root of
`its first derivative (gm).
`
`2.6. Transition method
`
`This method uses the sub-threshold-to-strong inver-
`sion transition region of the MOSFET’s transfer char-
`acteristics to extract the threshold voltage. It is based on
`
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`
`necessary values of voltage and current in an integral
`function D defined as
`y0
`x dy
`Dðx; yÞ ¼
`
`Z
`
`Z
`
`x0
`
`y dx;
`
`0
`
`0
`
`ð8Þ
`
`
`
`;
`
`an auxiliary operator that involves integration of the
`drain current as a function of gate voltage.
`In order to extract VT, the drain current is measured
`versus Vg below and above threshold with zero body bias
`and a small constant value of drain voltage. Next the
`following function G1 is numerically calculated from
`measured data [33]:
`
`R
`
`G1ðVg; IDÞ ¼ Vg 2
`
`Vga
`Vgb
`
`IDðVgÞdVg
`ID
`
`;
`
`ð7Þ
`
`where Vgb and Vga are the lower and upper limits of
`integration corresponding to gate voltages below and
`above threshold, respectively.
`A plot of G1 versus ln ID should result in a straight
`line below threshold, where the current is dominated by
`diffusion and consequently it is predominantly expo-
`nential. As soon as Vg ¼ VT function G1 should drop
`abruptly. This is what is observed with the present test
`device, as revealed in Fig. 7. It can be shown that the
`maximum value of G1 corresponds to the threshold
`voltage of the device [33], which for this case happens to
`be 0.49 V. It should be noted that parasitic resistance
`and mobility degradation effects influence the shape of
`the above-threshold G1, but not significantly its maxi-
`mum value, unless those effects are highly pronounced.
`
`2.7. Integral method
`
`The integral method was developed in [32] to be in-
`sensitive to the effect of drain and source parasitic series
`resistances. It was demonstrated that substituting the
`
`and after substituting and performing algebraic manip-
`ulations the following function can be obtained:
`
`D1ðVgb; RmVgbÞ ¼ 2Vgb
`Vgb
`þ
`KðVmax Vgb VTÞ
`K
`þ 2ðVmax VTÞ
`
`
`ln 1
`
`K
`
`Vgb
`Vmax VT
`
`ð9Þ
`where Vgb ¼ Vmax Vg and Vmax is a constant parameter
`equal to the maximum gate voltage under consideration.
`When D1 is plotted versus Vgb, the value of VT is
`obtained using a procedure similar to extracting the
`ideality factor and saturation current of a junction di-
`ode, as explained in [47,48]. Fig. 8 illustrates the appli-
`cation of this method to the test device producing a VT
`value of 0.51. Notice that D1 also permits the extraction
`of parameter K. Although this method gives accurate
`results, is it quite cumbersome to implement.
`
`2.8. Corsi function method
`
`Corsi and coworkers have proposed [21] a method
`based on the following function:
`Beta ¼ ID
`Vg VP
`
`ð10Þ
`
`;
`
`Fig. 7. Transition method implemented on the plot of function
`G1 versus ID of the test bulk device. This method evaluates the
`threshold voltage from the maximum value of G1.
`
`Fig. 8. Integral method implemented on the plot of function D1
`versus Vgb of the test bulk device. This method evaluates the
`threshold voltage by doing a curve fitting of function D1.
`
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`Exhibit 1008
`Page 006
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`
`589
`
`Fig. 9. Corsi function method implemented on the plot of the
`Corsi function versus Vg of the test bulk device for several ar-
`bitrary values of VP. This method evaluates the threshold
`voltage by finding the plot for which the minimum just disap-
`pears and for this particular case VP ¼ VT.
`
`where Vg > VP and VP is a parameter chosen in the region
`of expected values of VT. Fig. 9 shows plots of this
`function versus Vg, for several values of VP, as derived
`from the experimental transconductance characteristics
`of the test device. The minimum is related to a value
`of Vg ¼ VT þ ða=2ÞVd, where a is a parameter dependent
`on small channel effects and the body effect. It can
`be demonstrated that the minimum disappears when
`VP ¼ VT. In practice this method appears not to be very
`precise for determining the value of VT and in our
`opinion it offers no particular advantages.
`
`2.9. Second derivative logarithmic method
`
`The SDL method was proposed by Aoyama in 1995
`[31]. The threshold voltage is determined as the gate
`voltage at which the second difference of the logarithm
`of the drain current takes on a minimum value. It cor-
`responds to the gate voltage at which drift and diffusion
`drain currents are equal to each other. The authors
`claim that this definition of VT overcomes the disad-
`vantages of the CC method, which requires measuring
`the effective channel length, and that it is more accurate
`than ELR, which can be applied only to the low drain
`voltage region, or than the already described transcon-
`ductace method. However, similarly to other methods
`based on taking SDs, this method is highly sensitive
`to experimental measurement noise and error. Fig. 10
`shows the implementation of this method for the present
`test device. It produces a reasonable value for VT of
`
`Fig. 10. SDL method implemented on the plot of d2 lnðIDÞ=dV 2
`versus Vg of the test bulk device measured at Vd ¼ 10 mV. This
`method consists of finding the gate-voltage at which d2ID=dV 2
`g
`exhibits a minimum value.
`
`g
`
`about 0.5 V, if measurement noise and error are sup-
`pressed.
`
`2.10. Linear cofactor difference operator method
`
`ð11Þ
`
`where Gx is an arbitrary constant. The drain current,
`neglecting parasitic series resistance, is modeled by
`
`This method (LCDO), recently developed by He and
`co-workers to avoid the dependence of the extracted VT
`value on mobility degradation, proposes to use the fol-
`lowing auxiliary function [22]:
`DID  GxVg ID;
`
`
`
`ID ¼ Gd Vg VT
`1 þ h Vg VT
`where Gd  ðW =LeffÞlCoVd is a constant of the device
`with units of conductance, h is the mobility reduction
`factor due to the vertical electric field in the channel,
`and other parameters have their usual meaning. Sub-
`stituting (12) into (11) and taking the first derivative,
`it can be proved that DID will present a minimum
`value located at Vg ¼ Vgp and DID ¼ DIDP. The evalua-
`tion of this minimum value allows to extract VT and h by
`#
`"
`
`
`using:
`VT ¼ DIDP
` Gx
`Þ1=2 þ 1
`ð
`Gd
`GxGd
`
`
`
`;
`
`ð12Þ
`
`1=2
`
`Vgp
`
`ð13Þ
`
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`
`2
`
`;
`
`
`
`ID ¼ b VGS VT VDS
`VDS
`ð15Þ
`Þ
`1 þ h VGS VTð
`
`where b ¼ ðW =LeffÞlCo is the transconductance param-
`eter, h is the mobility reduction factor due to the vertical
`electric field in the channel, and other parameters have
`their usual meaning. For the MOSFET biased in the
`strong inversion region with a small drain voltage, and
`assuming the voltage drop in the source and drain series
`resistances is small compared to the gate bias, the drain
`current can be rewritten as
`Vg b
`ID ¼ a
`Vg c
`
`Vd;
`
`ð16Þ
`
`Fig. 11. LCDO method implemented on the plot of function
`DID versus Vg of the test bulk device measured at Vd ¼ 10 mV.
`
`and
`
`
`d G1=2
`h ¼ G1=2
`Vgp VT
`G1=2
`x
`
`x
`
`
`
`:
`
`ð14Þ
`
`Fig. 11 shows the results of applying this method to the
`present test device. As can be observed, the location of
`the minimum value changes for different Gx. According
`to this method, the values of VT and h should be inde-
`pendent on the selected value of Gx. In contrast to this
`assumption, our results indicates that for variations of
`Gx from 40 to 60 lS, VT changes from 0.35 to 0.45 V and
`h goes from 0.53 to 0.38 V1. Therefore this method
`does not seem to be very appropriate for short-channel
`devices.
`
`2.11. Non-linear optimization method
`
`The non-linear optimization method [23,24] extracts
`VT based on optimization techniques applied to the
`MOSFET current–voltage characteristics. It has two
`main advantages: (1) the consistent determination of all
`the model parameters because of the simultaneous ex-
`traction; and (2) the reduction of the effects of the noise
`on the experimental data due to the optimization tech-
`niques. There are two main disadvantages, however: (1)
`non-physical parameter values can be obtained because
`of the pure fitting scheme, and (2) the requirement of a
`long computational process.
`The development of this method, proposed by Kar-
`lsson and Jeppson [24], is as follows; The drain current
`for the MOSFET is expressed as
`
`where
`a ¼
`
`b
`h þ bRDS
`
`;
`
`b ¼ VT þ Vd
`2
`
` VT;
`
`ð17Þ
`
`ð18Þ
`
`ð19Þ
`
`and
`c ¼ VT
`
`:
`
`1
`h þ bRDS
`Fig. 12 shows measured ID versus Vg characteristics
`(solid lines) for Vd ¼ 10 mV of the same test device
`previously described. The fit (closed circles) to the sim-
`ulated results were obtained by using the optimized
`values of a ¼ 12:4 mA/V, b ¼ VT ¼ 0:57 V and c ¼
`0:24 V such that the following parameter e has the
`minimum value:
`
`Fig. 12. Non-linear optimization method implemented on the
`measured ID–Vg characteristics of the test bulk device measured
`at Vd ¼ 10 mV.
`
`LG Display Co., Ltd.
`Exhibit 1008
`Page 008
`
`

`

`A. Ortiz-Conde et al. / Microelectronics Reliability 42 (2002) 583–596
`
`591
`
`ð20Þ
`
`
`
`2
`
`:
`
`Vg b
`Vg c
`
`Vd
`
`
`
` a
`
`ID
`
`XN
`
`i¼1
`
`e 
`
`Then, the following three parameters can be calculated
`from the values of a, b and c:
`b ¼ a
`b c Vd
`
`;
`
`2
`
`ð21Þ
`
`h þ bRDS ¼
`
`1
`b c Vd
`b1 ¼ ðlCoÞ1 ðLm DLeffÞ
`
`;
`
`2
`
`W
`
`ð22Þ
`
`ð23Þ
`
`:
`
`3. Extraction from the ID–Vg curve of MOSFETs biased
`in the saturation region
`
`To extract the saturation threshold voltage VTsat the
`drain current must be measured as a function of gate
`voltage with the drain connected to the gate, to guarantee
`that the device is operating in the saturation regime.
`
`3.1. Extrapolation method in the saturation region
`
`The ESR method, determines the threshold voltage
`from the gate voltage axis intercept of the I 0:5
`Dsat–Vg
`characteristics linearly extrapolated at its maximum first
`derivative (slope) point [1–3] as illustrated in Fig. 13.
`The value of VTsat calculated for the present device re-
`sults to be 0.46 V.
`
`3.2. G1 function method
`
`This method [34,35] considers that the device is op-
`erating in the saturation region and under strong in-
`version. The gate and drain terminals are connected
`together to ensure saturation operation. The saturation
`drain current may be expressed as [1–3]
`IDsat ¼ K
`ð
` VTÞ2;
`2
`
`ð24Þ
`
`VGS
`
`where VT is the threshold voltage,
`VGS ¼ Vg IDsatRs
`
`ð25Þ
`
`is the intrinsic gate–source voltage, Vg is the extrinsic
`gate–source voltage, Rs is the source series resistance,
`and
`K ¼
`
`b
`
`
`1 þ h VGS VTð
`
`Þ :
`
`ð26Þ
`
`In the previous equation, h is the mobility degradation
`parameter and b ¼ ðW =LeffÞlCo is the transconductance
`parameter.
`
`Fig. 13. Extrapolation method in the saturation region (ESR)
`D –Vg characteristics of the
`implemented on the measured I 0:5
`test bulk device measured at Vd ¼ Vg. This method consists
`D ¼ 0) of the
`of finding the gate-voltage axis intercept (i.e., I 0:5
`D –Vg curve at its maximum slope
`linear extrapolation of the I 0:5
`point.
`
`
`Substituting (25) and (26) into (24) and solving for Vg,
`we obtain:
`Vg ¼ VT þ RtIDsat þ 2IDsat
`Ko
`
`þ R2
`hI 2
`
`Dsat
`
`1=2
`
`;
`
`ð27Þ
`
`
`
`where
`Rh  h
`Ko
`
`ð28Þ
`
`is an effective resistance due to the free-carrier mobility
`degradation in the channel, and
`Rt  Rs þ Rh
`
`ð29Þ
`
`is the total effective resistance.
`Using the approximation, ð2IDsat=KoÞ  R2
` 
`hI 2
`Dsat, Eq.
`(27) is simplified to
`Vg  VT þ RtIDsat þ 2
`Ko
`
`1=2
`
`I 1=2
`Dsat:
`
`ð30Þ
`
`Based on an approach developed previously [47,48], we
`have proposed to use the following function to suppress
`the linear term of IDsat in (30):
`
`Z
`
`¼ Vg 2
`IDsat
`
`Vg
`
`0
`
`IDsatðVgÞdVg:
`
`ð31Þ
`
`
`
`
`
`G1 Vg; IDsat
`
`LG Display Co., Ltd.
`Exhibit 1008
`Page 009
`
`

`

`592
`
`A. Ortiz-Conde et al. / Microelectronics Reliability 42 (2002) 583–596
`
`smaller drain currents than conventional single-crystal
`bulk devices. Amorphous TFTs introduce the following
`additional difficulties for VT extraction: First, the satu-
`ration drain current in strong inversion is usually mod-
`eled by an equation of the form [49]
`ð33Þ
`
`IDsat ¼ K VGSð
` VTÞm;
`where K is a conductance parameter with units of A Vm
`and m an empirical parameter which can be different
`from 2, the value used in conventional MOSFET mod-
`els. Second, the value of parameter m cannot be easily
`extracted from a simple plot of logðIDsatÞ versus logðVgÞ
`because practical operation values of Vg are usually not
`large enough to validate the approximation: ðVGS
`VTÞ  Vg. Third, it is not clear at what point the IDsat
`versus Vg plot could be linearly extrapolated, since the
`curve does not present an inflexion point because the
`mobility of these devices raises as Vg is increased.
`A method to extract the threshold voltage of amor-
`phous thin film MOSFETs, that circumvents some of
`these difficulties,
`is based on the following function
`R
`which can be numerically computed from the measured
`
`IDsatðVgÞ characteristics:
`IDsatðVgÞdVg
`IDsat
`
`Vg
`0
`
`¼
`
`H Vg
`
`;
`
`ð34Þ
`
`Fig. 14. G1
`function method in the saturation region im-
`plemented using the plot of the G1 function versus I 0:5
`D of the
`test bulk device measured at Vd ¼ Vg. This method consists of
`D ¼ 0) of the linear
`finding the gate-voltage axis intercept (i.e., I 0:5
`D –Vg curve.
`extrapolation of the I 0:5
`
`where the upper limit of integration is any suitable value
`greater than the threshold voltage.
`The integral in (34) is negligible for values of Vg such
`R
`that the device is operating in the strong inversion re-
`
`gion. Thus, HðVgÞ may be approximated by
`IDsatðVgÞdVg
`IDsat
`
`Vg
`VT
`
`
`
`H Vg
`
`:
`
`ð35Þ
`
`After substitution of (33) into (35), and assuming that
`the variation of K with respect to Vg is insignificant, we
`obtain:
`
`
`
`
`
`
`¼ Vg VT
`H Vg
`m þ 1
`which means that HðVgÞ behaves linearly in the strong
`inversion region. Therefore, a plot of function H versus
`Vg has a slope that defines the value of m and a Vg axis
`intercept which gives the sought after value of VT. Be-
`cause of the low-pass filter nature of integration, this
`method offers the additional advantage of inherently
`reducing the effects of experimental errors.
`After having found m and VT, the remaining pa-
`rameter in (33), K, may be easily evaluated from
`IDsat
`K ¼
`Vg VT
`
`;
`
`
`
`
`
`m :
`
`ð36Þ
`
`ð37Þ
`
`This extraction procedure will be applied to an experi-
`mental n-channel a-Si:H thin film MOSFET having: a
`
`The function defined in the previous equation, with units
`of V, can be numerically computed from the measured
`IDsatðVgÞ characteristics. It can be proved, after using
` 
`integration b