Declaration for Inter Partes Review of USP 7,907,137
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Inter Partes Review of:
`U.S. Patent No. 7,907,137
`Issued: March 15, 2011
`Application No.: 11/391,941
`
`For: Active matrix drive circuit
`
`)
`)
`)
`)
`)
`
`DECLARATION OF MILTIADIS HATALIS, PH.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,907,137
`
`LG Display Co., Ltd.
`Exhibit 1003
`Page 001
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`

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`Declaration for Inter Partes Review of USP 7,907,137
`
`B.
`
`
`CONTENTS
`I.
`INTRODUCTION ........................................................................................... 1
`II.
`BACKGROUND AND QUALIFICATIONS ................................................. 1
`III. DOCUMENTS CONSIDERED IN FORMING MY OPINIONS .................. 8
`IV. UNDERSTANDING OF LEGAL PRINCIPLES ........................................... 9
`V.
`BACKGROUND ........................................................................................... 14
`A.
`Technology Background ..................................................................... 14
`1.
`Active Matrix OLED Displays ................................................. 14
`2.
`Thin Film Transistors ................................................................ 17
`3.
`Drive Circuits In Active Matrix Displays ................................. 25
`The ’137 Patent ................................................................................... 30
`1.
`The ’137 Patent’s Display Apparatus ....................................... 31
`a.
`Threshold Voltage Detection .......................................... 32
`b.
`Compensation Voltage Application ............................... 34
`c.
`Supplying Gradation Current.......................................... 35
`d.
`Light Emission ................................................................ 38
`The Challenged Claims ............................................................. 39
`2.
`Prosecution History ................................................................... 42
`3.
`VI. CLAIM CONSTRUCTION .......................................................................... 46
`VII. CLAIMS 1, 10-11 AND 36-37 ARE UNPATENTABLE OVER
`MIYAZAWA ALONE OR IN VIEW OF CHILDS ..................................... 50
`1. Miyazawa (Ex. 1005) ................................................................ 50
`2.
`Childs (Ex. 1006) ...................................................................... 61
`Independent Claim 10 Is Unpatentable over Miyazawa Alone or
`with Childs. ......................................................................................... 66
`1.
`Preamble: operation of the display drive apparatus .................. 67
`
`A.
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`LG Display Co., Ltd.
`Exhibit 1003
`Page 002
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`Declaration for Inter Partes Review of USP 7,907,137
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`C.
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`II.
`
`B.
`
`2.
`[a] Threshold voltage detection circuit ..................................... 72
`[b] Compensation voltage application circuit ........................... 94
`3.
`[c] Gradation signal generation circuit ................................... 101
`4.
`Independent Claim 36 Is Unpatentable over Miyazawa Alone or
`with Childs. ....................................................................................... 108
`Independent Claim 1 Is Unpatentable over Miyazawa, Alone or
`with Childs ........................................................................................ 111
`D. Dependent Claims 11 and 37 Are Unpatentable over Miyazawa
`Alone or with Childs. ........................................................................ 115
`1.
`Claim 11 .................................................................................. 115
`2.
`Claim 37 .................................................................................. 118
`DEPENDENT CLAIMS 9, 15 AND 39 ARE UNPATENTABLE
`OVER MIYAZAWA, ALONE OR WITH CHILDS, AND KASAI. ........ 119
`A. Overview of Claims 9, 15 and 39 ...................................................... 119
`B.
`Overview of Kasai (Ex. 1007) ........................................................... 123
`C.
`Claims 9, 15 and 39 Are Unpatentable Over Miyazawa, Alone
`Or With Childs, and Kasai. ............................................................... 130
`III. CONCLUSION ............................................................................................ 137
`
`
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`ii
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`LG Display Co., Ltd.
`Exhibit 1003
`Page 003
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`Declaration for Inter Partes Review of USP 7,907,137
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`I.
`
`INTRODUCTION
`1.
`I have been retained as an independent expert witness on behalf of LG
`
`Display Co., Ltd. (“LG Display” or “Petitioner”) in the above-captioned inter partes
`
`review (“IPR”) relating to U.S. Patent No. 7,907,137 (“’137 patent”) (Ex. 1001).
`
`2.
`
`I understand that LG Display is petitioning for IPR of claims 1, 10, 11,
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`15, 36, 37 and 39 of the ’137 patent and requests that the United States Patent and
`
`Trademark Office (“PTO”) cancel those claims.
`
`3.
`
`In preparing this Declaration, I have reviewed the ’137 patent, and
`
`considered the documents identified in Section III in light of the general knowledge
`
`in the relevant art. In forming my opinions, I relied upon my education, knowledge,
`
`and experience, and considered the level of ordinary skill in the art as discussed
`
`below.
`
`4.
`
`I am being compensated for my work in this matter at my standard
`
`consulting rate, which is $400 per hour, plus actual expenses. My compensation is
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`not dependent in any way upon the outcome of this matter.
`
`II. BACKGROUND AND QUALIFICATIONS
`5. My complete qualifications and professional experience are described
`
`in my academic curriculum vitae, a copy of which is provided as Exhibit 1004. The
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`following is a brief summary of my relevant qualifications and professional
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`experience.
`
`1
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`Exhibit 1003
`Page 004
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`Declaration for Inter Partes Review of USP 7,907,137
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`6.
`
`I am currently a Professor in the Department of Electrical and Computer
`
`Engineering at Lehigh University. I hold a B.S. degree in physics from Aristotle
`
`University, Greece, an M.S. degree in electrical engineering from SUNY Buffalo,
`
`and a Ph.D. (1987) in electrical engineering from Carnegie Mellon University. In
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`1987, I joined Lehigh University as an assistant professor in the Department of
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`Electrical & Computer Engineering. I served as an associate professor at Lehigh
`
`University from 1991 to 1995, and have been a full professor at Lehigh University
`
`since 1995. From 1988 to 1993, I served as associate director of the
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`Microelectronics Research Laboratory at Lehigh University. Since 1992, I have
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`served as director of the Display Research Laboratory at Lehigh University. From
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`2010 to 2013, I served as interim director of the Sherman Fairchild Center for Solid
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`State Studies at Lehigh University. From 2003 to 2008, I concurrently served as
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`professor in the Department of Computer Science at Aristotle University, Greece.
`
`7.
`
`From 1987 to 2015, I also worked as an independent consultant for a
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`number of major technology companies in the flat panel display and semiconductor
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`field, including IBM, Kodak, Sharp and Motorola Solutions. In 1992, I was a
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`visiting scientist at XEROX Palo Alto Research Laboratory.
`
`8.
`
`As discussed below, my technical expertise is in flat panel display
`
`technologies, including thin film transistor (“TFT”) and active-matrix organic light-
`
`emitting diode (“AMOLED”) technologies.
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`2
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`LG Display Co., Ltd.
`Exhibit 1003
`Page 005
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`Declaration for Inter Partes Review of USP 7,907,137
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`9.
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`I am the author or co-author of 180 technical publications including
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`three issued patents, and two book chapters, including one on AMOLED pixel
`
`electronic circuits and one on polysilicon TFT technology. As of this writing, I have
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`a total of 4,118 citations and my h-index is 28 according to Google Scholar.
`
`10.
`
`In 1992, I founded, and became Director of, the “Display Research
`
`Laboratory,” which was the first academic laboratory in the United States dedicated
`
`to research and development of electronic thin film materials and devices, including
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`thin film transistors, for flat panel displays, flexible electronics and novel large area
`
`microelectronic system applications. As Director of Lehigh’s Display Research
`
`Laboratory, I have raised over $13 million through research contracts and grants to
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`support the laboratory's research activities. These contracts and grants were funded
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`by the Defense Advanced Research Program Agency (DARPA), the Army Research
`
`Laboratory (ARL), the National Science Foundation (NSF), the National
`
`Aeronautics and Space Administration (NASA), the State of Pennsylvania, and a
`
`variety of industrial companies including Corning, IBM, Kodak, Sharp, Northrop
`
`Grumman, and others.
`
`11. From 1987 to present I have conducted research in microelectronics,
`
`including semiconductors, electronic materials, devices and circuits for integrated
`
`circuits and integrated microsystems. My research mainly focuses on electronic thin
`
`film materials and devices, microelectronic fabrication processes, novel electronic
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`3
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`Exhibit 1003
`Page 006
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`Declaration for Inter Partes Review of USP 7,907,137
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`circuits, and integrated microsystems.
`
` My research group pioneered the
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`development of electronic materials, devices, and circuits on flexible substrates,
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`active matrix organic light emitting diode displays, and addressable arrays for
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`integrated sensor applications such as fingerprint sensors for biometrics and
`
`multichannel gas sensors.
`
`12. As a faculty member, I supervised the research of twenty PhD
`
`dissertations in the technical field of semiconductors/microelectronics. Upon
`
`graduating, all twenty of my PhD graduate students moved either to industrial
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`positions in the electronic industry, including positions at Apple, IBM, Intel, TSMC,
`
`and Motorola, or into academic positions in the United States or abroad. I have also
`
`supervised the research of several post-doctoral researchers and research associates
`
`at Lehigh. Moreover, I have supervised a large number of graduate student Master’s
`
`theses and numerous undergraduate research projects. I have been an invited
`
`lecturer at numerous universities, industrial laboratories, and conferences in the
`
`United States and overseas.
`
`13. The list of peer-reviewed journals in which my papers were published
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`include Thin Solid Films, Journal of the Electrochemical Society, Solid State
`
`Electronics, Journal of Applied Physics, Journal of the Society for Information
`
`Display, Journal of Materials Science, and multiple IEEE journals including the
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`IEEE Journal of Display Technology, IEEE Transactions on Electronic Devices,
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`4
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`Exhibit 1003
`Page 007
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`Declaration for Inter Partes Review of USP 7,907,137
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`IEEE Solid State Circuits, and IEEE Electron Device Letters. The technical
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`conferences where my papers were presented have been organized by scientific
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`societies including: Society of Information Display (SID), Materials Research
`
`Society (MRS), Electrochemical Society (ECS), and Institute of Electrical and
`
`Electronics Engineers (IEEE).
`
`14.
`
`I am also a named inventor on U.S. Patent No. 8,390,536, directed at
`
`controlling current to pixels in an active matrix display by adjusting voltage on the
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`data lines and two international patents associated with the above invention, one
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`issued in Korea and one in Japan.
`
`15.
`
`I have taught a number of different undergraduate and graduate level
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`courses in the Electrical and Computer Engineering department at Lehigh
`
`University. These courses have generally centered on physics, technology, and the
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`design and fabrication of solid-state devices and integrated circuits. I have also
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`introduced several new courses which include “Introduction to VLSI Design,”
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`“Semiconductor Material and Device Characterization,” and “Introduction to
`
`Photovoltaic Energy Systems.” I also regularly teach the “Principles of Electrical
`
`Engineering,” “Introduction to Computer Engineering,” “Electronic Circuits,” and
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`“Introduction to VLSI Circuits” courses.
`
`16. As part of my research, I utilize much of the same equipment and many
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`of the same microfabrication processes that are in use by the semiconductor industry
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`5
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`Exhibit 1003
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`Declaration for Inter Partes Review of USP 7,907,137
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`including: Plasma-Enhanced Chemical Vapor Deposition (PECVD) for the
`
`deposition of amorphous silicon, silicon nitride and silicon dioxide films; sputter and
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`e-beam deposition tools for aluminum, copper, nickel tungsten, titanium, gold,
`
`tantalum, and other metallic thin films; photolithographic tools for defining
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`photoresist patterns on the substrates; as well as reactive ion etching or wet etching
`
`tools for removing various thin film materials from the substrates. I also utilize
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`several tools for the characterization of the materials and structures used in
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`microelectronic devices
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`including: optical microscopes, Scanning Electron
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`Microscopy (SEM), Transmission Electron Microscopy (TEM), and Atomic Force
`
`Microscopy (AFM). I further utilize a variety of electrical characterization
`
`techniques and instruments for testing the electrical performance of completed
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`electronic circuits and systems.
`
`17. As part of my research, I pioneered a technique for crystallizing
`
`amorphous silicon. Similar techniques have been used in the manufacturing of
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`integrated circuits and flat panel displays. In addition, my research group at Lehigh
`
`pioneered the fabrication of electronic devices and circuits on novel flexible
`
`substrates and the development of integrated microsystems flexible substrates,
`
`including active matrix organic light emitting diode displays, and addressable arrays
`
`for integrated sensor applications such as fingerprint sensors for biometrics and
`
`multichannel gas sensors. Many industrial and academic laboratories currently
`
`6
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`Exhibit 1003
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`Declaration for Inter Partes Review of USP 7,907,137
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`pursue similar research activities; such research flows from the accomplishments of
`
`my research group in this technical field.
`
`18. My industrial experience includes work at the XEROX Palo Alto
`
`Research Laboratory and various consulting projects with companies in the flat-
`
`panel display or semiconductor technical fields. Those projects related to electronic
`
`materials, semiconductor devices and their application to microelectronic systems.
`
`19.
`
`I am a member of several professional organizations including the
`
`Electron Device Society of the IEEE and the SID. I have also been the chair or
`
`co-chair at numerous national and international conferences and symposiums,
`
`including several SID-sponsored Workshops on Active Matrix Liquid Crystal
`
`Displays and a Materials Research Society Symposium on Flat Panel Displays. I
`
`have co-authored two book chapters, one dealing with the “Polysilicon TFT
`
`Technology” and another on the application of “Polysilicon TFTs in AMOLED
`
`Displays.” I have served as a reviewer for technical papers submitted to several
`
`scientific journals and have also served as a reviewer for several years for the
`
`National Science Foundation Small Business Innovative Research (SBIR) program.
`
`20. A detailed list of my publications, education and professional
`
`experience, research grants, PhD dissertations for which I served as advisor,
`
`publications, and litigation cases in which I served as a technical expert, can be found
`
`in my curriculum vitae attached and submitted as Exhibit 1004.
`
`7
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`Page 010
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`Declaration for Inter Partes Review of USP 7,907,137
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`III. DOCUMENTS CONSIDERED IN FORMING MY OPINIONS
`21.
`In addition to the information identified above (e.g., ¶¶ 3, 5-20) and
`
`elsewhere in this Declaration, in forming my opinions, I have considered the
`
`following documents:
`
`Description
`Ex.
`1001 U.S. Patent No. 7,907,137 (“’137 Patent”)
`1002 Prosecution history for U.S. Patent Application 11/391,941 (“’137 FH”)
`
`1005 U.S. Patent Application Publication No. 2005/0116902 (“Miyazawa”)
`1006
`International Patent Application Publication No. WO 2005/069267
`(“Childs”)
`1007 U.S. Patent Application Publication No. 2005/0156837 (“Kasai”)
`1008 A. Ortiz-Conde, et. al., A Review of Recent MOSFET Threshold Voltage
`Extraction Methods, 583 Microelectronics Reliability 42 (2002) (“Ortiz-
`Conde”)
`1009 Solas's Opening Claim Construction Brief, Solas OLED Ltd. v. LG
`Display Co., Ltd., et al., Case No. 6:19-cv-00236-ADA, Dkt. 68 (W.D.
`Tex. Mar. 13, 2020) (“Solas's Op. Claim Construction Br.”)
`1010 Defendants' Opening Claim Construction Brief, Solas OLED Ltd. v. LG
`Display Co., Ltd., et al., Case No. 6:19-cv-00236-ADA, Dkt. 67 (W.D.
`Tex. Mar. 13, 2020) (“Defendants' Op. Claim Construction Br.”)
`1011 U.S. Patent Application Publication No. 2002/0101172 (“Bu”)
`1012 Excerpts from Neil H.E. Weste & Kamran Eshraghian, Principles of
`CMOS VLSI Design (2nd Ed. 1993) (“Weste”)
`1013 Answer and Counterclaims of Defendant LG Display Co., Ltd. to
`Plaintiff’s Second Amended Complaint, Solas OLED Ltd. v. LG Display
`Co., Ltd., et al., Case No. 6:19-cv-00236-ADA, Dkt. 41 (W.D. Tex. Oct.
`28, 2019) (“Answer”)
`
`8
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`Declaration for Inter Partes Review of USP 7,907,137
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`Description
`Ex.
`1014 UK Patent Application No. 2,389,952 (“Routley”)
`
`1015 U.S. Patent No. 6,809,706 (“Shimoda”)
`
`1016 U.S. Patent No. 8,115,707 (“Nathan”)
`1017 Excerpts from Transcript of Telephonic Markman Hearing before the
`Honorable Alan. D. Albright, Solas OLED Ltd. v. LG Display Co., Ltd.,
`et al., Case No. 6:19-cv-00236-ADA (W.D. Tex. May 22, 2020)
`(“Markman Hearing Transcript”)
`1018 U.S. Patent No. 7,576,718 (“Miyazawa-718”)
`
`1019 U.S. Patent Application Publication No. 2005/0067971 (“Kane”)
`
`
`
`IV. UNDERSTANDING OF LEGAL PRINCIPLES
`22.
`I understand that a prior art reference can anticipate a patent claim when
`
`the prior art’s disclosure renders the recited claim elements not novel. I understand
`
`that in order to anticipate a patent claim, a prior art reference must teach each and
`
`every element of the claim, expressly or inherently, with the same arrangement as in
`
`the claims. I understand that a reference anticipates a claim if it discloses the claimed
`
`invention such that a POSITA could take its teachings in combination with his/her
`
`own knowledge of the particular art and be in the possession of the invention.
`
`23.
`
`In analyzing anticipation, I understand that it is important to consider
`
`the scope of the claims, the level of skill in the relevant art, and the scope and content
`
`of the prior art. I understand that extrinsic evidence may be considered for
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`Declaration for Inter Partes Review of USP 7,907,137
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`anticipation so long as it is used to explain, but not expand, the meaning of the
`
`reference.
`
`24.
`
`I understand that a prior art reference can render a patent claim obvious
`
`to one of ordinary skill in the art if the differences between the subject matter set
`
`forth in the patent claim and the prior art are such that the subject matter of the claim
`
`would have been obvious at the time the claimed invention was made.
`
`25.
`
`In analyzing obviousness, I understand that it is important to consider
`
`the scope of the claims, the level of skill in the relevant art, the scope and content of
`
`the prior art, the differences between the prior art and the claims, and any secondary
`
`considerations.
`
`26.
`
`I understand that when the claimed subject matter involves combining
`
`pre-existing elements to yield no more than what one would expect from such an
`
`arrangement, the combination is obvious. I also understand that in assessing whether
`
`a claim is obvious one must consider whether the claimed improvement is more than
`
`the predictable use of prior art elements according to their established functions. I
`
`understand that there need not be a precise teaching in the prior art directed to the
`
`specific subject matter of a claim because one can take account of the inferences and
`
`creative steps that a person of skill in the art would employ. I further understand
`
`that a person of ordinary skill is a person of ordinary creativity, not an automaton.
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`10
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`Declaration for Inter Partes Review of USP 7,907,137
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`27.
`
`I understand that obviousness cannot be based on the hindsight
`
`combination of components selectively culled from the prior art. I understand that
`
`in an obviousness analysis, neither the motivation nor the avowed purpose of the
`
`inventors controls the inquiry. Any need or problem known in the field at the time
`
`of the invention and addressed by the patent can provide a reason for combining
`
`elements. For example, I understand that it is important to consider whether there
`
`existed at the time of the invention a known problem for which there was an obvious
`
`solution encompassed by the patent’s claims. I understand that known techniques
`
`can have obvious uses beyond their primary purposes, and that in many cases a
`
`person of ordinary skill can fit the teachings of multiple pieces of prior art together
`
`like pieces of a puzzle.
`
`28.
`
`I understand that, when there is a reason to solve a problem and there
`
`is a finite number of identified, predictable solutions, a person of ordinary skill has
`
`good reason to pursue the known options within his or her technical grasp. I further
`
`understand that, if this leads to the anticipated success, it is likely the product not of
`
`innovation but of ordinary skill and common sense, which bears on whether the
`
`claim would have been obvious.
`
`29.
`
`I understand that secondary considerations can include, for example,
`
`evidence of commercial success of the invention, evidence of a long-felt need that
`
`was solved by an invention, evidence that others copied an invention, or evidence
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`11
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`Declaration for Inter Partes Review of USP 7,907,137
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`that an invention achieved a surprising or unexpected result. I further understand
`
`that such evidence must have a nexus, or causal relationship to the elements of a
`
`claim, in order to be relevant. I am unaware of any such secondary considerations
`
`for the ’891 patent.
`
`30.
`
`I understand that a person of ordinary skill in the art (“POSITA”) is a
`
`hypothetical person who is presumed to be aware of all pertinent art, possesses
`
`conventional wisdom in the art, is a person of ordinary creativity, and has common
`
`sense. I understand that this hypothetical person is considered to have the normal
`
`skills and knowledge of a person in a certain technical field (including knowledge
`
`of known problems and desired features in the field).
`
`31.
`
`I have been asked to analyze claims 1, 9, 10-11, 15, 36, 37 and 39 of
`
`the ’137 patent, and prior art relating thereto, from the perspective of such a person
`
`at the time of the alleged inventions. I have been informed by counsel to assume
`
`that this is in the 2005 time frame. I will refer to this time as the “relevant time” or
`
`similar herein.
`
`32.
`
`I understand that the factors that may be considered in determining the
`
`level of ordinary skill in the art may include (a) the type of problems encountered in
`
`the art, (b) prior art solutions to those problems, (c) the rapidity with which
`
`innovations are made, (d) sophistication of the technology, and (e) the educational
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`level of active workers in the field. I also understand that in a given case, every
`
`factor may not be present, and one or more factors may predominate.
`
`33. Based on my review of these factors, the prior art described below and
`
`my personal experience in the field, it is my opinion that the level of ordinary skill
`
`in the art for the ’137 patent at the relevant time (2005) would have had at least a
`
`bachelor’s degree in electrical engineering (or equivalent) and at least two years’
`
`industry experience, or equivalent research in circuit design. Alternatively, a
`
`POSITA could substitute directly relevant additional education for experience, e.g.,
`
`an advanced degree relating to the design of electroluminescent devices, drive
`
`circuits, or other circuit design or an advance degree in electrical engineering (or
`
`equivalent), with at least one year of industry experience. I have also been informed
`
`that in the District Court litigation, Patent Owner’s expert states that a person with a
`
`bachelor’s degree in physics, electrical engineering, or a related field with
`
`approximately 3–5 years of experience in active-matrix and/or LED displays and
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`systems, or a postgraduate degree such as a master’s degree in physics, electrical
`
`engineering, or a related field with approximately 1–2 years of experience in active-
`
`matrix and/or LED displays.
`
`34. At the relevant time, I would have qualified as at least a POSITA under
`
`either mine or Patent Owner’s definition, and my opinions herein are informed by
`
`my own knowledge based on my personal experiences and observing others of
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`various skill levels (including those above and below the level of a POSITA). In
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`particular, I was actively engaged in the field of the ’137 patent at the relevant time
`
`(2005 timeframe), as discussed above.
`
`35. Nevertheless, my opinions below are not restricted to the precise
`
`definition of a POSITA above. The claims of the ’137 patent are directed to a drive
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`circuit design that was well-known and taught by numerous prior art references
`
`including the references discussed below. Thus, my opinions below would apply
`
`under any reasonable definition of a POSITA.
`
`
`
`
`
`V. BACKGROUND
`A. Technology Background
`1.
`Active Matrix OLED Displays
`36. As stated in the ’137 patent, organic electroluminescent (OEL)-based
`
`display screens were well-known in the art as of 2005. See, e.g., ’137 patent, 1:36-
`
`58 (stating that “self-luminous type display[s]” with “organic electroluminescent
`
`elements (organic EL elements) … arranged in a matrix,” with “various driving
`
`control mechanisms and/or control methods for controlling an operation of the
`
`optical elements” were known in the art). A type of OEL element that was
`
`commonly used in such displays were organic light emitting diodes, or OLEDs.
`
`37. OLEDs are “current driven devices,” which means that the amount of
`
`light the OLED emits varies approximately linearly with the amount of current
`
`flowing through the OLED. See Bu (Ex. 1011), [8]. This feature of OLEDs stands
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`in contrast to liquid crystal display (LCD) devices, which are “voltage driven
`
`devices.” Id. Because the amount of light emitted by the OLED varies linearly with
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`the amount of current, and because the amount of current in turn varies nonlinearly
`
`with the amount of voltage difference between the anode and the cathode of the
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`OLED, the amount of light emitted by the OLED varies nonlinearly with the voltage
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`difference between the anode and the cathode of the OLED. See Routley (Ex. 1014),
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`Figs. 4a, 4b, 017 (Figure 4a shows the “typical light intensity-voltage curve [] for an
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`OLED…is non-linear and exhibits a dead region corresponding to the OLED turn-
`
`on voltage….Figure 4b shows a light intensity-current curve [] for an OLED
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`which…is approximately linear.”), id., 018-020. This relationship is depicted in the
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`figure below, which shows the light intensity vs. voltage curve (left) and the light
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`intensity vs. current curve (right) of an OLED.
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`Routley (Ex. 1014), Figs. 4a, 4b, 017-20; see also, e.g., Shimoda (Ex. 1015), Fig. 7.
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`Page 018
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`Declaration for Inter Partes Review of USP 7,907,137
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`38. A typical OLED display is an array of many (e.g., millions) of OLEDs,
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`each of which must generate the intended level of light emission for a given pixel in
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`a given frame in order to achieve light emission uniformity. See ’137 patent, 2:1-10
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`(describing “conventional organic EL display apparatus”). An exemplary
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`“conventional” display is shown in Figure 35 of the ’137 patent below, where the
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`pixel circuits EMp are arranged at an intersection of scan lines Ssel arranged in the
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`row direction and data lines DLp arranged in a column direction.
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`
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`’137 patent, Fig. 35.
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`39.
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`In an “active matrix” OLED display, such as the display described in
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`the ’137 patent, the amount of current applied to each OLED is controlled by a
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`Page 019
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`Declaration for Inter Partes Review of USP 7,907,137
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`separate drive circuit for each pixel (i.e., within each pixel EMp is a drive circuit).
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`’137 patent, 1:44-45. An active matrix drive circuit includes a memory element,
`
`which is typically a storage capacitor that holds a voltage level, and at least one thin
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`film transistor (“TFT”) that controls the current supplied to the OLED. Id., 2:11-25.
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`Like any field effect transistor, a TFT comprises a semiconductor material (e.g.,
`
`polysilicon or amorphous silicon) forming the channel, and three electrodes: (1) the
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`gate electrode; (2) the source electrode; and (3) the drain electrode. WESTE (Ex.
`
`1012), 120 (“A thin-film transistor has source/drain and channel regions constructed
`
`from deposited thin films of semiconductor material.”). The drive circuit of the ’137
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`patent is described later in this section.
`
`2.
`Thin Film Transistors
`In electrical circuits TFTs and other field-effect transistors (FETs) are
`
`40.
`
`routinely represented in one of two ways shown below. The depicted transistor on
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`the left is what is referred to as an N-channel-TFT, and on the right is a P channel
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`TFT.
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`
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`17
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`Page 020
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`Declaration for Inter Partes Review of USP 7,907,137
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`Weste, 023 (annotated).
`
`41. The gate electrode serves to control the flow of current through the
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`channel arranged between the source and drain. Specifically, the control takes place
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`via the voltage difference between the gate and source electrode (referred to as “gate-
`
`to-source voltage”). The gate-to-source voltage (simply referred as “gate-source
`
`voltage” in this declaration) serves to regulate the semiconductor resistance, to
`
`switch on or off a current flow through the channel (from source to drain) and to
`
`control the magnitude of the current flow (when the device operates in the saturation
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`region as explained below).
`
`42.
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`In an n-channel FET or TFT (above on the left) current can flow from
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`its drain to its source because, by convention, the drain is connected to a higher
`
`potential, and the transistor is conductive (i.e. the transistor is ON and current can
`
`flow) when the gate voltage (Vg) is higher than the source (Vs) voltage by at least
`
`the threshold voltage (Vtn). Thus, the necessary condition for current to flow in an
`
`n-channel TFT is for the gate-source voltage (Vgs) to be higher than the threshold
`
`voltage, i.e. Vgs=Vg-Vs>Vtn. Conversely, in a p-channel FET or TFT, current can
`
`flow from its source to its drain because its source is connected to the higher
`
`potential, and the transistor will conduct when the voltage at its gate (Vg) is lower
`
`than the voltage at its source (Vs) by at least the threshold voltage (Vtp). Thus, the
`
`necessary condition for current to flow in a p-channel TFT is for the gate-source
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`Page 021
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`Declaration for Inter Partes Review of USP 7,907,137
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`voltage (Vsg) to be higher than the threshold voltage, i.e. Vsg=Vs-Vg>IVtpI (where
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`IVtpI is the absolute value of the threshold voltage). Weste, 029.
`
`43. A typical way to model (i.e. describe quantitatively) the electrical
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`characteristics of a TFT is to follow the approach used in a MOS transistor made in
`
`single crystal silicon, where the transistor’s operation is divided in three distinct
`
`regions of operation. Within each of these three regions the drain to source current
`
`(Ids) can be described by a simple equation that may include the gate to source
`
`voltag