(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2010/0328262 A1
`HUANG et al.
`(43) Pub. Date:
`Dec. 30, 2010
`
`US 20100328262A1
`
`(54) DETECTOR AND DETECTION METHOD
`FOR A CAPACTIVE TOUCHPAD TO
`IDENTIFY AREAL TOUCH POINT
`
`(22) Filed:
`
`Jun. 21, 2010
`
`(30)
`
`Foreign Application Priority Data
`
`(75) Inventors:
`
`CHUN-CHUNGHUANG,
`HSINCHU CITY (TW);
`TSUN-MIN WANG, MIAOLI
`COUNTY (TW); TE-SHENG
`sty TAICHUNG COUNTY
`
`Correspondence Address:
`ROSENBERG, KLEIN & LEE
`3458 ELLCOTT CENTER DRIVE-SUTE 101
`ELLICOTT CITY, MD 21043 (US)
`
`(73) Assignee:
`
`ELAN MICROELECTRONICS
`CORPORATION, HSINCHU
`(TW)
`
`(21) Appl. No.:
`
`12/819,477
`
`Jun. 25, 2009 (TW) ................................. O98121462
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F 3/045
`(52) U.S. Cl. ........................................................ 345/174
`
`ABSTRACT
`(57)
`-
`A two-step detection for a capacitive touchpad to identify a
`real touch point first detects the self capacitances from mul
`tiple capacitance sensor traces of the capacitive touchpad to
`identify any touch point on the capacitive touchpad and then,
`if multiple touch points are detected, further detects the
`mutual capacitance at one of the detected touch points to
`identify whether it is a real touch point.
`
`Detect the self capacitances from multiple capacitance Sensor
`traces of a capacitive touchpad to identify any touch point
`
`S40
`
`
`
`
`
`
`
`
`
`
`
`
`
`Multiple
`touch points?
`
`Detect the mutual capacitance of one detected touch
`point to identify whether it is a real touch point
`
`Detection end
`
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`US 2010/0328262 A1
`
`Dec. 30, 2010
`
`DETECTOR AND DETECTION METHOD
`FOR A CAPACTIVE TOUCHPAD TO
`IDENTIFY AREAL TOUCH POINT
`
`FIELD OF THE INVENTION
`0001. The present invention is related generally to capaci
`tive touchpads and, more particularly, to a detector and
`method for a capacitive touchpad to identify a real touch
`point.
`
`BACKGROUND OF THE INVENTION
`0002 FIG. 1 is a simplified diagram showing the layout of
`a conventional two-dimensional capacitive touchpad 10
`which includes capacitance sensor traces TX1-TXN in X-di
`rection and TY1-TYM in Y-direction. For such capacitive
`touchpad 10, conventional methods for touch point detection
`is to detect the self capacitance from each of the capacitance
`sensor traces TX1-TXN and TY1-TYM, and then the position
`at which the detected capacitance has the maximum variation
`is determined as the touch point. However, Such methods can
`only detect a single touch point each time, but cannot be
`effective for multi-touch applications. For example, as shown
`in FIG. 2, when two fingers touch the capacitive touchpad 10
`simultaneously, in addition to the real touch points 20 and 22.
`there will be two ghost points 24 and 26 being detected as
`touch points simultaneously. In further detail, when the fin
`gers touch at the positions 20 and 22, it causes the self capaci
`tances of the capacitance sensor traces TX1, TX2. TY1 and
`TY2 having peak variations simultaneously, from which four
`touch points (TX1, TY1), (TX2. TY1), (TX1, TY2) and
`(TX2. TY2) will be identified. This case makes it impossible
`for a capacitive touchpad 10 to properly identify the real
`touch points 20 and 22 from the multiple detected touch
`points 20-26.
`0003. Therefore, it is desired a detector and method for a
`capacitive touchpad to distinguish a real touch point from a
`ghost point.
`
`SUMMARY OF THE INVENTION
`0004 An object of the present invention is to provide a
`simple detector for a capacitive touchpad to identify a real
`touch point.
`0005. An object of the present invention is to provide a
`simple method for a capacitive touchpad to identify a real
`touch point.
`0006. According to the present invention, it is a two-step
`detection for a capacitive touchpad to identify a real touch
`point. First, the self capacitances of multiple capacitance
`sensor traces of the capacitive touchpad are detected to iden
`tify any touch point, and then, if multiple touch points are
`detected, one of the detected touch points is further detected
`for the mutual capacitance at this touch point to identify
`whether it is a real touch point.
`0007 According to the present invention, a detector for a
`capacitive touchpad to identify a real touch point includes a
`self negative capacitance compensator for compensating the
`self capacitor of a detected capacitance sensor trace, a first
`Switch connected between the self negative capacitance com
`pensator and the detected capacitance sensor trace, a Switch
`ing circuit connected to the detected capacitance sensor trace
`for applying one of multiple Supply Voltages to the detected
`capacitance sensor trace, a mode Switching device connected
`to the detected capacitance sensor trace and another capaci
`
`tance sensor trace which has an intersection with the detected
`capacitance sensor, a second Switch connected between the
`detected capacitance sensor trace and the mode Switching
`device, and a sensing circuit connected to the mode Switching
`device for detecting the self capacitance of the detected
`capacitance sensor trace or the mutual capacitance at the
`intersection to generate a sense signal. In a first mode, the
`mode Switching device connects the detected capacitance
`sensor trace to the sensing circuit to detect the variation of the
`self capacitance from the detected capacitance sensor trace,
`and in a second mode, the mode Switching device connects
`the other capacitance sensor trace to the sensing circuit to
`detect the variation of the mutual capacitance at the intersec
`tion.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0008. These and other objects, features and advantages of
`the present invention will become apparent to those skilled in
`the art upon consideration of the following description of the
`preferred embodiments of the present invention taken in con
`junction with the accompanying drawings, in which:
`0009 FIG. 1 is a simplified diagram showing the layout of
`a conventional two-dimensional capacitive touchpad;
`0010 FIG. 2 is a schematic view showing a ghost phenom
`enon caused by two fingers simultaneously touching a capaci
`tive touchpad;
`0011 FIG.3 is a schematic view showing two capacitance
`sensor traces of a capacitive touchpad that have a parasitic
`mutual capacitor therebetween at an intersection thereof;
`0012 FIG. 4 is a flowchart of a detection method for a
`capacitive touchpad to identify a real touch point according to
`the present invention;
`0013 FIG. 5 is the circuit diagram of a first embodiment
`according to the present invention to carry out the process of
`FIG. 4;
`0014 FIG. 6 is the equivalent circuit of the detector shown
`in FIG. 5 in a first mode:
`0015 FIG. 7 is a timing diagram of the available switches
`shown in FIG. 6;
`0016 FIG. 8 is the equivalent circuit of the detector shown
`in FIG. 6 during the first time phase shown in FIG. 7 when no
`object touches a detected capacitance sensor trace;
`(0017 FIG.9 is the equivalent circuit of the detector shown
`in FIG. 6 during the second and fourth time phases shown in
`FIG. 7 when no object touches a detected capacitance sensor
`trace;
`(0018 FIG. 10 is the equivalent circuit of the detector
`shown in FIG. 6 during the third time phase shown in FIG. 7
`when no object touches a detected capacitance sensor trace;
`(0019 FIG. 11 is the equivalent circuit of the detector
`shown in FIG. 6 during the first time phase shown in FIG. 7
`when a detected capacitance sensor trace is touched;
`(0020 FIG. 12 is the equivalent circuit of the detector
`shown in FIG. 6 during the second and fourth time phases
`shown in FIG. 7 when a detected capacitance sensor trace is
`touched;
`(0021
`FIG. 13 is the equivalent circuit of the detector
`shown in FIG. 6 during the third time phase shown in FIG. 7
`when a detected capacitance sensor trace is touched;
`0022 FIG. 14 is the equivalent circuit of the detector
`shown in FIG. 5 in a second mode;
`0023 FIG. 15 is a timing diagram of the available switches
`shown in FIG. 14;
`
`DELL EXHIBIT 1039 PAGE 35
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`
`Dec. 30, 2010
`
`0024 FIG. 16 is the equivalent circuit of the detector
`shown in FIG. 14 during the first time phase shown in FIG. 15
`when no object touches a detected capacitance sensor trace;
`0025 FIG. 17 is the equivalent circuit of the detector
`shown in FIG. 14 during the second time phase shown in FIG.
`15 when no object touches a detected capacitance sensor
`trace;
`0026 FIG. 18 is the equivalent circuit of the detector
`shown in FIG. 14 during the first time phase shown in FIG. 15
`when a detected capacitance sensor trace is touched;
`0027 FIG. 19 is the equivalent circuit of the detector
`shown in FIG. 14 during the second time phase shown in FIG.
`15 when a detected capacitance sensor trace is touched;
`0028 FIG. 20 is another timing diagram of the available
`switches shown in FIG. 14;
`0029 FIG. 21 is the equivalent circuit of the detector
`shown in FIG. 14 during the first time phase shown in FIG. 20
`when no object touches a detected capacitance sensor trace;
`0030 FIG. 22 is the equivalent circuit of the detector
`shown in FIG. 14 during the second time phase shown in FIG.
`20 when no object touches a detected capacitance sensor
`trace;
`FIG. 23 is the circuit diagram of a second embodi
`0031
`ment according to the present invention to carry out the pro
`cess of FIG. 4;
`0032 FIG. 24 is the equivalent circuit of the detector
`shown in FIG. 23 in a first mode;
`0033 FIG.25 is a timing diagram of the available switches
`shown in FIG. 24;
`0034 FIG. 26 is the equivalent circuit of the detector
`shown in FIG.24 during the first time phase shown in FIG.25:
`0035 FIG. 27 is the equivalent circuit of the detector
`shown in FIG. 24 during the second and fourth time phases
`shown in FIG. 25:
`0036 FIG. 28 is the equivalent circuit of the detector
`shown in FIG. 24 during the third time phase shown in FIG.
`25;
`0037 FIG. 29 is the equivalent circuit of the detector
`shown in FIG. 23 in a second mode;
`0038 FIG.30 is a timing diagram of the available switches
`shown in FIG. 29:
`0039 FIG. 31 is the equivalent circuit of the detector
`shown in FIG.29 during the first time phase shown in FIG.30;
`0040 FIG. 32 is the equivalent circuit of the detector
`shown in FIG. 29 during the second time phase shown in FIG.
`30:
`0041 FIG.33 is another timing diagram of the available
`switches shown in FIG. 29;
`0042 FIG. 34 is the equivalent circuit of the detector
`shown in FIG.32 during the first time phase shown in FIG.33;
`and
`0043 FIG. 35 is the equivalent circuit of the detector
`shown in FIG.32 during the first time phase shown in FIG.33.
`
`DETAILED DESCRIPTION OF THE INVENTION
`0044) For clearer illustration of the principle that the
`present invention is based on, FIG. 3 provides a schematic
`view of two capacitance sensor traces TXN and TYM of a
`capacitive touchpad. As is well known, at an intersection of
`the capacitance sensor traces TXN and TYM, there will be a
`parasitic mutual capacitor 30 whose capacitance is repre
`sented by Cxy. Touching at the intersection of the capacitance
`sensor traces TXN and TYM will cause not only variations of
`respective self capacitances of the capacitance sensor traces
`
`TXN and TYM, but also a variation of the mutual capacitance
`Cxy. Therefore, this mutual capacitance variation can be used
`for identifying whether the intersection of the capacitance
`sensor traces TXN and TYM is touched.
`004.5
`FIG. 4 is a flowchart of a detection method for a
`capacitive touchpad to identify a real touch point according to
`the present invention. Step S40 detects the self capacitances
`from multiple capacitance sensor traces of the capacitive
`touchpad to identify the touch points on the capacitive touch
`pad. Step S42 identifies whether multiple touch points are
`detected in step S40. If there is only one touch point, then the
`detection is ended; otherwise, the process goes to step S44 to
`further identify whether each of the detected touch points is a
`real touch point.
`0046 FIG. 5 is the circuit diagram of a first embodiment
`according to the present invention to carry out the process of
`FIG. 4, in which a detector 50 is used to scan the capacitance
`sensor traces TX1-TXN and TY1-TYMofa capacitive touch
`pad for identifying any real touch point. Multiplexers 52 and
`54 are used to select from the capacitance sensor traces TX1
`TXN and TY1-TYM to connect to the detector 50 for being
`detected for capacitance therefrom. In the detector 50, a
`switching circuit 56 includes switches SW2, SW3 and SW4
`connected between the output terminal of the multiplexer 52
`and nodes having supply voltages VREFP. VCOM and
`VREFN, respectively, and is thereby controlled to apply one
`of the supply voltages VREFP VCOM and VREFN to the
`output terminal of the multiplexer 52. A switch SW1 is further
`connected between the output terminal of the multiplexer 52
`and a self negative capacitance compensator 58 which is used
`to compensate the detected capacitance sensor trace when
`detecting the variation of the self capacitance therefrom, to
`eliminate the difference in basic self capacitance between
`different capacitance sensor traces and thereby improve the
`detection. The self negative capacitance compensator 58 has
`a capacitor CN connected between the switch SW1 and a
`node having a Supply Voltage VN. The structure and operation
`of the self negative capacitance compensator 58 are well
`known, for example, see Taiwan Patent Application Publica
`tion No. 200905538. A Switch SWS is connected between the
`output terminal of the multiplexer 52 and a mode switching
`device 60 which is controlled to connect the output terminal
`of the multiplexer 52 or 54 to an input terminal of a sensing
`circuit 62 depending on the mode selected for the detector 50
`to operate with. The sensing circuit 62 may detect the self
`capacitance of each of the capacitance sensor traces TX1
`TXN and TY1-TYM, and the mutual capacitance at the inter
`section of any two capacitance sensor traces, to generate a
`sense signal Vs. In the sensing circuit 62, an operational
`amplifier 64 has two input terminals 66 and 68 connected to
`the mode Switching device 60 and receiving a Supply Voltage
`VCOM, respectively, a switch SW6 is connected between the
`input terminal 66 and the output terminal 70 of the operational
`amplifier 64, a gain control capacitor array CF has a first
`terminal 76 and a second terminal 78 connected to the input
`terminal 66 and the output terminal 70 of the operational
`amplifier 64, respectively, and is configured to determine the
`gain of the sensing circuit 62, and a storage capacitor array CS
`is connected to the output terminal 70 of the operational
`amplifier 64 to store the sense signal Vs. An analog-to-digital
`converter (ADC) 72 converts the sense signal Vs from analog
`to digital, and the digital signal Vd is sent to a microprocessor
`control unit (MCU) 74 which controls the multiplexers 52 and
`54, the switches SW1-SW6, and the mode switching device
`
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`
`Dec. 30, 2010
`
`60, determines the capacitances of the capacitors CN and CF,
`and processes the digital signal Vd to calculate the coordi
`nates of the detected touch points. The voltage difference
`between the supply voltage VREFP and the supply voltage
`VCOM on the input terminal 68 of the operational amplifier
`64, and the Voltage difference between the supply voltage
`VREFN and the supply voltage VCOM on the input terminal
`68 of the operational amplifier 64, are designed to be equal in
`magnitude but opposite in polarity.
`0047. In FIG. 5, when the input terminal 66 of the opera
`tional amplifier 64 is switched to the position a by the mode
`switching device 60, the detector 50 enters a first mode to
`detect the self capacitance from either of the capacitance
`sensor traces TX1-TXN and TY1-TYM. FIG. 6 is the equiva
`lent circuit of the detector 50 in the first mode, and FIG. 7 is
`a timing diagram of the available switches SW1-SW2 and
`SW4-SW6 shown in FIG. 6. As shown in FIG. 7, the first
`mode includes four time phases T1–T4, and FIGS. 8-10 are
`the equivalent circuits of the detector 50 during the time
`phases T1–T4, when no object touches the detected capaci
`tance sensor trace. Referring to FIGS. 7 and 8, during the time
`phase T1, the switches SW1, SW4 and SW5 are opened and
`the Switches SW2 and SW6 are closed, so that the detected
`capacitance sensor trace is charged by the Voltage source
`VREFP. Since no object touches the detected capacitance
`sensor trace, the self capacitor 90 of the detected capacitance
`sensor trace has the original capacitance CB and will store the
`charge
`
`0048 For the operational amplifier 64 whose input termi
`nal 66 is directly connected to its output terminal 70 now, due
`to the virtual short circuit between the input terminals 66 and
`68 of the operational amplifier 64, the voltages on both the
`input terminal 66 and the output terminal 70 of the operational
`amplifier 64 are VCOM, and thus the terminals 76 and 78 of
`the gain control capacitor array CF are at an equal Voltage
`VCOM and the charge stored in the gain control capacitor
`array CF is Zero accordingly.
`0049 Referring to FIGS. 7 and 9, during the time phase
`T2, the Switches SW1 and SWS are closed and the switches
`SW2. SW4 and SW6 are opened, so that the self negative
`capacitance compensator 58 and the input terminal 66 of the
`operational amplifier 64 are connected to the detected capaci
`tance sensor trace, and an amplifier configuration is estab
`lished by the operational amplifier 64 and the gain control
`capacitor array CF. At this time, the Voltage of the self nega
`tive capacitance compensator 58 is lower than the Voltage
`VCOM. Due to the virtual short circuit between the input
`terminals 66 and 68 of the operational amplifier 64, the input
`terminal 66 is at a voltage equal to VCOM, and the self
`capacitor 90 will store the charge
`Gcb=VCOMXCB.
`The capacitor CN stores the charge
`Con=(VCOM-VN)xCN.
`The gain control capacitor array CF stores the charge
`Eq-4
`Gof (VS-VCOM)xCF.
`According to the law of charge conservation, the net charge
`during the time phase T1 is equal to that of the time phaseT2,
`i.e.,
`
`Eq-2
`
`Eq-3
`
`from which it is obtained
`
`The MCU 74 may adjust the capacitance CN or the supply
`voltage VN in the self negative capacitance compensator 58
`Such that when no object touches the detected capacitance
`sensor trace, the charge stored in the self negative capacitance
`compensator 58 and that stored in the self capacitor 90 can
`cancel each other out, and thereby no remaining charge will
`be transferred to the gain control capacitor array CF. In other
`words, in case no object touches the detected capacitance
`sensor trace, the sense signal Vs outputted by the operational
`amplifier 64 is equal to VCOM, so that the equation Eq-6 may
`be modified into
`
`0050 Referring to FIGS. 7 and 10, during the time phase
`T3, the switches SW1, SW2 and SW5 are opened and the
`switches SW4 and SW6 are closed, so that the detected
`capacitance sensor trace is charged by the Voltage source
`VREFN and therefore the self capacitor 90 stores the charge
`
`The input terminal 66 of the operational amplifier 64 is
`directly connected to its output terminal 70 now, and due to
`the virtual short circuit between the input terminals 66 and 68
`of the operational amplifier 64, the voltages on both the input
`terminal 66 and the output terminal 70 of the operational
`amplifier 64 are VCOM, and thus the terminals 76 and 78 of
`the gain control capacitor array CF are at an equal Voltage
`VCOM and the charge stored in the gain control capacitor
`array CF is Zero accordingly.
`0051 Referring to FIGS. 7 and 9, during the time phase
`T4, the switches SW1 and SWS are closed and the switches
`SW2. SW4 and SW6 are opened, so that the self negative
`capacitance compensator 58 and the input terminal 66 of the
`operational amplifier 64 are connected to the detected capaci
`tance sensor trace, and an amplifier configuration is estab
`lished by the operational amplifier 64 and the gain control
`capacitor array CF. At this time, the Voltage of the self nega
`tive capacitance compensator 58 is higher than the Voltage
`VCOM. Due to the virtual short circuit between the input
`terminals 66 and 68 of the operational amplifier 64, the input
`terminal 66 of the operational amplifier 64 is at a voltage
`equal to VCOM, so that the charge Qcb stored in the self
`capacitor 90 is as shown in the equation Eq-2, the charge Qcn
`stored in the capacitor CN is as shown in the equation Eq-3,
`and the charge Qcf stored in the gain control capacitor array
`CF is as shown in the equation Eq-4. According to the law of
`charge conservation, the net charge during the time phase T3
`is equal to that of the time phase T4, i.e.,
`
`from which it is obtained
`
`In case no object touches the detected capacitance sensor
`trace, the MCU 74 may adjust the capacitance CN or the
`Supply Voltage VN in the self negative capacitance compen
`sator 58 such that the charge stored in the self negative capaci
`tance compensator 58 and that stored in the self capacitor 90
`can cancel each other out and thereby, no remaining charge
`will be transferred to the gain control capacitor array CF and
`
`DELL EXHIBIT 1039 PAGE 37
`
`

`

`US 2010/0328262 A1
`
`Dec. 30, 2010
`
`the sense signal Vs outputted by the operational amplifier 64
`is equal to VCOM. Thus, the equation Eq-10 may be modified
`into
`
`0052 FIGS. 11 and 13 are the equivalent circuits of the
`detector 50 in the first mode during the time phases T1–T4
`when the detected capacitance sensor trace is touched. Refer
`ring to FIGS. 7 and 11, during the time phase T1, the switches
`SW1, SW4 and SW5 are opened and the switches SW2 and
`SW6 are closed, so that the detected capacitance sensor trace
`is charged by the voltage source VREFP. Since the detected
`capacitance sensor trace is touched, the self capacitor 90 has
`a capacitance increment AC. As a result, the detected capaci
`tance of the self capacitor 90 is changed into CB+AC, and the
`self capacitor 90 will store the charge
`
`The input terminal 66 of the operational amplifier 64 is con
`nected to the output terminal 70 now, and due to the virtual
`short circuit between the input terminals 66 and 68 of the
`operational amplifier 64, the voltages on both the input ter
`minal 66 and the output terminal 70 of the operational ampli
`fier 64 are VCOM and thus, the terminals 76 and 78 of the gain
`control capacitor array CF are at an equal voltage VCOM and
`the charge stored in the gain control capacitor array CF is Zero
`accordingly.
`0053 Referring to FIGS. 7 and 12, during the time phase
`T2, the Switches SW1 and SWS are closed and the switches
`SW2. SW4 and SW6 are opened, so that the self negative
`capacitance compensator 58 and the input terminal 66 of the
`operational amplifier 64 are connected to the detected capaci
`tance sensor trace, and an amplifier configuration is estab
`lished by the operational amplifier 64 and the gain control
`capacitor array CF. At this time, the Voltage in the self nega
`tive capacitance compensator 58 is lower than the Voltage
`VCOM. Due to the virtual short circuit between the input
`terminals 66 and 68 of the operational amplifier 64, the input
`terminal 66 of the operational amplifier 64 is at a voltage
`equal to VCOM, and the self capacitor 90 will store the charge
`
`The charge stored in the capacitor CN is as shown in the
`equation Eq-3, and the charge stored in the gain control
`capacitor array CF is as shown in the equation Eq-4. Accord
`ing to the law of charge conservation, the net charge during
`the time phase T1 is equal to that of the time phaseT2, i.e.,
`
`from which it is obtained
`
`By Substituting the equation Eq-7 into the equation Eq-15, it
`is obtained
`Eq-16
`Vs=(AC/CF)(VREFP-VCOM)+VCOM.
`0054 Referring to FIGS. 7 and 13, during the time phase
`T3, the switches SW1, SW2 and SW5 are opened and the
`switches SW4 and SW6 are closed, so that the detected
`capacitance sensor trace is charged by the Voltage source
`VREFN. Hence, the self capacitor 90 will store the charge
`
`The input terminal 66 of the operational amplifier 64 is
`directly connected to the output terminal 70 now. Due to the
`virtual short circuit between the input terminals 66 and 68 of
`the operational amplifier 64, the voltages on both the input
`terminal 66 and the output terminal 70 of the operational
`amplifier 64 are VCOM and thus, the terminals 76 and 78 of
`the gain control capacitor array CF are at an equal Voltage
`VCOM and the charge stored in the gain control capacitor
`array CF is Zero accordingly.
`0055 Referring to FIGS. 7 and 12, during the time phase
`T4, the switches SW1 and SWS are closed and the switches
`SW2. SW4 and SW6 are opened, so that the self negative
`capacitance compensator 58 and the input terminal 66 of the
`operational amplifier 64 are connected to the detected capaci
`tance sensor trace, and an amplifier configuration is estab
`lished by the operational amplifier 64 and the gain control
`capacitor array CF. At this time, the Voltage in the self nega
`tive capacitance compensator 58 is higher than the Voltage
`VCOM. Due to the virtual short circuit between the input
`terminals 66 and 68 of the operational amplifier 64, the input
`terminal 66 of the operational amplifier 64 is at a voltage
`equal to VCOM, so that the charge Qcb stored in the self
`capacitor 90 is as shown in the equation Eq-13, the charge
`Qcn stored in the capacitor CN is as shown in the equation
`Eq-3, and the charge Qcf stored in the gain control capacitor
`array CF is as shown in the equation Eq-4. According to the
`law of charge conservation, the net charge during the time
`phase T3 is equal to that of the time phase T4, i.e.,
`
`from which it is obtained
`
`By Substituting the equation Eq-11 into the equation Eq-19, it
`is obtained
`
`Eq-20
`Vs=(AC/CF)(VREFN-VCOM)+VCOM.
`0056. The storage capacitor array CS stores the sense sig
`nals Vs generated during the time phases T2 and T4, and
`extracts the average therefrom to eliminate low-frequency
`noise. During the time phases T1 and T3, the detected capaci
`tance sensor trace is charged by the voltage sources VREFP
`and VREFN, respectively, and therefore, the low-frequency
`noise of the sense signals Vs obtained from the time phases T2
`and T4 will act as that a DC voltage is added to one of the
`sense signals Vs and the same DC voltage is subtracted from
`the other sense signal Vs. Hence, by averaging the two sense
`signals Vs, the magnitude of the noise is averaged into Zero.
`The extracted average of the two sense signals Vs is converted
`into the digital signal Vd by the ADC 72. As described above,
`when no object touches the detected capacitance sensor trace,
`the sense signal Vs is equal to VCOM; on the other hand,
`when the detected capacitance sensor trace is touched, the
`sense signal VS is as shown in the equation Eq-16 or Eq-20.
`Thereby, the MCU 74 can identify whether the detected
`capacitance sensor trace is touched according to the digital
`signal Vd. In the previously mentioned operation, actions
`corresponding to the time phases T3 and T4 may also be
`conducted before those corresponding to the time phases T1
`and T2.
`0057 Referring to FIG. 5, when the input terminal 66 of
`the operational amplifier 64 is switched to the position bby
`the mode switching device 60, the detector 50 enters a second
`
`DELL EXHIBIT 1039 PAGE 38
`
`

`

`US 2010/0328262 A1
`
`Dec. 30, 2010
`
`mode to detect the mutual capacitor at an intersection of two
`capacitance sensor traces. FIG. 14 is the equivalent circuit of
`the detector 50 in the second mode, in which the multiplexers
`52 and 54 select the capacitance sensor traces TXN and TYM.
`respectively. In the equivalent circuit 100 of the two capaci
`tance sensor traces TXN and TYM, a self capacitor 102 of the
`capacitance sensor trace TXN has a ca