(12) United States Patent
`Maharyta
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,319,505 B1
`Nov. 27, 2012
`
`US008319505B1
`
`(54) METHODS AND CIRCUITS FOR
`MSENMUTUAL AND SELF
`
`(75) Inventor: Andriy Maharyta, Lviv (UA)
`(73) Assignee: Cypress Semiconductor Corporation,
`San Jose, CA (US)
`Subject to any site the still
`patent 1s extended or adjusted under
`U.S.C. 154(b) by 240 days.
`
`c
`- r
`(*) Notice:
`
`(21) Appl. No.: 12/606,147
`
`(22) Filed:
`
`Oct. 26, 2009
`
`Related U.S. Application Data
`(63) Continuation-in-part of application No. 12/395,462.
`filed on Feb. 27, 2009.
`(60) Eyal application No. 61/108,450, filed on Oct.
`
`(51) Int. Cl
`(2006.01)
`GOIR 27/26
`(52) U.S. Cl. ........................................ 324/658; 324/678
`(58) Field of Classification Search
`None
`See annlication file for com lete search history
`pp
`p
`ry.
`References Cited
`
`(56)
`
`324,680
`
`U.S. PATENT DOCUMENTS
`6,720,777 B2 * 4, 2004 Wan
`6,768.420 B2
`
`7,006,938 B2
`2, 2006 Laraia
`7,075,864 B2
`7/2006 Kakitsuka
`7,932,897 B2
`4/2011 Elias et al.
`2.
`583 R etal
`2006/0273804 Ai: 12/2006 Delormeet al... 324/658
`2007/0173220 A1
`7, 2007 Kim
`2007/0236478 A1 10/2007 Geaghan et al.
`
`7/2004 Marthy . .
`
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`KR
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`38.39 s A. 33: SR et al.
`aryta
`2012, 0043973 A1
`2/2012 Kremlin
`FOREIGN PATENT DOCUMENTS
`102O100135220
`12/2010
`OTHER PUBLICATIONS
`USPTO Non-Final Rejection for U.S. Appl. No. 1 1/442,212 dated
`Feb. 25, 2011; 13 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/332,980 dated
`Oct. 4, 2011; 5 pages.
`USPTO Advisory Action for U.S. Appl. No. 12/332,980 dated Aug.9,
`2011; 3 pages.
`USPTO Final Rejection for U.S. Appl. No. 12/332,980 dated May 31,
`2011; 11 pages.
`USPTO Non-Final Rejection for U.S. Appl. No. 12/332,980 dated
`Dec. 22, 2010; 9 pages.
`USPTO Advisory Action for U.S. Appl. No. 12/395,462 dated Mar.
`28, 2012; 2 pages.
`
`(Continued)
`Primary Examiner — Minh NTang
`
`ABSTRACT
`(57)
`Capacitance measurement circuits for measuring self and
`mutual capacitances are described. In One embodiment the
`il cap
`described. I
`bodiment th
`capacitance measurement circuit includes: a first electrode
`capacitively coupled with a second electrode; a first plurality
`of switches coupled with the first electrode; and a second
`plurality of switches coupled with the second electrode,
`wherein, during a first operation stage, the first plurality of
`Switches is configured to apply a first initial voltage to the first
`electrode and the second plurality of switches is configured to
`apply a second initial Voltage to the second electrode, and
`wherein, during a second operation stage, the first plurality of
`switches is configured to connect the first electrode with a
`measurement circuit, and the second plurality of Switches is
`configured to connect the second electrode with a constant
`Voltage.
`
`23 Claims, 18 Drawing Sheets
`
`swich
`{&
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`&
`38:
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`US 8,319.505 B1
`Page 2
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`OTHER PUBLICATIONS
`USPTO Final Rejection for U.S. Appl. No. 12/395,462 dated Jan. 3,
`2012; 6 pages.
`USPTO Non-Final Rejection for U.S. Appl. No. 12/395,462 dated
`Aug. 23, 2011; 5 pages.
`USPTO Requirement for Restriction for U.S. Appl. No. 12/395,462
`dated May 13, 2011; 6 pages.
`International Search Report of the International Searching Authority,
`dated Feb. 9, 2009 for International Application No. PCTUS2008/
`0.13622; 2 pages.
`International Written Opinion of the International Searching Author
`ity, dated Feb. 9, 2009 for International Application No. PCT/
`US2008/013622; 5 pages.
`U.S. Appl. No. 61/016,123 "Capacitive Field Sensor With Sigma
`Delta Modulator', filed Dec. 21, 2007, 23 pages.
`U.S. Appl. No. 61/023.988 “TouchSensing Jon Peterson, et al., filed
`Jan. 28, 2008; 26 pages.
`U.S. Appl. No. 61/024,158 “Multi-Touch Sensing Method With Dif
`ferential Input' Dana Olson et al., filed Jan. 28, 2008; 19 pages.
`U.S. Appl. No. 61/067,743 “Multi-Touch Sensing Method with Dif
`ferential Input' Dana Olson et al., filed Feb. 29, 2008; 19 pages.
`USPTO Final Rejection for U.S. Appl. No. 1 1/601.465 dated May 28,
`2010; 12 pages.
`USPTO Non-Final Rejection for U.S. Appl. No. 12/380,141 dated
`Sep. 19, 2011; 6 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 1 1/600,255 dated
`May 30, 2012.
`USPTO Notice of Allowance for U.S. Appl. No. 12/040,387 dated
`Mar. 29, 2012; 8 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/239,692 dated
`Jan. 5, 2012; 8 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/239,692 dated
`May 16, 2012; 8 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/239,692 dated
`Jun. 25, 2012; 8 pages.
`
`USPTO Notice of Allowance for U.S. Appl. No. 12/239,692 dated
`Oct. 13, 2011; 8 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/380,141 dated
`Jan. 26, 2012; 7 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/380,141 dated
`Apr. 10, 2012; 7 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/380,141 dated
`May 15, 2012; 7 pages.
`U.S. Appl. No. 60/947,865: "Capacitive Field Sensor with Sigma
`Delt Modulator.” Viktor Kremin, filed Jul. 3, 2007; 33 pages.
`U.S. Appl. No. 61/030,526: "Capacitive Sensing Universal System
`and Method.” Andriy Ryshtun, filed Feb. 21, 2008; 22 pages.
`Chapweske, Adam; “The PS/2 Mouse Interface.” PS/2 Mouse Inter
`facing, 2001, retrieved on May 18, 2006; 11 pages.
`Cypress Semiconductor Corporation, "CY8C21x34 Data Sheet.”
`CSR User Module, CSRV.1.0; Oct. 6, 2005; 36 pages.
`U.S. Appl. No. 61/108,450: “Alternative Realizations of the CSX
`(TxRX-I) Sensing Scheme for ITO Panels.” Andriy Maharyta, filed
`Oct. 24, 2008; 7 pages.
`USPTO Final Rejection for U.S. Appl. No. 12/395,969 dated Jul. 17,
`2012; 25 pages.
`USPTO Non-Final Rejection for U.S. Appl. No. 12/380,141 dated
`Sep. 5, 2012; 6 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/239,692 dated
`Aug. 15, 2012; 8 pages.
`USPTONotice of Allowance for U.S. Appl. No. 12/380, 14 dated Jun.
`14, 2012; 8 pages.
`USPTO Notice of Allowance for 12/380,141 dated Jul. 31, 2012: 5
`pageS.
`USPTO Notice of Allowance for U.S. Appl. No. 12/395,462 dated
`Jul. 20, 2012; 6 pages.
`USPTO Notice of Allowance for U.S. Appl. No. 12/395,462 dated
`Aug. 29, 2012; 5 pages.
`* cited by examiner
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`US 8,319,505 B1
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`1.
`METHODS AND CIRCUITS FOR
`MEASURING MUTUAL AND SELF
`CAPACITANCE
`
`CROSS REFERENCE TO RELATED
`APPLICATION
`
`This application claims the benefit of U.S. Provisional
`Patent Application No. 61/108,450 filed Oct. 24, 2008. This
`application is a continuation-in-part of U.S. patent applica
`tion Ser. No. 12/395,462 filed Feb. 27, 2009 which claims the
`benefit of U.S. Provisional Patent Application No. 61/067,
`539 filed Feb. 27, 2008.
`
`TECHNICAL FIELD
`
`10
`
`15
`
`The present disclosure relates generally to touch sensors
`and, more particularly, to capacitive touch sensors.
`
`BACKGROUND
`
`Capacitive touch sensors may be used to replace mechani
`cal buttons, knobs and other similar mechanical user interface
`controls. The use of a capacitive sensor allows for the elimi
`nation of complicated mechanical Switches and buttons, pro
`viding reliable operation under harsh conditions. In addition,
`capacitive sensors are widely used in modern customer appli
`cations, providing new user interface options in existing prod
`uctS.
`
`25
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`30
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Embodiments are illustrated by way of example and are not
`intended to be limited by the figures of the accompanying
`drawings, in which like references indicate similar elements
`and in which:
`FIG. 1 illustrates two electrodes situated close to each
`other, according to one embodiment;
`FIG. 2 illustrates one embodiment of a self-capacitance
`circuit that uses a charge accumulation technique;
`FIG. 3 illustrates a block diagram of an apparatus for
`measuring mutual or self capacitance, according to one
`embodiment;
`FIG. 4A illustrates one embodiment of a capacitance to
`current sink converter having an integration capacitor
`coupled to ground;
`FIG. 4B illustrates one embodiment of a capacitance to
`current sink converter having an integration capacitor
`coupled to a high Voltage Supply potential;
`FIG. 5A illustrates one embodiment of a capacitance to
`current source converter having an integration capacitor
`coupled to ground;
`FIG. 5B illustrates one embodiment of a capacitance to
`current source converter having an integration capacitor
`coupled to a high Voltage Supply potential;
`FIG. 6A illustrates a first phase of a converter operation,
`according to one embodiment;
`FIG. 6B illustrates a second phase of a converter operation,
`according to one embodiment;
`FIG. 7A illustrates one embodiment of a capacitance to
`current sink converter used for mutual capacitance measure
`ment, having an integration capacitor coupled to ground;
`FIG. 7B illustrates one embodiment of a capacitance to
`current sink converter used for mutual capacitance measure
`ment, having an integration capacitor coupled to V,
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`FIG. 8A illustrates one embodiment of a capacitance to
`current source converter having an integration capacitor
`coupled to ground;
`FIG. 8B illustrates one embodiment of a capacitance to
`current source converter having an integration capacitor
`coupled to a high Voltage Supply potential;
`FIG. 9A illustrates one embodiment of a capacitance to
`current sink converter used for self capacitance measurement,
`having an integration capacitor coupled to ground;
`FIG.9B illustrates one embodiment of a capacitance to
`current sink converter used for self capacitance measurement,
`having an integration capacitor coupled to a high Voltage
`Supply potential;
`FIG. 10A illustrates one embodiment of a capacitance to
`current source converter used for self capacitance measure
`ment, having an integration capacitor coupled to a high Volt
`age Supply potential;
`FIG. 10B illustrates one embodiment of a capacitance to
`current source converter used for self capacitance measure
`ment, having an integration capacitor coupled to ground;
`FIG. 11 illustrates one embodiment of an interval timer
`method for capacitance measurement;
`FIG. 12 illustrates one embodiment of a resettable current
`integrator with an operation amplifier and an analog-to-digi
`tal converter (ADC);
`FIG. 13 illustrates one embodiment of a current-to-voltage
`converter built around an operational amplifier;
`FIG. 14 illustrates one embodiment of a capacitance to
`current converter with a conversion circuit;
`FIG. 15 illustrates one embodiment of a capacitance to
`current converter with a low-pass filter;
`FIG.16 illustrates one embodiment of a sigma-delta modu
`lator configured as a capacitance to duty cycle converter,
`FIG.17 illustrates one embodiment of a low pass filter with
`a differential analog to digital converter;
`FIG. 18A illustrates base capacitance current compensa
`tion using a resistor as a current sink in a capacitance to
`current converter, according to one embodiment;
`FIG. 18B illustrates base capacitance current compensa
`tion using a resistor for a current source in a capacitance to
`current converter, according to one embodiment;
`FIG. 19A illustrates base capacitance current compensa
`tion using a current source as a current sink in a capacitance
`to current converter, according to one embodiment;
`FIG. 19B illustrates base capacitance current compensa
`tion using a current source in a capacitance to current con
`Verter, according to one embodiment;
`FIG. 20A illustrates using a current mirror with a voltage
`conversion system, according to one embodiment;
`FIG. 20B illustrates using a current mirror with a current
`conversion system, according to one embodiment;
`FIG. 20O illustrates one embodiment of a current mirror
`using a bipolar process technology; and
`FIG. 21 illustrates one embodiment of a capacitance mea
`Surement circuit in a multi-touch touchpad system.
`FIG. 22 illustrates one embodiment of a capacitance to
`current converter with a conversion circuit comprising a cur
`rent mirror, an integration circuit and a timer.
`
`DETAILED DESCRIPTION
`
`In the following description, for purposes of explanation,
`numerous specific details are set forth in order to provide a
`thorough understanding of embodiments of the present inven
`tion. It will be evident, however, to one skilled in the art that
`embodiments of the present invention may be practiced with
`out these specific details. In other instances, well-known cir
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`3
`cuits, structures, and techniques are not shown in detail or are
`shown in block diagram form in order to avoid unnecessarily
`obscuring an understanding of this description.
`Reference in the description to “one embodiment' or “an
`embodiment’ means that a particular feature, structure, or
`characteristic described in connection with the embodiment
`is included in at least one embodiment of the invention. The
`appearances of the phrase “in one embodiment' in various
`places in the specification do not necessarily all refer to the
`same embodiment. Like reference numerals denote like ref
`erences elements throughout.
`A capacitive sensor may be characterized by a base capaci
`tance that includes a self capacitance component and a mutual
`capacitance component. Since the values of these capacitance
`components affect the operation of the capacitive touchsen
`sor and may vary from one capacitive sensor to another, a
`capacitive sensing circuit may benefit from the capability of
`independently measuring the self and mutual capacitances of
`a capacitive sensor.
`Apparatus for and methods of measuring mutual and self
`capacitance in a capacitive touch sensor are described. The
`apparatus and methods described herein may be used in
`capacitive touch detection systems such as, for example,
`capacitive touch screens and, in particular, with capacitive
`touch screens having multiple simultaneous touch detection
`capabilities. Alternatively, the apparatus and methods
`described herein may be used with single touch detection
`systems or other types of capacitive touch systems.
`The capacitance measurement circuits described herein
`may be used for touch detection in single electrode systems,
`transmit/receive (TX-RX) systems, or in combined TX-RX
`and single electrode systems. The TX-RX systems can use the
`mutual capacitance change detection, and single electrode
`systems can use the self capacitance change detection. In
`some embodiments, additional multiplexers can be added for
`multiple electrode scanning. In other embodiments additional
`capacitance-to-current converters may be added to allow par
`allel scanning of multiple sensor electrodes. The capacitance
`measurement circuits described herein may be used in various
`applications including, for example, single button applica
`tions, multiple buttons applications, linear and radial sliders,
`dual dimension touchpads and touchscreens, and multi-touch
`touchpad and touchscreen applications. Multi-touch touch
`pad and touchscreen systems are composed of a matrix of RX
`and TX electrodes, where the presence (e.g., touch) of a finger
`45
`(or other conductive object) is detected as a decrease in the
`mutual capacitance at the intersection of the TX-RX elec
`trodes.
`Embodiments of the present invention allow for measure
`ment of two or more electrodes mutual and self capacitance
`separately. Capacitance measurement can be performed with
`a single pair of electrodes or with the use of a multiple elec
`trode system. Two electrodes situated close to each other are
`shown at FIG.1, where C 101 and C102 are electrode self
`capacitances, and C, 103 is the mutual capacitance between
`the two electrodes E 104 and E 105.
`There are various circuit implementations that may be used
`for performing capacitance measurement. FIG. 2 illustrates a
`self-capacitance circuit 200 that uses a charge accumulation
`technique to measure the capacitance C204. A charge accu
`mulation technique operates in the following way: initially
`the integration capacitor 203 is reset by turning on a reset
`signal for some time which sets switch 205 such that both
`ends of integration capacitor 203 are grounded. After reset,
`the switches 201 and 202 start operation in the two non
`overlapping phases, wherein Switch 201 when closed accu
`mulates charge onto C and wherein switch 202 when closed
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`allows that charged to be integrated onto C,
`203. As more
`charge is integrated onto integration capacitor C 203, the
`Voltage on C 203 starts increasing. The sensing capacitance
`may be determined by the number of switching cycles used to
`get the integrator capacitor Voltage to Some threshold value,
`Such as V/2 or a bandgap Voltage (V).
`With Such a charge accumulation technique, the Voltage on
`the integration capacitance rises exponentially with respect to
`time (said time can be measured by a count of the number of
`cycle it takes to reach the threshold value). This relationship
`can be linearized for measurement methods where capaci
`tance is calculated as a function of integration capacitor Volt
`age after a predefined number of cycles. Also, the mutual
`capacitance measurement scheme has some sensitivity to the
`sensor self capacitance, which decreases the measurement
`accuracy.
`FIG. 3 illustrates a block diagram of a capacitance mea
`surement circuit 300 for measuring mutual or self capaci
`tance, according to one embodiment of the present invention.
`The apparatus illustrated in FIG. 3 can be used for separately
`measuring mutual or self capacitances of a capacitance sen
`sor. In order to measure a mutual capacitance, the C. C. (of
`FIG. 1) capacitance influence should be excluded. This can be
`accomplished by charging and discharging the C. electrode
`from a low-impedance Voltage source and keeping the Volt
`age of the C. electrode close to constant to minimize the
`influence of its charge-discharge current. In order to measure
`the self-capacitance (of C or C) the Voltage change across
`C, should be kept to zero to minimize the influence of this
`capacitance on the measurement results.
`The capacitance measurement circuit 300 can be separated
`into two parts: the Switching capacitor front-end capacitance
`to-current converter 301, and the back-end current-to-digital
`value converter 302, as illustrated in FIG. 3. In the following
`description, the front-end and back-end circuits are described
`separately. A Switching capacitor front-end converts the sens
`ing capacitance to current pulses. The back-end system aver
`ages the current and converts it into readable digital values.
`The circuits described herein are based on a Switching capaci
`tor technique in capacitance-to-current converter circuits.
`FIGS. 4A, 4B, 5A and 5B show different embodiments for
`a capacitance to current converter for mutual capacitance
`measurement. In the referenced figures, a voltage buffer 401
`resides between the integration capacitor C, 406 and the
`switches 402,404 connecting to the mutual electrodes of the
`capacitance-to-current. It should be noted that the integration
`capacitor C, 406 is considered as part of the current mea
`Surement system and shown here for ease of explanation. The
`integration capacitor 406 can be connected between the con
`verter output and a fixed potential net, for example, GND and
`V, as illustrated in FIGS. 4A, 4B, 5A and 5B, respectively.
`The operation of the circuit may be described in several
`stages, which are repeated in cycle. Table 1 contains the
`Switching sequence of Switches for the circuits shown in
`FIGS. 4A and 4B.
`
`TABLE 1
`
`Switching sequence of switches shown in FIGS. 4A and 4B.
`
`Switch Switch Switch Switch
`4O2
`403
`404
`40S
`
`Stage
`
`Ucine, Uce1: Uce2. Ucm
`
`1
`2
`
`3
`
`OFF
`ON
`
`OFF
`OFF
`
`OFF
`ON
`
`OFF
`
`OFF
`
`OFF
`
`OFF
`OFF
`
`UC = Uo
`U = 0, U = U =
`c. Ubuf
`OFF U = 0, U1 = U2 = U.
`
`DELL EXHIBIT 1025 PAGE 22
`
`

`

`US 8,319,505 B1
`
`5
`TABLE 1-continued
`
`6
`a larger charge quantum being moved in each phase and an
`increase in the speed of the integration capacitor 406 voltage
`rising. The current measurement circuit may not keep a volt
`age on the integration capacitor 406 constant in this embodi
`ment.
`The circuit embodiments illustrated in FIGS. 7A, 7B, 8A,
`and 8B may be used to keep voltage on C, 406 constant. The
`difference between the circuit embodiments illustrated in
`FIGS. 7A, 7B, 8A, and 8B, versus those illustrated in FIGS.
`4A, 4B, 5A, and 5B, is that the left terminal of C 103 is
`connected to the fixed voltage source V, in FIGS. 7A, 7B.
`8A and 8B. In FIGS. 7A, 7B, 8A and 8B the variable buffer
`output voltage of an analog buffer 701 is coupled to the right
`terminal of C 103 and in FIGS. 4A, 4B, 5A and 5B buffer
`401 is coupled with the left terminal of C, 103. Only the
`switch 702 connection is changed on the circuits illustrated in
`FIGS. 7A, 7B, 8A, and 8B.
`The switching sequence of the switches illustrated in FIGS.
`7A and 7B is shown in Table 3.
`
`TABLE 3
`
`Switching sequence of switches in FIGS. 7A and 7B.
`
`Switch Switch Switch Switch
`702
`703
`704
`705
`
`Stage
`
`Ucine, Uce1: Uce2. Ucm
`
`OFF
`ON
`
`OFF
`OFF
`
`OFF
`ON
`
`OFF
`
`OFF
`
`OFF
`
`OFF
`OFF
`
`ON
`OFF
`
`OFF
`OFF
`
`2
`
`3
`
`4
`5
`
`OFF
`OFF
`
`UC = Uo
`-UC = Uva - UCine,
`Uce = Uc, :
`Usual ce2 :
`Uva
`Ucn = Uvda - UCine
`Cce1 = UCUCe2 = Uva
`ON UC = UC = UC1,UC2 = 0
`OFF
`UC = Uce.UCe2 = 0
`
`OFF
`
`The switching sequence of the switches illustrated in FIGS.
`8A and 8B is shown in Table 4.
`
`TABLE 4
`
`Switching sequence of switches in FIGS. 8a and 8b
`
`Switch Switch Switch Switch
`702
`703
`704
`705
`
`Stage
`
`Ucine, Uce1: Uce2. Ucm
`
`1
`2
`3
`4
`
`5
`
`OFF
`OFF
`OFF
`ON
`
`OFF
`ON
`OFF
`OFF
`
`OFF
`ON
`OFF
`OFF
`
`OFF
`
`OFF
`
`OFF
`
`UC = Uo
`OFF
`OFF Uc = Use= Uc = Uce
`OFF
`UC = UC = Uce
`ON -UC = Up - UCUC1 =
`Ucial ce2 : Uva
`OFF UC = O.UC1 = UCUC2 =
`U i
`
`The stages from 2 to 5 are performed in cycles. As a result,
`the average current flowing out of the C, 406 capacitor for
`the circuits on FIGS. 7A, 7B, 8A, and 8B may be calculated
`by Equation 3:
`
`Switching Sequence of Switches shown in FIGS. 4A and 4B.
`
`Switch
`4O2
`
`Switch Switch Switch
`403
`404
`40S
`
`Stage
`
`Ucine Uce1: Uce2. UC
`
`4
`5
`
`OFF
`OFF
`
`ON
`OFF
`
`OFF
`OFF
`
`ON UC = UC = UCIUCe2 = 0
`OFF
`UC = Uce.UCe2 = 0
`
`Table 2 contains the Switching sequence of switches for the
`circuits shown in FIGS. 5A and 5B.
`
`10
`
`TABLE 2
`
`Switching sequence of switches shown in FIGS. 5A and 5B.
`
`15
`
`Switch
`402
`
`Switch Switch Switch
`403
`404
`40S
`
`Stage
`
`Ucine Uce1: Uce2. UCn
`
`1
`2
`3
`4
`
`5
`
`OFF
`OFF
`OFF
`ON
`
`OFF
`
`OFF
`ON
`OFF
`OFF
`
`OFF
`
`OFF
`ON
`OFF
`OFF
`
`OFF
`
`UC = Uo
`OFF
`OFF Uc = Utr= Uc = Uce
`OFF
`UC = UC = Uce
`ON UC = O.UC1 = U.C.UC2 =
`Uci,
`OFF U = O.U. = tan-Uc.
`Ucint
`
`25
`
`30
`
`35
`
`The stages from 2 to 5 are performed in cycles. In effect, the
`circuits shown in FIGS. 4A and 4B may act as current sinks,
`and the circuits shown in FIGS.5A and 5B may act as current
`Sources in the respective embodiment. The integration
`capacitor C, 406 is external to the capacitance-to-current
`converter and is not part of the current measurement circuit.
`FIGS.6A and 6B illustrates one embodiment of the opera
`tion phases for the circuits shown in FIGS. 4A and 4B, respec
`tively. During the first phase (FIG. 6A), both ends of the C.
`103 are connected to voltage buffer 401. During the second
`phase (FIG. 6B), the left C terminal is grounded and the right
`terminal is connected to the integration capacitor C, 406.
`For both circuits, an averaged absolute current sink/Source
`(Is) value can be calculated by Equation 1:
`(1)
`Isfiy Ucini'C,
`where, f is the Switching frequency of phases 2-5 repeating.
`It should be noted that the capacitance of C. electrode 102 is
`shunted by switch 402 or 403 in each operation phase and
`does not have an impact on the output current. The capaci
`tance of the C. electrode 101 has a potential equal to U
`during both charge transfer stages and is not recharged
`between different operation phases. Therefore, the output
`current is determined by the value of C, 103 and the potential
`applied across it.
`A special case of the capacitance-to-current converter
`operation is now considered, when it is loaded by stand-alone
`integration capacitor C, 406. In this case, the relationship
`between the Voltage change on U and the cycles count N
`has a nonlinear exponential character, as expressed in Equa
`55
`tion 2:
`
`40
`
`45
`
`50
`
`Uen Uen (1
`
`isit
`
`W
`
`C
`-N in
`(U8, St. Unt e C)
`
`2
`(2)
`
`60
`
`where, N is the quantity of conversion cycles and U" is the
`Voltage on the integration capacitor 406 at the initial time.
`The exponential character of this dependence is caused by
`the positive voltage feedback via buffer 401: increasing volt
`age on the integration capacitor 406 (when the capacitance
`to-current converter is configured as a current source) causes
`
`65
`
`(3)
`Is fraC
`For the given values off and V, parameters, the output
`current (Is) linearly depends on C, and is proportional to f.
`and V, in this embodiment. The change of current direction
`is done by a change of the Switches operation phases. If the
`current measurement Subsystem does not load the integration
`
`DELL EXHIBIT 1025 PAGE 23
`
`

`

`7
`capacitor C, 406, a Voltage on this capacitor changes linearly
`with the number of cycles N, as expressed in Equation 4:
`
`US 8,319,505 B1
`
`8
`TABLE 6
`
`Switching sequence of Switches illustrated in FIGS. 10A, 10B.
`
`Stage
`
`Switch
`902
`
`Switch Switch Switch
`903
`904
`905
`
`Ucine Uce1: Uce2. Ucm
`
`(4)
`
`Uent – Uva ( -N. isit
`
`C
`
`A similar Equation 5 is used for describing the circuits
`illustrated in FIGS. 8A and 8B:
`
`10
`
`1
`2
`3
`4
`5
`
`OFF
`ON
`OFF
`OFF
`OFF
`
`OFF
`OFF
`OFF
`ON
`OFF
`
`OFF
`ON
`OFF
`OFF
`OFF
`
`UC = Uo
`OFF
`OFF UCI = UC2 = Up.UC = 0
`OFF UC1 = UC2 Uta.U = 0
`ON
`U1 = U
`OFF U1 = UC = UC2.UC = 0
`
`UN = N Udd :
`
`Cn
`Cint
`
`Stages 2 through 5 are performed in cycles. As a result, the
`average current flowing out of capacitor C for the circuits
`illustrated in FIGS. 9A and 9B may be described by Equation
`6:
`
`(5)
`
`15
`
`(6)
`Isf, UCC-1
`The average current flowing into C, capacitor for the
`circuits illustrated in FIGS. 10A and 10B may be described by
`Equation 7:
`(7)
`Is f(Uvai-Ucin) Cel
`The potential difference on electrode capacitor C, 103 is
`equal to approximately Zero during the stages of charge trans
`fer and does not have an impact on the measurement in this
`embodiment. The C. electrode 102 capacitance is switched
`off by switches 902 and 904 during the stages of operation. In
`this case, the relationship between the Voltage change on
`U, and the cycle count N has a nonlinear exponential char
`acter for the circuits illustrated in FIGS. 9A and 9B, inaccord
`with Equation 8:
`
`Uen Uent (1
`
`(8)
`
`Equation 9 similarly describes the circuits illustrated in
`FIGS. 10A and 1 OB:
`
`25
`
`30
`
`35
`
`The mutual capacitance circuit embodiments described
`previously may be used for self-capacitance measurement
`with minimal hardware changes by routing the buffer signal
`to the left-side switches. To do this, the switched voltages may
`be adjusted in Such a way that the Voltage change on the
`mutual capacitance C is equal to Zero between different
`phases. In other circuit configurations, the Voltage on C is
`kept constant but the Voltage on C, is varied. In the circuit
`embodiments illustrated in FIGS. 7A, 7B, 8A, and 8B, the
`Voltage on C is varied and the Voltage change on C, is kept
`COnStant.
`FIGS. 9A and 9B illustrate embodiments of a capacitance
`to current sink converter for self capacitance measurement.
`As previously noted, the integration capacitor C, 406 is
`considered part of the current measurement system and is
`shown here for ease of explanation. The integration capacitor
`406 can be connected between the converter output and any
`fixed potential net, for example, GND and V, as illustrated
`in FIGS. 9A and 9B respectively. Alternatively, the integra
`tion capacitor 406 can be connected between the converter
`output and other fixed potentials.
`The Switching sequence of Switches illustrated in the cir
`cuit of FIGS. 9A and 9B is shown in Table 5.
`
`40
`
`TABLE 5
`
`Switching sequence of switches illustrated in FIGS. 9A. 9B.
`
`45
`
`Stage
`
`Switch Switch Switch Switch
`902
`903
`904
`905
`
`Ucine, Uce1: Uce2. Ucm
`
`1
`2
`3
`4
`5
`
`OFF
`OFF
`OFF
`ON
`OFF
`
`OFF
`ON
`OFF
`OFF
`OFF
`
`OFF
`ON
`OFF
`OFF
`OFF
`
`UC = Uo
`OFF
`OFF Uce = UCe2 = 0.UC = 0
`OFF Uce = UCe2 = 0.UC = 0
`ON U = U = U2U = 0
`OFF
`U1 = U
`
`50
`
`FIGS. 10A and 10B illustrate embodiments of a capaci
`55
`tance to current Source converter for self capacitance mea
`surement. As previously noted, the integration capacitor C.
`406 is considered part of the current measurement system and
`is shown here for ease of explanation. The integration capaci
`tor 406 can be connected between the converter output and
`any fixed potential net, for example, GND and V, as illus
`trated in FIGS. 10A and 10B respectively. Alternatively, the
`integration capacitor 406 can be connected between the con
`verter output and other fixed potentials.
`The switching sequence of switches in FIGS. 10A and 10B
`is shown in Table 6.
`
`65
`
`60
`
`C
`-N el
`Uent – Usa i - 8 c)
`
`(9)
`
`Various alternative variants of the conversion circuits
`described above may be used. Alternative conversion circuits
`include integration circuits such as time measurement of the
`integration capacitor Voltage threshold crossing, current inte
`grations with an operational amplifier as a current integrator.
`Alternative conversion circuits include analog-to-digital cir
`cuits such as a current-to-voltage convers