Trials@uspto.gov
`571-272-7822
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`Paper 12
`Date: September 10, 2020
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`PACT XPP SCHWEIZ AG,
`Patent Owner.
`____________
`
`IPR2020-00537
`Patent 7,928,763 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, KEN B. BARRETT, and
`CHRISTOPHER L. OGDEN, Administrative Patent Judges.
`
`BARRETT, Administrative Patent Judge.
`
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`571-272-7822
`
`
`
`
`
`
`
`Paper 12
`Date: September 10, 2020
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`PACT XPP SCHWEIZ AG,
`Patent Owner.
`____________
`
`IPR2020-00537
`Patent 7,928,763 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, KEN B. BARRETT, and
`CHRISTOPHER L. OGDEN, Administrative Patent Judges.
`
`BARRETT, Administrative Patent Judge.
`
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`IPR2020-00537
`Patent 7,928,763 B2
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`I.
`
`INTRODUCTION
`Background and Summary
`A.
`Intel Corporation (“Petitioner”)1 filed a Petition requesting inter
`
`partes review of U.S. Patent No. 7,928,763 B2 (“the ’763 patent,”
`Ex. 1003). Paper 2 (“Pet.”). The Petition challenges the patentability of
`claims 19 and 492 of the ’763 patent. PACT XPP Schweiz AG (“Patent
`Owner”)3 filed a Preliminary Response to the Petition. Paper 6 (“Prelim.
`Resp.”). As authorized by the Board, Petitioner filed a Reply to the
`Preliminary Response (Paper 7, “Pet. Reply”) and Patent Owner filed a
`Sur-Reply (Paper 10, “PO Sur-Reply”).
`
`An inter partes review may not be instituted “unless . . . the
`information presented in the petition . . . shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of the
`claims challenged in the petition.” 35 U.S.C. § 314(a) (2018). Having
`considered the arguments and evidence presented by Petitioner and Patent
`Owner, we determine that Petitioner has not demonstrated a reasonable
`likelihood of prevailing on at least one of the challenged claims of the ’763
`patent. Accordingly, we do not institute an inter partes review of the
`challenged claims.
`
`
`1 Petitioner identifies Intel Corporation as the real party-in-interest. Pet. 2.
`2 As discussed below in Section II.A, the Petition also has grounds directed
`to claims 1–3, 9–14, 16–18, 20–22, 24, 26, 30–33, 39–44, 46–48, 50–52, 54,
`56, and 60. However, because those claims have been statutorily disclaimed
`by Patent Owner, they are treated as if they never were part of the ’763
`patent. See Ex. 2002, 2.
`3 Patent Owner identifies PACT XPP Schweiz AG (formerly known as
`Scientia Sol Mentis AG) as the real party-in-interest. Paper 3, 1.
`2
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`Related Proceedings
`B.
`One or both parties identify, as matters involving or related to
`
`the ’763 patent: PACT XPP Schweiz AG v. Intel Corp., No. 19-cv-00267 (D.
`Del. Feb. 7, 2019); PACT XPP Schweiz AG v. Intel Corp., No. 19-cv-00273
`(W.D. Tex. April 23, 2019); Intel Corp. v. PACT XPP Schweiz AG, No. 19-
`cv-02241 (N.D. Cal. April 25, 2019); and PACT XPP Schweiz AG v. Intel
`Corp., No. 1:19-cv-010064 (D. Del. May 30, 2019). Pet. 2; Paper 3, 1–2.
`
`The ’763 Patent
`C.
`The ’763 patent is titled “Multi-Core Processor System,” and “relates
`
`to a cell element field and a method for operating same . . . [and] in
`particular to reconfigurable data processing architectures.” Ex. 1003, code
`(54), 1:23–25. According to the patent, such architectures have certain
`advantages and off-setting disadvantages, and that “[i]t is desirable to design
`and use the reconfigurable architecture in such a way that even those data
`processing steps which are typically particularly suitable for being executed
`using sequencers are executable particularly rapidly and efficiently.” Id.
`at 1:61–2:9.
`[I]t is possible to construct a sequencer structure in a cell
`element field by providing a dedicated control connection
`controlled by function cells in a dedicated manner between
`function cell and function cell means and memory cell and/or
`memory cell means with only two elements connected by
`suitable buses without requiring additional measures and/or
`design changes otherwise.
`Id. at 3:19–24. Figure 1 of the ’763 is reproduced below.
`
`
`4 Patent Owner identified the case as “19-1066.” Paper 3, 2 (underlining
`added). We understand that to contain a typographical error.
`3
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`Id., Fig. 1. Figure 1 shows “a cell element field 1 for data processing [that]
`includes function cell means 2 for execution of arithmetic and/or logic
`functions and memory cell means 3 for receiving, storing and/or outputting
`information, [and] a control connection 4 connecting function cells 2 to
`memory cells 3,” and “interface circuit for communication with external
`load logic 6.” Id. at 7:31–32, 7:47–60. “The connections may be configured
`by switching bus systems 5 as necessary.” Id. at 7:55–56.
`
`Illustrative Claim
`D.
`The challenged claims of the ’763 patent, claims 19 and 49, depend,
`
`respectively, from disclaimed independent claims 1 and 31. Independent
`claim 1 and dependent claim 19, reproduced below, are illustrative.
`1. A multi-processor chip, comprising:
`a plurality of data processing cells, each adapted for
`sequentially executing at least one of algebraic and logic
`functions and having:
`at least one arithmetic logic unit;
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`at least one data register file;
`a program pointer; and
`at least one instruction decoder;
`a plurality of memory cells;
`at least one interface unit;
`at least one Memory Management Unit (MMU); and
`a bus system for interconnecting the plurality of data processing
`cells, the plurality of memory cells, and the at least one
`interface unit;
`wherein the bus system is adapted for programmably
`interconnecting at runtime at least one of data processing
`cells and memory cells with at least one of memory cells
`and one or more of the at least one interface unit.
`
`19. The multi-processor chip according to claim 1, wherein
`at least one of the memory cells is adapted to store data
`in a non-volatile manner.
`Ex. 1003, 13:2–20, 14:13–15.
`
`
`
`Evidence
`E.
`Petitioner relies on the following references:
`Reference
`
`US 5,197,140; filed Nov. 17, 1989; issued Mar. 23, 1993
`(“Balmer”)
`US 5,761,523; filed June 7, 1995; issued June 2, 1998
`(“Wilkinson”)
`Takashi Miyamori & Kunle Olukotun, A Quantitative
`Analysis of Reconfigurable Coprocessors for Multimedia
`Applications, PROCEEDINGS, IEEE SYMPOSIUM ON FPGAS
`FOR CUSTOM COMPUTING MACHINES, date of conference
`April 17, 1998 (“Miyamori”)5
`
`Exhibit No.
`
`1005
`
`1007
`
`1009
`
`
`5 Patent Owner disputes the status of Miyamori as a prior art printed
`publication. Prelim. Resp. 30–35. For reasons discussed below, disposition
`of this case does not require us to reach that issue.
`5
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`Reference
`
`John L. Hennessy & David A. Patterson, COMPUTER
`ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE
`INTERFACE (2d. ed. 1998) (“Hennessy”)
`
`Exhibit No.
`
`1012
`
`Petitioner also relies on the Declaration of Dr. Pinaki Mazumder
`
`(Ex. 1001) in support of its arguments.
`
`Asserted Grounds of Unpatentability
`F.
`Petitioner asserts that the challenged claims are unpatentable on the
`
`following grounds:
`Claim(s) Challenged
`19, 49
`19, 49
`19, 49
`
`Reference(s)/Basis
`Balmer
`Wilkinson, Hennessy
`Wilkinson, Hennessy, Miyamori
`
`35 U.S.C. §
`103(a)
`103(a)
`103(a)
`
`II. ANALYSIS
`A. Patent Owner’s Disclaimer of Claims 1–3, 9–14, 16–18, 20–22, 24, 26,
`30–33, 39–44, 46–48, 50–52, 54, 56, and 60
`Petitioner seeks inter partes review of claims 1–3, 9–14, 16–22, 24,
`
`26, 30, 31–33, 39–44, 46–52, 54, 56, 60 of the ’763 patent. Pet. 1. After the
`filing of the Petition, Patent Owner filed a statutory disclaimer of claims 1–
`3, 9–14, 16–18, 20–22, 24, 26, 30–33, 39–44, 46–48, 50–52, 54, 56, and 60.
`Ex. 2002, 2; see also Prelim. Resp. 2–3.
`
`Based on Federal Circuit precedent and our rules, we cannot institute
`a trial on claims that have been disclaimed and no longer exist. “The
`Federal Circuit has held consistently that claims disclaimed under § 253(a)
`should be treated as though they never existed.” Facebook, Inc. v. SKKY,
`LLC, Case CBM2016-00091, slip op. at 8 (PTAB Sept. 28, 2017) (Paper 12)
`
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`(expanded panel) (precedential) (citing Vectra Fitness, Inc. v. TWNK Corp.,
`162 F.3d 1379, 1383 (Fed. Cir. 1998) (“This court has interpreted the term
`‘considered as part of the original patent’ in section 253 to mean that the
`patent is treated as though the disclaimed claims never existed.”); Guinn v.
`Kopf, 96 F.3d 1419, 1422 (Fed. Cir. 1996); Genetics Inst., LLC v. Novartis
`Vaccines & Diagnostics, Inc., 655 F.3d 1291, 1299 (Fed. Cir. 2011)) (“[A]
`claim that ‘never existed’ [due to a statutory disclaimer] cannot form the
`basis for an interference.”). Recognizing that a disclaimed claim is treated
`as one that never existed, our rules state that “[n]o inter partes review will be
`instituted based on disclaimed claims.” 37 C.F.R. § 42.107(e) (2019).
`
`This is consistent with the statutory scope of review in an inter partes
`review, which is limited to claims in a patent. See 35 U.S.C. § 311(b) (“A
`petitioner in an inter partes review may request to cancel as unpatentable 1
`or more claims of a patent.”); 35 U.S.C. § 318(a) (“If an inter partes review
`is instituted and not dismissed under this chapter, the Patent Trial and
`Appeal Board shall issue a final written decision with respect to the
`patentability of any patent claim challenged by the petitioner.”).
`
`SAS does not mandate a different result. In SAS, the Supreme Court
`held that a decision to institute under 35 U.S.C. § 314 may not institute on
`less than all claims challenged in the petition. See SAS Inst., Inc. v.
`Iancu, 138 S. Ct. 1348, 1354, 1359–60 (2018). However, as discussed
`above, claims 1–3, 9–14, 16–18, 20–22, 24, 26, 30–33, 39–44, 46–48, 50–
`52, 54, 56, and 60 are treated as if they never existed and were never part of
`the ’763 patent. Therefore, those claims are no longer “claims challenged in
`the [P]etition.” Because the disclaimed claims were never part of the ’763
`patent, Petitioner cannot seek review of those claims, and we would not
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`issue a Final Written Decision on them even if we were to institute an inter
`partes review on any remaining challenged claims.
`
`Principles of Law
`B.
`Petitioner bears the burden of persuasion to prove unpatentability of
`
`the claims challenged in the Petition, and that burden never shifts to Patent
`Owner. Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375,
`1378 (Fed. Cir. 2015).
`
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of skill in the art; and (4) any objective evidence of obviousness
`or non-obviousness.6 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`C. The Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art, various factors
`
`may be considered, including the “type of problems encountered in the art;
`prior art solutions to those problems; rapidity with which innovations are
`made; sophistication of the technology; and educational level of active
`
`
`6 The parties have not directed our attention to any objective evidence of
`obviousness or non-obviousness.
`
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`workers in the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`(internal quotation marks and citation omitted).
`
`Petitioner, relying on its declarant’s testimony, asserts: “A [person of
`ordinary skill in the art] at the time of the alleged invention would have had
`at least a[n] M.S. degree in electrical engineering or computer engineering
`(or equivalent experience), and at least three years of experience with
`processor design and memory architecture.” Pet. 10 (citing Ex. 1001 ¶¶ 73–
`74). Patent Owner, at this stage, does not disagree or propose a different
`definition of the person of ordinary skill in the art.
`
`We determine that the definition offered by Petitioner comports with
`the qualifications a person would have needed to understand and implement
`the teachings of the ’763 patent and the prior art of record. Cf. Okajima v.
`Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (the prior art itself may
`reflect an appropriate level of skill in the art). For purposes of this decision,
`we apply Petitioner’s description of the person of ordinary skill in the art.
`
`D. Claim Construction
`In an inter partes review requested in a petition filed on or after
`
`November 13, 2018, we apply the same claim construction standard used in
`district courts, namely that articulated in Phillips v. AWH Corp., 415 F.3d
`1303 (Fed. Cir. 2005) (en banc). See 37 C.F.R. § 42.100(b) (2019).
`
`In applying that standard, claim terms generally are given their
`ordinary and customary meaning as would have been understood by a person
`of ordinary skill in the art at the time of the invention and in the context of
`the entire patent disclosure. Phillips, 415 F.3d at 1312–13. “In determining
`the meaning of the disputed claim limitation, we look principally to the
`intrinsic evidence of record, examining the claim language itself, the written
`
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`description, and the prosecution history, if in evidence.” DePuy Spine, Inc.
`v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006)
`(citing Phillips, 415 F.3d at 1312–17).
`
`Petitioner does not propose an explicit claim construction for any
`term, asserting that every term should be given its ordinary and customary
`meaning. Pet. 5. Patent Owner similarly does not propose an explicit claim
`construction for any term. On this record and for purposes of this decision,
`we determine that no claim terms require express construction.
`
`E.
`
`The Alleged Obviousness of Dependent Claims 19 and 49
`Over Balmer
`Petitioner alleges that dependent claims 19 and 49 of the ’763 patent
`
`would have been obvious over Balmer. See Pet. 44–45; see also id. at 17–32
`(Petitioner’s analysis of the limitations of underlying independent claims 1
`and 31). Claims 19 and 49 depend, respectively, from disclaimed
`independent claims 1 and 31 and, therefore, include all of the limitations of
`those underlying independent claims.
`1. Balmer (Ex. 1005)
`Balmer discloses a multi-processor system arranged as an image and
`
`graphics processor. Ex. 1005, code (57). “The processor is structured with
`several individual processors all having communication links to several
`memories [and a] crossbar switch serves to establish the processor memory
`links.” Id. “The entire image processor, including the individual processors,
`the crossbar switch and the memories, is contained on a single silicon chip.”
`Id. Figure 1 of Balmer is reproduced below.
`
`10
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`Figure 1 “show[s] an overall view of the elements of the image processing
`system.” Id. at 3:24–25. The image processing system includes “a set of
`parallel processors 100-103 and a master processor 12 connected to a series
`of memories 10 via a cycle-rate local connection network switch matrix 20
`called a crossbar switch.” Id. at 4:45–48. “Transfer processor 11
`communicates with external memory 15 via bus 21.” Id. at 5:4–5.
`
`Balmer’s Figure 4 is shown below.
`
`
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`11
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`Figure 4 “shows a more detailed view of [Figure 1] where the four parallel
`processors 100-103 are shown interconnected by communication bus 40 and
`also shown connected to memory 10 via crossbar switch matrix 20.” Id.
`at 5:62-66. “[E]ach parallel processor 100-103 has a particular global bus
`and a particular local bus to allow the processor access to the various
`memories.” Id. at 6:30–32. “This structure allows data from
`memories 10-0, 10-2, 10-3 and 10-4 to be distributed to any of the
`processors 100-103.” Id. at 6:49–51. “In operation, any processor can
`access any of a number of memories, while certain memories are dedicated
`to handling instructions for the individual processors.” Id. at 3:14–16.
`2. Discussion
`Disclaimed independent claim 1, from which challenged claim 19
`
`depends, recites, in pertinent part, “[a] multi-processor chip, comprising: a
`plurality of data processing cells . . . ; a plurality of memory cells; at least
`one interface unit; . . . and a bus system for interconnecting the plurality of
`data processing cells, the plurality of memory cells, and the at least one
`interface unit.” Ex. 1003, 13:2–16. Challenged dependent claim 19 adds to
`“[t]he multi-processor chip according to claim 1” the requirement that “at
`least one of the memory cells is adapted to store data in a non-volatile
`manner.” Id. at 14:13–15.7 The other challenged claim, dependent claim
`49, contains substantively similar pertinent language.8 See, e.g., Ex. 1003,
`
`
`7 “‘[N]on-volatile memory’ refers to a type of memory that will retain stored
`data even when the system’s power is shut off.” Ex. 1001 ¶ 143.
`8 Petitioner identifies, as a difference between the claim sets, the recitations
`of “the bus system is adapted for programmably interconnecting . . .” of
`independent claim 1 and “the bus system is adapted for dynamically
`interconnecting . . .” of independent claim 31. Pet. 28 (emphasis added).
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`14:61–63, 16:10–12 (Independent claim 31 reciting “a bus system for
`interconnecting the plurality of data processing cells, the plurality of
`memory cells, and the at least one interface unit”; Dependent claim 49
`reciting “[t]he multi-processor chip according to claim 31, wherein at least
`one of the memory cells is adapted to store data in a non-volatile manner.”).
`
`In other words, challenged dependent claims 19 and 49 call for a
`multi-processor chip comprising data processing cells, memory cells with at
`least one being adapted to store data in a non-volatile manner, an interface
`unit, and a bus system for interconnecting these elements. Patent Owner
`argues that Petitioner fails to make an adequate showing concerning the
`dependent claims’ further limitation on the independent claims, the
`limitation regarding a non-volatile memory. See, e.g., Prelim. Resp. 14–15.
`
`Petitioner asserts, for the claims’ recited multi-processor chip, that
`“Balmer discloses ‘[a] multiprocessor system’ whereby ‘[t]he processor is
`structured with several individual processors all having communication links
`to several memories,’” and that “Balmer’s invention is ‘contained on a
`single silicon chip.’” Pet. 17 (emphasis omitted; citing Ex. 1005, code (57);
`Ex. 1001 ¶ 89). Petitioner utilizes an annotated version of Balmer’s
`Figure 1, reproduced below, to explain its contentions regarding certain
`limitations.
`
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`Pet. 27; see also id. at 18, 23, 24. Shown above is Petitioner’s annotated
`version of Balmer’s Figure 1, an overall view of the elements of an image
`processing system. See Ex. 1007, 3:24–25. For the underlying independent
`claims, Petitioner maps Balmer’s parallel processors 100–103 (blue) to the
`recited “data processing cells,” memories 10 (purple) to the “memory cells,”
`transfer processor 11 (orange) to the “interface unit,” and crossbar switch 20
`and processor interconnection bus 409 (yellow) to the “bus system.” Pet. 18,
`23–24, 23–24 (annotating transfer processor 11 as pink, rather than orange),
`26–28.
`
`As mentioned, Petitioner identifies Balmer’s memories 10 as the
`recited “plurality of memory cells” of the independent claims. Pet. 23
`(citing Ex. 1005, 4:45–48; Ex. 1001 ¶ 99); see also Ex. 1001 ¶ 99
`(Petitioner’s expert, with emphasis omitted: “In my opinion, Balmer teaches
`this [plurality of memory cells] limitation. Specifically, Balmer teaches that
`
`
`9 Balmer identifies element 40 at least as “communication bus,” “processor
`interconnection bus,” “bus,” and “interprocessor communication link.” See,
`e.g., Ex. 1005, 4:67–5:1, 5:55, 20:35, 36:17–18.
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`its processors are ‘connected to a series of memories 10 via a cycle-rate local
`connection network switch matrix 20 called a crossbar switch.’”).
`Petitioner, also under the heading for the “plurality of memory cells”
`limitation, states: “Additionally, Balmer teaches that before being loaded
`for execution, instructions are ‘previously stored in an optical disc 5001 or a
`hard drive 5002’ memory.” Pet. 23 (citing Ex. 1005, 28:56–57). Petitioner
`does not elaborate here on the intended import of this statement and
`Dr. Mazumder does not include this statement in the cited paragraph 99 of
`his declaration. Id.; Ex. 1001 ¶ 99.
`
`For the limitation of dependent claims 19 and 49—“wherein at least
`one of the memory cells is adapted to store data in a non-volatile manner”—
`Petitioner asserts:
`Balmer teaches that “any type of arrangement of memory and
`memory capacities can be utilized with this invention.” See
`Ex. 1005, 15:30-41. And before being loaded for execution by
`Balmer’s parallel processors, instructions are “previously stored
`in an optical disc 5001 or a hard drive 5002” (Ex. 1005, 28:56-
`57), which are non-volatile memories.
`Pet. 44–45; see also Ex. 1001 ¶¶ 143–144 (Dr. Mazumder quoting the same
`and opining that a hard drive is non-volatile memory and that the “any type
`of . . . memory” statement means that Balmer “thus contemplates additional
`non-volatile memory for storing data.”). Petitioner also provides the
`following annotated version of Balmer’s Figure 50.
`
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`Pet. 45 (citing Ex. 1005, Fig. 50; Ex. 100 ¶ 143). Figure 50 “describes an
`imbedded application of the image system processor [ISP] 5000,” and
`includes Petitioner’s annotations of the image system processor (ISP) in red
`and optical disc 5001 and hard drive 5002 in purple. Ex. 1005, 28:43–56;
`see id. at 7:38 (referring to the “image system processor discussed herein”).
`
`We agree with Patent Owner’s argument that Petitioner has failed to
`adequately address the specific manner in which the subject dependent
`claims narrow the underlying independent claims. See, e.g., Prelim.
`Resp. 19 (“The Petition simply fails to address the optical disc and hard
`drive as part of the ‘memory cells’ when it analyzes the ‘bus system.’”).
`Although Petitioner points to Balmer’s disclosure of non-volatile memory in
`the form of an optical disc and hard drive, Petitioner does not explain
`adequately how or why those structures would become at least one of the
`on-chip memory cells identified in Petitioner’s mapping for the independent
`claims, namely the memories 10. Similarly, Petitioner does not adequately
`explain how the optical disc or hard drive are interconnected to the pertinent
`components via crossbar switch 20 or processor interconnection bus 40, the
`structures identified in Petitioner’s mapping for the bus system limitations of
`the independent claims.
`
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`We also do not find to be satisfactory Petitioner’s statement that
`
`“Balmer teaches that ‘any type of arrangement of memory and memory
`capacities can be utilized with this invention,’” Pet. 44 (quoting
`Ex. 1005, 15:30–41), or Dr. Mazumder’s conclusory opinion that the same
`quote indicates that Balmer “contemplates additional non-volatile memory
`for storing data,” Ex. 1001 ¶ 144.10 To the extent that Petitioner implies that
`a person of ordinary skill in the art would find that quote to be a teaching to
`utilize a non-volatile form for the identified on-chip memory, the argument
`is not persuasive. As Patent Owner points out, Prelim. Resp. 21–23, that
`quote is made in the context of Balmer’s discussion of Figure 17, “showing
`a particular layout of memory,” i.e. an arrangement, and referring to
`“particular memory sizes,” i.e. capacities, see Ex. 1005, 15:29–36. Neither
`Petitioner nor Dr. Mazumder adequately draw a logical tie of memory layout
`and size to the form of the memory being volatile or non-volatile.
`
`Petitioner has not shown a likelihood of prevailing in demonstrating
`that dependent claims 19 and 49 would have been obvious over Balmer.
`
`F.
`
`The Alleged Obviousness of Dependent Claims 19 and 49
`Over Wilkinson and Hennessy
`Petitioner alleges that dependent claims 19 and 49 of the ’763 patent
`
`would have been obvious over the combination of Wilkinson and Hennessy.
`See Pet. 78–79; see also id. at 55–71 (Petitioner’s analysis of the limitations
`of underlying independent claims 1 and 31). Like the ground discussed
`above, Patent Owner argues that Petitioner has failed to adequately address
`
`10 We consider this paragraph 144 of Dr. Mazumder’s declaration
`notwithstanding that Petitioner did not identify it as support for the
`arguments as to dependent claims 19 and 49. See Pet. 44–45 (citing
`paragraph 143 of Ex. 1001 but not paragraph 144).
`17
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`IPR2020-00537
`Patent 7,928,763 B2
`
`the specific non-volatile memory limitation of the challenged dependent
`claims. Prelim. Resp. 24–28.
`1. Wilkinson (Ex. 1007)
`Wilkinson discloses “[a] parallel array processor for massively
`
`parallel applications.” Ex. 1007, code (57). Each of “[e]ight processors on a
`single chip have their own associated processing element, significant
`memory, and I/O.” Id. Figure 11 is reproduced below.
`
`
`Figure 11 “is a block diagram of a scalable parallel processor chip where
`each PME [processor memory element] is a 16 bit wide processor with 32K
`words of local memory and there is I/O porting for a broadcast port which
`provides a controller-to-all interface.” Id. at 15:12–15. As shown in
`Figure 8 (not reproduced here), “the PME has its 32K by 16 bit main store in
`
`18
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`IPR2020-00537
`Patent 7,928,763 B2
`
`the form of two DRAM [dynamic random access memories] macros.” Id.
`at 26:25–27.
`
`Wilkinson also explains:
`An advantage of the APAP [Advanced Parallel Array
`Processor] concept is the ability to use DASD [direct-access
`storage device] associated with groups of PMEs. This APAP
`capability, as well as the ability to connect displays and
`auxiliary storage, is a by-product of picking MC bus structures
`as the interface to the external I/O ports of the PME Array.
`Thus, APAP systems will be configurable and can include card
`mounted hard drives selected from one of the set of units that
`are compatible with PS/2 or RISC/6000 units.
`Id. at 69:14–22.
`2. Hennessy (Ex. 1012)
`Hennessy is a book titled Computer Organization and Design: The
`
`Hardware/Software Interface. Hennessy discusses processor architecture
`and bus systems that interconnect processors with other processors, memory,
`and I/O.
`
`3. Discussion
`Petitioner asserts, for the challenged claims’ recited multi-processor
`
`chip, that “Wilkinson discloses a processor array node that includes ‘eight
`processors on a single chip’ that each ‘have their own associated processing
`element, significant memory, and I/O.’” Pet. 55 (citing Ex. 1007, code (57);
`Ex. 1001 ¶ 163). Wilkinson explains that a single processor and memory,
`along with other components, form a “processor memory element,” or
`“PME.” Ex. 1007, 7:43–51; see Pet. 56. For the “memory cell” limitation
`of independent claims 1 and 31, Petitioner asserts that the corresponding
`memory cell of Wilkinson is the memory included in the PME. Pet. 61.
`Petitioner argues:
`
`19
`
`
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`IPR2020-00537
`Patent 7,928,763 B2
`
`
`Wilkinson’s PMEs include memory cells. Ex. 1007, 7:43-51
`(each PME has “a single processor, memory and I/O capable
`system element or unit[.]”). More specifically, each PME
`includes “32K of 16 bit memory” “in the form of two DRAM
`macros.” Ex. 1007, 25:19-24, 26:25-27.
`Id. at 61. Petitioner states, still under the “a plurality of memory cells”
`limitation heading, “Wilkinson additionally discloses ‘card mounted hard
`drives[,]’ which are also a form of memory cell.” Id. at 62 (citing
`Ex. 1007, 69:19–22; Ex. 1001 ¶ 170); see also Ex. 1001 ¶ 170 (same).
`Neither Petitioner nor its expert elaborates here on the intended import of
`this statement beyond the assertion that Wilkinson discloses memory in the
`form of a hard drive. Pet. 62; Ex. 1001 ¶ 170.
`
`For the “bus system” limitation of the underlying independent claims,
`Petitioner again articulates its position as mapping the PME memory to the
`claimed “memory cells.” Pet. 65 (Petitioner arguing that “Wilkinson
`discloses a bus system that connects the PME processing cells to the PME
`memory cells and the BCI [broadcast and control interface].”)
`
`For the limitation of dependent claims 19 and 49—“wherein at least
`one of the memory cells is adapted to store data in a non-volatile manner”—
`Petitioner asserts:
`Wilkinson discloses the use of “card mounted hard drives[.]”
`Ex. 1007, 69:19-22. Such hard drives are non-volatile memory
`in which Wilkinson’s system stores data. Ex. 1001 ¶ 205.
`Id. at 79 (alteration in original); see also Ex. 1001 ¶ 205 (Dr. Mazumder:
`“Wilkinson discloses the use of ‘card mounted hard drives,’ and such hard
`drives are non-volatile memory, where Wilkinson’s multiprocessor system
`stores data.”).
`
`Thus, Petitioner asserts that Wilkinson discloses a memory adapted to
`store data in a non-volatile manner in the form of a hard drive. Petitioner,
`
`20
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`IPR2020-00537
`Patent 7,928,763 B2
`
`however, does not explain adequately how Wilkinson’s hard drive is, as
`required by claims 19 and 49, one of the memory cells mapped by Petitioner
`for the underlying independent claim, namely the PME memory cells, or
`why such a configuration would have been obvious. And, we agree with
`Patent Owner’s argument that Petitioner does not adequately explain how
`the hard drive is interconnected via the structure of Wilkinson that Petitioner
`identified as the recited “bus system for interconnecting the plurality of data
`processing cells, the plurality of memory cells, and the at least one interface
`unit.” See Prelim. Resp. 25 (quoting Ex. 1003, claims 1 and 31).
`
`Petitioner has not shown a likelihood of prevailing in demonstrating
`that dependent claims 19 and 49 would have been obvious over Wilkinson
`and Hennessy.
`
`G.
`
`The Alleged Obviousness of Dependent Claims 19 and 49
`Over Wilkinson, Hennessy, and Miyamori
`Petitioner adds Miyamori to the Wilkinson-Hennessy ground
`
`discussed immediately above, relying on Miyamori in an alternative theory
`pertaining to the bus limitation. See Pet. 83–84. Petitioner asserts that
`Miyamori discloses that each of the processors contains memory
`interconnected to all the processors via the bus system. Id. at 88; see also id.
`(referring to the processors’ RAM as “memories”). Petitioner’s proposed
`combination involves the substitution of Miyamori’s bus system for
`Wilkinson’s, and continues to rely on Wilkinson’s PME internal memory as
`the recited memory cells of the independent claims. Id. at 89–90. Petitioner
`does not rely on Miyamori regarding the limitation of dependent claims 19
`and 49 calling for at least one of the memory cells of the respective
`independent claim to be non-volatile. See id. at 91. As such, Petitioner does
`
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`IPR2020-00537
`Patent 7,928,763 B2
`
`not rely on Miyamori in a manner that cures the underlying defect of the
`Wilkinson-Hennessy ground.
`
`Petitioner has not shown a likelihood of prevailing in demonstrating
`that dependent claims 19 and 49 would have been obvious over Wilkinson,
`Hennessy, and Miyamori.
`
`III. CONCLUSION
`Petitioner has not demonstrated a reasonable likelihood of prevailing
`
`in showing the unpatentability of claims 19 and 49 of the ’763 patent.
`
`IV. ORDER
`For the foregoing reasons, it is
`
`ORDERED that that the Petition is denied as to the challenged claims,
`
`and no trial is instituted.
`
`
`22
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`IPR2020-00537
`P
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