United States Patent [19]
`Wilkinson et al.
`
`[54] PARALLEL PROCESSING SYSTEM HAVING
`ASYNCHRONOUS SIMD PROCESSING AND
`DATA PARALLEL CODING
`
`[75]
`
`Inventors: Paul Amba Wilkinson. Apalachin;
`James Warren Dieft'enderfer. Owego;
`Peter Michael Kogge, Endicott;
`Nicholas Jerome Schoonover. Tioga
`Center, all of N.Y.
`
`[73] Assignee: International Business Machines
`Corporation. Armonk. N.Y.
`
`[21] Appl. No.: 487,363
`Jun. 7, 1995
`
`[22] Filed:
`
`Related U.S. Application Data
`
`[62] Division of Ser. No. 233,210, Apr. 26, 1994, which is a
`continuation of Ser. No. 888,680, May 22, 1992, abandoned,
`which is a continuation-in-part of Ser. No. 611,594, Nov. 13,
`1990, abandoned, and Ser. No. 798,788, Nov. 27, 1991,
`abandoned.
`Int. CL 6
`[51]
`...................................................... G06F 15/80
`[52] U.S. Cl. ......................................... 395/800.2; 395/379
`[58] Field of Search ..................................... 395/375. 800.
`395/379. 800.2. 800.1. 800.11, 800.12.
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`800.22
`
`[56]
`
`References Cited
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`
`I IIII IIII II II IIII I llll llll I1I111111I11I111
`
`US005761523A
`[111 Patent Number:
`[45J Date of Patent:
`
`5,761,523
`Jun. 2, 1998
`
`OTHER PUBLICATIONS
`
`T.A. Kriz and M.J. Marple. "Multi-Port Bus Structure With
`Fast Shared Memory". IBM Technical Disclosure Bulletin.
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`
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`
`Primary Examiner-Richard L. Ellis
`Attorney, Agent, or Finn-Lynn L. Augspurger; David V.
`Rossi
`
`[57]
`
`ABSTRACT
`
`A parallel array processor for massively parallel applications
`is formed with low power CMOS with DRAM processing
`while incorporating processing elements on a single chip.
`Eight processors on a single chip have their own associated
`processing element. significant memory. and I/0 and are
`interconnected with a hypercube based. but modified. topol(cid:173)
`ogy. These nodes are then interconnected. either by a
`hypercube, modified hypercube, or ring. or ring within ring
`network topology. Conventional microprocessor MMPs
`consume pins and time going to memory. The new archi(cid:173)
`tecture merges processor and memory with multiple PMEs
`( eight 16 bit processors with 32K and I/0) in DRAM and has
`no memory access delays and uses all the pins for network(cid:173)
`ing. Each chip will have eight 16 bit processors. each
`processor providing 5 MIPs performance. I/0 has three
`internal ports and one external port shared by the plural
`processors on the chip. The scalable chip PME has internal
`and external connections for broadcast and asynchronous
`SThfD. MIMD and SIMlMD (SIMD/MThfD) with dynamic
`switching of modes. The chip can be used in systems which
`employ 32. 64 or 128.000 processors. and can be used for
`lower, intermediate and higher ranges. Local and global
`memory functions can all be provided by the chips
`themselves, and the system can connect to and support other
`global memories and DASD. The chip can be used as a
`microprocessor accelerator. in personal computer
`applications. as a vision or avionics computer system. or as
`workstation or supercomputer.
`
`4 Claims, 24 Drawing Sheets
`
`INTEL - 1007
`
`

`

`5,761,523
`Page 2
`
`U.S. P.IITENT DOCUMENTS
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`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 1 of 24
`
`5,761,523
`
`FIG.1 A
`Prior Art
`
`FPU
`
`SHIFT
`
`NORMALISE
`
`Z BUS
`
`I
`
`I MANTISSA
`I
`I ALU
`\
`{Y
`{xt
`.
`NORMALISE
`I I
`I
`ROUNDING
`I I
`I
`A REG
`
`~
`,,
`
`i,
`
`B REG
`C REG
`
`DATA BUS
`INTERFACE
`
`...
`~DIN BUS
`.
`"f T
`DOUT eus)
`,,,
`Ir)
`
`IEXPONENTII I Z BUS
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`\
`{x)-
`{Y(
`S REG
`I I
`I I
`CONSTANTS
`I I
`I I
`A REG
`
`DIN BUS /
`,,,
`(oouT BUS
`"f
`
`1.,A--
`"-
`-.
`
`B REG
`C REG
`
`{'). FPopcode
`
`I
`
`INSTRUCTION
`STREAMER
`
`INSTRUCTION ~
`
`PTR
`OPERAND REG
`I I
`I I
`SCHEDULER
`WORKSPACE ~
`f'--r
`PTR
`
`...
`/
`'-,,
`
`.
`)
`,,,
`
`4 KBYTE
`RAM
`
`vu-
`l'r A
`D
`D
`R
`E
`s
`s
`
`8
`u
`s
`
`D
`A
`T
`A
`
`B
`u
`s
`
`FIG.1A
`
`FlG.18
`
`FIG.1
`
`~"
`,,/1----"...,
`
`DBUS
`
`-"-._
`
`'-r-,..' INTERLACE - ✓
`/'\
`
`D
`I
`N
`
`B
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`
`z
`k:= 8
`u
`s
`
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`
`DATA REG
`
`IXI
`IYI
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`B REG
`C REG
`I I
`I I
`11'.,
`~ DATA IN REG
`DATA OUT REG
`DOUT BUS
`~ CHANNEL
`! I I I
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 2 of 24
`
`5,761,523
`
`u
`
`8
`u
`s
`
`I
`TIMERS
`{x}
`\
`
`ALU
`I
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`
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`
`CON FIGURA TlON
`REGISTER &
`
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`TIMING CONTROL ' ...
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`MEMORY
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`PTR REG
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`PTR REG
`
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`
`INPUT
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`
`OUTPUT
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`
`DATA REG - LINK
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`I LINKS I
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`- - --
`
`LINK 1
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`I
`
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`LINKS
`
`ADDRESS
`REGISTERS
`
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`INSTRUCTION FETCH ADDRESS
`CHANNEL ADDRESS
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`
`FIG.18
`Prior Art
`
`INTEL - 1007
`
`

`

`100
`
`APPLICATION
`PROCESSOR 0
`
`110
`
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`PROCESSOR 1
`
`120
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`
`140
`
`ADVANCED
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`
`150
`160
`170
`180
`
`FIG.4
`
`I 111 I 111 I 111 I 111 I,,, I,, .I,, 1 I 11 ii
`
`CMOS GA TE ARRAY
`
`SCALABLE
`PARALLEL
`PROCESSOR
`CHIP
`
`32K X
`DRAM
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`
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`
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`
`FIG.2
`
`~
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`00000000 0000000
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`ooooooo<t" o'oooooo-<
`00000000 00000000
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`-- ----P
`0 0 0 000 00 000 0~0 0 Orr- - -~
`00000000 0000 ooo ooo
`00000000 00000000 nnnn~n nnhon
`00000000 00000000
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`
`950
`
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`00000000 00000000
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`00000000 00000000
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`
`FIG.16
`
`975
`
`00001000 00000000
`00000000 00000000
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`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2,1998
`
`Sheet 4 of 24
`
`5,761,523
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 5 of 24
`
`5,761,523
`
`200
`
`APPUCATION
`PROCESSOR 0
`
`210
`
`APPLICATION
`PROCESSOR 1
`
`220
`
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`
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`ARRAY N
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`ARRAY 02
`
`250~
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`I
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`12so
`ARRAY 01
`I.---_,____ .---........_-I,.....__ __
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`270
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`ARRA y
`ARRAY 00
`PROCESSOR
`CONTROLLER &
`SYNCHRONIZER I
`I
`INTERFACE
`1--......... ----------11----..J-
`
`280
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`.
`
`• 300
`•
`
`290
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`
`240
`
`TEST/DEBUG
`DEVICE
`
`FIG.5
`
`SER u
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`INT
`FA
`CE
`
`-
`
`-
`
`HOST APPLICATION PROCESSOR
`
`usER PROGRAMsl-H
`
`PERFORMANCE & DEMO
`PROGRAMS
`
`COMPILE I EXECUTE
`I
`APPLICATION
`DEV LIB
`
`--
`
`RISC/6000 TEST & DEBUG MONITOR
`DEBUGGER
`PERFORMANCE MONITOR
`& ANALYSIS
`DIAGNOSTICS
`SIMULATOR
`ASSEMBLER /LINKER
`& LOADER
`
`TEST &
`i--, INTERFACE
`MONITOR
`
`-
`
`FIG.19
`
`ARRAY CTRLR
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`f4-
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`ARRAY l'F
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`I
`
`I
`
`INTEL - 1007
`
`

`

`~
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`8/4
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`AEW
`RTALS
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`µ
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`
`512 PROCESSORS
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`340
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`313
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`314
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`8 PROCESSORS
`
`EIGHT - 1 BYTE BIDI PORTS i
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`f
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`300
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`FIG.6
`
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`INTEL - 1007
`
`

`

`400
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`425
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`REGISTER
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`420
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`435
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`410
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`406
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`480
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`FIG.7
`
`465
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`INTEL - 1007
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`

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`
`FIG.8
`
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`
`~
`
`tit
`-...J
`0"-,
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`N w
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 9 of 24
`
`5,761,523
`
`500
`
`510
`
`501
`
`515
`
`521,.
`•
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`
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`
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`
`•
`
`575
`
`-z
`
`570
`
`FIG.9
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 10 of 24
`
`5,761,523
`
`+X
`
`+w PE•------
`
`-W
`
`-x
`
`-Y
`
`+z
`
`FIG.10
`
`+y
`
`j
`
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`
`( +y)
`
`INTER
`PE
`BUS
`L_
`
`81ST
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`
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`
`PE
`
`(-y)
`
`~
`
`-y
`
`+x
`
`PE
`
`( +x)
`
`'
`
`I
`
`PE
`
`{-x)
`
`-x
`FIG.11
`
`-z
`
`+z
`
`j
`
`'
`
`PE
`
`( +z)
`
`I-<•
`
`--
`
`1 1
`
`PE
`
`(-z)
`
`--
`
`-z
`
`EXTERNAL
`PORTS
`
`--
`
`+w
`
`1
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`
`(+w)
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`.;;
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`
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`EXTERNAL
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`
`• •
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`
`-
`
`(-w)
`
`I
`
`'
`-w
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 11 of 24
`
`5,761,523
`
`p-o~---------7
`I
`I
`ARRA y DIRECTOR
`I
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`I
`APPUCA TION
`I
`
`640
`
`CLUSTER
`
`PROCESSOR
`
`FAST 1/0 (ZIPPMER)
`620
`
`620
`
`600
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`APPLICATION
`
`PROCESSORS
`
`CLUSTER
`
`660
`
`SYNCHRONIZER
`
`CONTROLLER
`INTERFACE
`------ ____ .,....., I
`650
`1sc1
`I
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`_______ J
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`MCA
`
`605
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`ARRAY CLUSTERS
`
`605
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`0 1
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`
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`
`695
`
`MCA BACKPLANE
`
`FIG.1.2
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 12 of 24
`
`5,761,523
`
`CLKS · · · · · · · · · · · · · ·
`
`CONT'R
`
`Bl-DIRECTIONAL
`TRISTATE DRIVERS
`(CONTROLLER
`ENABLE)
`
`8 X 8 NODE
`CLUSTER
`
`WlTH x AND y
`PATHS DOTTED
`WlTH
`SYSTEM BUS
`AT EDGE
`
`. . .
`
`•
`
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`
`FIG.13A
`PE xO PE x1 PE x2 PE x3
`
`PE x12 PE x13 PE x14 PE x15
`
`SYSTEM
`BUS
`
`•
`
`•
`
`DRIVER
`
`FIG.138
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 13 of 24
`
`5,761,523
`
`700
`ZIPPER BUS
`
`710
`
`WORD
`
`770
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`wd i
`
`word i+1
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`word i+2
`
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`720
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`1, 1,x,y
`
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`
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`
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`
`NODE
`1,n,x,y
`
`780
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`
`....
`
`790
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`
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`
`NODE
`n,n,x,y
`
`FIG.14
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 14 of 24
`
`5,761,523
`
`Q
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`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 15 of 24
`
`5,761,523
`
`HOW WOULD A 16 ELEMENT SORT REPEAT THE PATTERN?
`STAG
`2 3
`E 1
`4 5 6
`7
`8 9 10
`0
`+
`•
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`1
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`11
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`do J == 0 to I
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`
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`
`else TARGET = PE#-2'- J
`
`FOR SORTING n DATA ELEMENTS (n E {2':i EN,2's # OF PE'Sl)
`do I = 0 to (log
`n) - 1
`2
`if (PE# /2 1
`J ) %2 = 0
`then TARGET = PE#+2 1
`send DATA to TARGET
`receive data store in TEMP (If data is not available - wait)
`.
`PE#
`~
`rf (2(( 21 + 1) %2) + (( 2,+ 1) %2) +1) %2 = 0
`then if TEMP < DATA then DATA = TEMP else NOP
`then if TEMP> DATA then DATA= TEMP else NOP
`end bothe do's
`
`FIG.17
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 16 of 24
`
`5,761,523
`
`HOST
`PROCESSOR ..:_
`
`J
`
`HOST
`MEMORY
`
`DATA AND
`COMMANDS
`
`APPLICATION PROCESSOR
`INTERFACE
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`
`ARRAY
`CONTROLLER
`
`CLUSTER
`CONTROLLER 0
`cc
`{PORT TYPE)
`
`CLUSTER
`CONTROLLER 1
`cc
`(NON-PORTED)
`
`.....
`
`CLUSTER
`CONTROLLER N
`cc
`
`/64+P DATA
`PORT
`
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`NORMAL
`/16+
`BROADCAST B'CAST
`& STA rus
`
`'
`
`'
`STATUS MONITOR
`SERIAL LOOP
`
`CLUSTER 0
`
`64 NODES
`
`(512 PME's)
`
`CLUSTER 1
`
`CLUSTER N
`
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`
`FlG.18
`
`COMMAND
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`
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`
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`........ -........ .-------------1,---------,
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`
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`.
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`CHANNEL
`DEVICES, DASO.
`DISPLAYS,
`GATEWAYS,
`ETC.)
`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 17 of 24
`
`5,761,523
`
`VECTORIZED
`APPLICATION
`DEVELOPER ...... HIGH ORDER
`LANG SOURCE
`
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`
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`
`INTEL - 1007
`
`

`

`U.S. Patent
`
`Jun.2, 1998
`
`Sheet 18 of 24
`
`5,761,523
`
`APPLICATION
`DEVELOPER
`
`·OR
`
`SEQUENTIAL
`FORTRAN
`SOURCE
`
`VECTORIZED
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`INTEL - 1007
`
`

`

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`...._,____~"----
`
`INTEL - 1007
`
`

`

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